KR100186759B1 - Heat radiating structure of ball grid array semiconductor package using solder ball as input-output - Google Patents
Heat radiating structure of ball grid array semiconductor package using solder ball as input-output Download PDFInfo
- Publication number
- KR100186759B1 KR100186759B1 KR1019950025172A KR19950025172A KR100186759B1 KR 100186759 B1 KR100186759 B1 KR 100186759B1 KR 1019950025172 A KR1019950025172 A KR 1019950025172A KR 19950025172 A KR19950025172 A KR 19950025172A KR 100186759 B1 KR100186759 B1 KR 100186759B1
- Authority
- KR
- South Korea
- Prior art keywords
- heat sink
- grid array
- bga
- ball grid
- input
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
본 발명은 솔더볼을 입출력 단자로 사용하는 볼 그리드 어레이(BGA: Ball Grid Array) 반도체 패키지의 열 방출구조에 관한 것으로, 저면에 다수의 솔더볼이 부착된 PCB기판 중앙부에 공간부를 형성하고, 그 저면으로 외부 노출형 히트싱크를 부착하며, 상기 히트싱크 상부에 직접 반도체 칩을 부착 시킴으로서 반도체 칩에서 발생되는 열을 히트싱크를 통하여 마더 보드(MOTHER BOARD)로 직접 방출되도록 하므로서 반도체 칩에서 방출되는 열을 보다 효과적으로 방출시킬수 있는 동시에 박형 패키지화 할 수 있는 볼 그리드 어레이 반도체 패키지에 관한 것이다.The present invention relates to a heat dissipation structure of a ball grid array (BGA) semiconductor package using solder balls as input / output terminals. The present invention relates to a bottom portion of a PCB substrate having a plurality of solder balls attached to a bottom surface thereof. By attaching an external exposed heat sink and attaching a semiconductor chip directly on top of the heat sink, the heat generated from the semiconductor chip is directly discharged to the motherboard through the heat sink, thereby allowing more heat to be emitted from the semiconductor chip. The present invention relates to a ball grid array semiconductor package that can be effectively released and can be thinly packaged.
Description
제 1 도는 종래의 볼 그리드 어레이 반도체 패키지의 단면도1 is a cross-sectional view of a conventional ball grid array semiconductor package.
제 2 도는 본 발명의 볼 그리드 어레이 반도체 패키지의 단면도2 is a cross-sectional view of the ball grid array semiconductor package of the present invention.
제 3 도는 본 발명의 볼 그리드 어레이 반도체 패키지가 마더 보드에 실장된 상태를 도시한 단면도3 is a cross-sectional view showing a state in which the ball grid array semiconductor package of the present invention is mounted on a motherboard
제 4 도는 본 발명의 볼 그리드 어레이 반도체 패키지의 열 방출구조로 사용되는 히트싱크의 단면도4 is a cross-sectional view of a heat sink used as a heat dissipation structure of the ball grid array semiconductor package of the present invention.
*도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10 : PCB기판 11 : 솔더볼10: PCB board 11: solder ball
12 : 공간부 20 : 반도체 칩12: space portion 20: semiconductor chip
30 : 히트싱크 41,42 : 접착수단30: heat sink 41, 42: bonding means
50 : 골드 와이어 60 : 수지 봉지재50: gold wire 60: resin encapsulant
70 : 마더 보드(MOTHER BOARD)70: motherboard (MOTHER BOARD)
본 발명은 솔더볼을 입출력 단자로 사용하는 볼 그리드 어레이(BGA: Ball Grid Array)반도체 패키지의 열 방출구조에 관한 것으로, 더욱 상세하게는 PCB기판 중앙부에 공간부를 형성하고, 그 저면으로 외부 노출형 히트싱크를 부착하며, 상기 히트싱크 상부에 직접 반도체 칩을 부착 시킴으로서 반도체 칩에서 발생되는 열을 히트싱크를 통하여 마더 보드(MOTHER BOARD)로 직접 방출되도록 하므로서 반도체 칩에서 방출되는 열을 보다 효과적으로 방출시킬수 있는 볼 그리드 어레이 반도체 패키지에 관한 것이다.The present invention relates to a heat dissipation structure of a ball grid array (BGA) semiconductor package using solder balls as input / output terminals, and more particularly, to form a space in a center portion of a PCB substrate and to expose an externally exposed heat to the bottom thereof. By attaching the sink and attaching the semiconductor chip directly on the heat sink, the heat generated from the semiconductor chip is directly discharged to the motherboard through the heat sink, thereby effectively dissipating heat emitted from the semiconductor chip. A ball grid array semiconductor package.
일반적인 볼 그리드 어레이 반도체 패키지는 직접화한 반도체 칩의 전기적 회로를 출력시키는 단자를 볼로 구성하여 많은 수량의 초다핀을 갖게 한 것으로, 이러한 종래의 볼 그리드 어레이 반도체 패키지의 열 방출구조는 제 1 도에 도시된 바와같이 PCB기판(1) 하부에는 다수의 솔더볼(1a)을 부착하고, 상기 PCB기판(1) 상부에 반도체 칩(2)을 부착하며, 상기 반도체 칩(2)이 부착된 위치의 PCB기판(1)에는 다수의 PTH(1b)(Plated Through Hole;이하, 관통슬롯(1b)이라 한다)를 형성하여 반도체 칩(2)에서 발생된 열이 반도체 칩(2)의 저면과 부착된 전도성 수지(4)를 거쳐 PCB기판(1)에 형성된 다수의 관통슬롯(1b)을 통하여 PCB기판(1) 하부에 부착된 솔더볼(1a)을 경유하여 마더 보드로 방출되는 구조이다.A general ball grid array semiconductor package has a large number of ultra-fins by using a ball terminal configured to output an electrical circuit of a semiconductor chip, and the heat dissipation structure of the conventional ball grid array semiconductor package is shown in FIG. As shown, a plurality of solder balls 1a are attached to the lower portion of the PCB substrate 1, the semiconductor chip 2 is attached to the PCB substrate 1, and the PCB is attached to the position of the semiconductor chip 2. A plurality of plated through holes (hereinafter referred to as through slots 1b) are formed on the substrate 1 so that the heat generated from the semiconductor chip 2 adheres to the bottom surface of the semiconductor chip 2. It is a structure that is discharged to the motherboard via the solder ball (1a) attached to the lower portion of the PCB substrate 1 through a plurality of through slots (1b) formed on the PCB substrate 1 via the resin (4).
그러나, 이러한 종래의 볼 그리드 어레이(BGA) 반도체 패키지의 열 방출구조는 반도체 칩(2)에서 발생된 열이 방출되는 과정의 경로에서 많은 열 저항이 발생되므로 열 방출의 효과를 극대화 시키기에는 많은 어려움이 있었던 것이다.However, the heat dissipation structure of the conventional ball grid array (BGA) semiconductor package has a lot of difficulties in maximizing the effect of heat dissipation because a large amount of heat resistance is generated in the path of the heat dissipation generated in the semiconductor chip 2. This was there.
또한, 패키지의 구조상 반도체 칩(2)이 PCB기판(1) 상부에 부착됨에 의해 몰딩시 수지봉지재(6)의 높이가 높게 되므로 반도체 패키지의 전체적인 두께가 두꺼워지는 단점을 가지고 있는 것이다.In addition, since the height of the resin encapsulant 6 is increased during molding because the semiconductor chip 2 is attached to the PCB substrate 1 on the structure of the package, the overall thickness of the semiconductor package becomes thick.
본 발명의 목적은 이와같은 종래의 문제점을 해소하기 위해 발명된 것으로, 반도체 칩을 외부로 노출된 히트싱크에 직접 부착시킴으로서, 반도체 칩에서 방출되는 열의 저항을 획기적으로 줄어 열 방출의 효과를 극대화 시킬수 있도록 된 솔더볼을 입출력 단자로 사용하는 볼 그리드 어레이(BGA) 반도체 패키지의 열 방출구조를 제공함에 있다.An object of the present invention is to solve the conventional problems, and by attaching the semiconductor chip directly to the heat sink exposed to the outside, it is possible to dramatically reduce the resistance of the heat emitted from the semiconductor chip to maximize the effect of heat release. The present invention provides a heat dissipation structure of a ball grid array (BGA) semiconductor package that uses solder balls as input / output terminals.
본 발명의 다른 목적은 PCB기판의 중앙부분에 상하부가 완전 관통되는 공간부를 형성하고, 그 저면으로 히트싱크를 부착하며, 상기 히트싱크의 상면에 반도체 칩을 부착함으로서, 즉 반도체 칩이 PCB기판의 공간부를 통하여 PCB기판의 내부에 위치되도록 부착됨으로서 수지 봉지재의 두께를 현저히 줄일수 있도록 된 솔더볼을 입출력 단자로 사용하는 볼 그리드 어레이 (BGA) 반도체 패키지를 제공함에 있다.Another object of the present invention is to form a space portion through which the upper and lower portions are completely penetrated in the central portion of the PCB, attaching a heat sink to the bottom surface thereof, and attaching a semiconductor chip to the upper surface of the heat sink, that is, the semiconductor chip is formed of the PCB substrate. The present invention provides a ball grid array (BGA) semiconductor package using solder balls as input / output terminals, which are attached to be spaced inside the PCB, thereby significantly reducing the thickness of the resin encapsulant.
이러한 목적을 달성하기 위한 본 발명의 구성은, 솔더볼을 입출력 단자로 사용하는 볼 그리드 어레이(BGA) 반도체 패키지를 구성함에 있어서, 저면에 다수의 솔더볼이 부착된 PCB기판에 반도체 칩이 부착되는 위치에 상하부가 완전 관통되는 공간부를 형성하고, 상기 공간부의 하부에 위치되도록 히트싱크를 PCB기판의 저면에 부착하며, 상기 히트싱크의 상면에 반도체 칩을 직접 부착한 것을 특징으로 하는 솔더볼을 입출력 단자로 사용하는 볼 그리드 어레이(BGA) 반도체 패키지의 열 방출구조이다.In order to achieve the above object, in the configuration of a ball grid array (BGA) semiconductor package using solder balls as input / output terminals, a semiconductor chip is attached to a PCB substrate having a plurality of solder balls attached to a bottom surface thereof. A solder ball is used as an input / output terminal, characterized by forming a space part through which the upper and lower parts are completely penetrated, attaching a heat sink to the bottom surface of the PCB substrate so as to be positioned below the space part, and attaching a semiconductor chip directly to the upper surface of the heat sink. Is a heat dissipation structure of a ball grid array (BGA) semiconductor package.
이하, 본 발명을 첨부도면을 참조하여 각 실시예를 보다 구체적으로 설명하면 다음과 같다.Hereinafter, each embodiment will be described in more detail with reference to the accompanying drawings.
저면에 다수의 솔더볼(11)이 부착된 볼 그리드 어레이(BGA) 용 PCB기판(10)에 반도체 칩(20)이 부착되는 위치에 상하부가 완전 관통되는 공간부(12)를 형성하고, 상기 공간부(12)의 하부로 일정크기의 히트싱크(30)를 부착시킨다. 이때, 히트싱크(30)의 재질은 열 전도율이 양호한 금속재등의 재질을 사용하고, 히트싱크(30)의 크기는 PCB기판(10)의 공간부(12) 보다는 큰 히트싱크(30)를 PCB기판(10)의 저면에 접착재 또는 양면접착테이프 등의 접착수단(42)으로 부착한다. 그리고, 상기 히트싱크(30)의 상면에 반도체 칩(20)을 에폭시등의 접착수단(41)을 사용하여 직접 부착 시키고, 상기 반도체 칩(20)과 PCB기판(10)을 골드 와이어(50)로 본딩시킨 다음, 그 외부를 수지 봉지재(60)로 몰딩하여 패키지를 완성한다.On the bottom surface of the PCB grid 10 for the ball grid array (BGA) to which a plurality of solder balls 11 are attached, a space portion 12 is formed in which the upper and lower portions are completely penetrated. The heat sink 30 of a predetermined size is attached to the lower part of the part 12. At this time, the material of the heat sink 30 is made of a material such as a metal material having a good thermal conductivity, the size of the heat sink 30 is larger than the space portion 12 of the PCB substrate 10 to the heat sink 30 PCB The bottom surface of the substrate 10 is attached by an adhesive means 42 such as an adhesive or a double-sided adhesive tape. Then, the semiconductor chip 20 is directly attached to the upper surface of the heat sink 30 by using an adhesive means 41 such as epoxy, and the semiconductor chip 20 and the PCB substrate 10 are gold wires 50. After bonding to, and then molded the outside with a resin encapsulant 60 to complete the package.
이와같은 구성을 갖는 본 발명의 볼 그리드 어레이(BGA) 반도체 패키지를 마더보드(70:MOTHER BOARD)에 실장시킨다. 이때, 상기 PCB기판(10) 하부에 부착된 히트싱크(30)가 마더보드(70)에 직접 부착되도록 함으로서 반도체 칩(20)에서 발생되는 열의 방출효과를 극대화 시킬수 있는 것이다. 즉, 상기 히트싱크(30)는 솔더볼(11)이 위치한 면에 부착되는 패키지로서 반도체 칩(20)에서 발생되는 열이 히트싱크(30)를 통하여 마더 보드(70)로 직접 방출되도록 하여 열 방출시 열 저항이 전혀 없도록하여 보다 효과적으로 열 방출이 될수 있는 것이다.The ball grid array (BGA) semiconductor package of the present invention having such a configuration is mounted on a motherboard 70 (MOTHER BOARD). In this case, the heat sink 30 attached to the lower portion of the PCB substrate 10 may be directly attached to the motherboard 70 to maximize the heat dissipation effect generated from the semiconductor chip 20. That is, the heat sink 30 is a package attached to the surface where the solder ball 11 is located so that heat generated from the semiconductor chip 20 is directly discharged to the mother board 70 through the heat sink 30. Since there is no thermal resistance at all, the heat can be released more effectively.
또한, 상기 히트싱크(30)의 상, 하부면(31)(32)에는 제 4도에 도시된 바와같이 상부면(31)에는 PCB기판(10)과의 접착강도를 높이기 위하여 흑색 또는 갈색 산화물(Black or Brown oxide)을 처리할 수 있으며, 또는 그라운드 본드(Ground Bond)를 위하여 실버 플레이팅(Silver Plating)을 할 수 있는 것이다. 또한, 상기 히트싱크(30)의 하부면(32)에는 패키지를 마더 보드(70)에 실장시 히트싱크(30)가 마더 보드(70)와 직접 솔더링이 가능하도록 하기 위하여 팔라디움(Pd)층을 형성할수 있으며, 또는 솔더 플레이팅 처리를 할수도 있는 것이다.In addition, the upper and lower surfaces 31 and 32 of the heat sink 30 have black or brown oxides on the upper surface 31 to increase the adhesive strength with the PCB substrate 10, as shown in FIG. It can handle black or brown oxide, or silver plating for ground bonds. In addition, a palladium (Pd) layer is formed on the lower surface 32 of the heat sink 30 so that the heat sink 30 can be directly soldered to the motherboard 70 when the package is mounted on the motherboard 70. It can be formed, or it can be solder plated.
그리고, 상기 히트싱크(30)의 높이(두께)는 패키지가 마더 보드(70)에 실장될때 솔더볼(11)이 타원형으로 찌그러 지면서 죠인트되는 높이(0.4mm)와 일치되도록 히트싱크(30)의 두께를 최대 0.4mm를 넘지 않도록 하면 바람직 한 것이다.And, the height (thickness) of the heat sink 30 is the thickness of the heat sink 30 to match the height (0.4mm) is joined to the solder ball 11 is deformed in an oval shape when the package is mounted on the motherboard 70 It is desirable to not exceed the maximum 0.4mm.
또한, 상기 히트싱크(30)를 PCB기판(10)의 저면에 접착하는 접착수단(42)으로는 접착재 또는 양면접착테이프로 된 접착테이프를 사용하여 그 접착 강도를 증대시키고, 나아가 계면박리 및 열적스트레스에 대한 변형을 효과적으로 방지할수 있는 것이다.In addition, the adhesive means 42 for adhering the heat sink 30 to the bottom surface of the PCB substrate 10 increases the adhesive strength by using an adhesive tape made of an adhesive material or a double-sided adhesive tape, and further, the interface peeling and thermal It can effectively prevent deformation of stress.
상기 반도체 칩(20)은 PCB기판(10)의 높이 보다 낮은 히트싱크(30) 상면에 부착 됨으로서 수지 봉지재(60)의 높이를 현저히 줄일수 있으므로 박형인 패키지로 할 수 있다.Since the semiconductor chip 20 is attached to the upper surface of the heat sink 30 lower than the height of the PCB substrate 10, the height of the resin encapsulant 60 may be significantly reduced, thereby making it a thin package.
이상의 설명에서 알수 있듯이 본 발명의 솔더볼을 입출력 단자로 사용하는 볼 그리드 어레이(BGA) 반도체 패키지의 열 방출구조에 의하면, 저면에 다수의 솔더볼이 부착되고, 외부 노출형 히트싱크가 저면 중간부에 위치되도록 부착되어 반도체 칩을 히트싱크 상면에 직접 부착시켜 열방출의 효과를 극대화 시킴은 물론, 패키지를 박형으로 할수 있는 등의 효과가 있다.As can be seen from the above description, according to the heat dissipation structure of the ball grid array (BGA) semiconductor package using the solder ball of the present invention as an input / output terminal, a plurality of solder balls are attached to the bottom, and an external exposed heat sink is located at the middle of the bottom. It is attached to the semiconductor chip directly attached to the heat sink to maximize the effect of heat dissipation, as well as to make the package thin.
Claims (9)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950025172A KR100186759B1 (en) | 1995-08-16 | 1995-08-16 | Heat radiating structure of ball grid array semiconductor package using solder ball as input-output |
| JP7352583A JP2727435B2 (en) | 1995-08-16 | 1995-12-28 | Thin ball grid array semiconductor package with externally exposed heat sink attached |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950025172A KR100186759B1 (en) | 1995-08-16 | 1995-08-16 | Heat radiating structure of ball grid array semiconductor package using solder ball as input-output |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR970013134A KR970013134A (en) | 1997-03-29 |
| KR100186759B1 true KR100186759B1 (en) | 1999-04-15 |
Family
ID=19423577
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950025172A KR100186759B1 (en) | 1995-08-16 | 1995-08-16 | Heat radiating structure of ball grid array semiconductor package using solder ball as input-output |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP2727435B2 (en) |
| KR (1) | KR100186759B1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100649878B1 (en) * | 2000-12-29 | 2006-11-24 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor package |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100474193B1 (en) * | 1997-08-11 | 2005-07-21 | 삼성전자주식회사 | BG Package and Manufacturing Method |
| KR20010057046A (en) * | 1999-12-17 | 2001-07-04 | 이형도 | Package substrate having cavity |
| KR20030066996A (en) * | 2002-02-06 | 2003-08-14 | 주식회사 칩팩코리아 | Ball grid array package with improved thermal emission property |
| CN100364076C (en) * | 2003-09-08 | 2008-01-23 | 日月光半导体制造股份有限公司 | Bridging chip package structure |
| CN103531549A (en) * | 2013-10-24 | 2014-01-22 | 桂林微网半导体有限责任公司 | Semiconductor chip packaging structure and packaging method |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61260699A (en) * | 1985-05-14 | 1986-11-18 | 三菱電線工業株式会社 | Electronic circuit apparatus |
| JP2660295B2 (en) * | 1988-08-24 | 1997-10-08 | イビデン株式会社 | Substrate for mounting electronic components |
| JP2958380B2 (en) * | 1990-03-12 | 1999-10-06 | 株式会社日立製作所 | Semiconductor device |
-
1995
- 1995-08-16 KR KR1019950025172A patent/KR100186759B1/en not_active IP Right Cessation
- 1995-12-28 JP JP7352583A patent/JP2727435B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100649878B1 (en) * | 2000-12-29 | 2006-11-24 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor package |
Also Published As
| Publication number | Publication date |
|---|---|
| KR970013134A (en) | 1997-03-29 |
| JPH09186272A (en) | 1997-07-15 |
| JP2727435B2 (en) | 1998-03-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100201380B1 (en) | Heat radiation structure of bga semiconductor package | |
| US5677566A (en) | Semiconductor chip package | |
| US6781242B1 (en) | Thin ball grid array package | |
| US6642610B2 (en) | Wire bonding method and semiconductor package manufactured using the same | |
| US6964888B2 (en) | Semiconductor device and method for fabricating the same | |
| US5241133A (en) | Leadless pad array chip carrier | |
| US7662672B2 (en) | Manufacturing process of leadframe-based BGA packages | |
| US20050077613A1 (en) | Integrated circuit package | |
| EP0563264B1 (en) | Leadless pad array chip carrier | |
| US6819565B2 (en) | Cavity-down ball grid array semiconductor package with heat spreader | |
| KR100186759B1 (en) | Heat radiating structure of ball grid array semiconductor package using solder ball as input-output | |
| KR20010056618A (en) | Semiconductor package | |
| KR100280083B1 (en) | Printed Circuit Board and Manufacturing Method of Printed Circuit Board and Semiconductor Package Using the Same | |
| KR100192758B1 (en) | Method of manufacturing semiconductor package and structure of the same | |
| KR100203932B1 (en) | BGA package having thermal emissive substrate attached to chip | |
| KR0119757Y1 (en) | Semiconductor package | |
| KR100260996B1 (en) | Array type semiconductor package using a lead frame and its manufacturing method | |
| KR100218633B1 (en) | Ball grid array package having a carrier frame | |
| KR0173930B1 (en) | Ball grid array for lead frame | |
| US6541844B2 (en) | Semiconductor device having substrate with die-bonding area and wire-bonding areas | |
| KR100225236B1 (en) | Bga semiconductor package | |
| KR100369501B1 (en) | Semiconductor Package | |
| KR100760953B1 (en) | BGA Semiconductor Package with Heatsink | |
| KR100237566B1 (en) | Semiconductor thin package | |
| KR0119755Y1 (en) | Semiconductor package |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| N231 | Notification of change of applicant | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20121212 Year of fee payment: 15 |
|
| FPAY | Annual fee payment |
Payment date: 20131213 Year of fee payment: 16 |
|
| LAPS | Lapse due to unpaid annual fee |