KR970013134A - Heat Dissipation Structure of Ball Grid Array (BGA) Semiconductor Package Using Solder Ball as Input / Output Terminal - Google Patents
Heat Dissipation Structure of Ball Grid Array (BGA) Semiconductor Package Using Solder Ball as Input / Output Terminal Download PDFInfo
- Publication number
- KR970013134A KR970013134A KR1019950025172A KR19950025172A KR970013134A KR 970013134 A KR970013134 A KR 970013134A KR 1019950025172 A KR1019950025172 A KR 1019950025172A KR 19950025172 A KR19950025172 A KR 19950025172A KR 970013134 A KR970013134 A KR 970013134A
- Authority
- KR
- South Korea
- Prior art keywords
- bga
- grid array
- ball grid
- heat sink
- heat dissipation
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 230000017525 heat dissipation Effects 0.000 title claims abstract description 15
- 229910000679 solder Inorganic materials 0.000 claims abstract 14
- 239000000758 substrate Substances 0.000 claims abstract 3
- 239000000853 adhesive Substances 0.000 claims 6
- 230000001070 adhesive effect Effects 0.000 claims 6
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims 3
- 239000002390 adhesive tape Substances 0.000 claims 2
- 239000004593 Epoxy Substances 0.000 claims 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical group [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims 1
- 229910052763 palladium Inorganic materials 0.000 claims 1
- 229910052709 silver Inorganic materials 0.000 claims 1
- 239000004332 silver Substances 0.000 claims 1
- 230000008646 thermal stress Effects 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
본 발명은 솔더볼을 입출력 단자로 사용하는 볼 그리드 어레이(BGA: Ball Grid Array) 반도체 패키지의 열방출구조에 관한 것으로, 저면에 다수의 솔더볼이 부착된 PCB기판 중앙부에 공간부를 형성하고, 그 저면으로 외부 노출형 히트싱크를 부착하며, 상기 히트싱크 상부에 직접 반도체 칩을 부착시킴으로써 반도체 칩에서 발생되는 열을 히트싱크를 통하여 마더 보드(MOTHER BOARD)로 직접 방출되도록 하므로서 반도체 칩에서 방출되는 열을 보다 효과적으로 방출시킬수 있는 동시에 박형 패키지와 할수 있는 볼 그리드 어레이 반도체 패키지에 관한 것이다.The present invention relates to a heat dissipation structure of a ball grid array (BGA) semiconductor package using solder balls as input / output terminals. The present invention relates to a heat dissipation structure of a PCB substrate having a plurality of solder balls attached to a bottom thereof. By attaching an external exposed heat sink and attaching a semiconductor chip directly on top of the heat sink, the heat generated from the semiconductor chip is discharged directly to the motherboard through the heat sink, thereby allowing more heat to be emitted from the semiconductor chip. The present invention relates to a thin-walled package and a ball grid array semiconductor package that can be effectively released.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제2도는 본 발명의 볼 그리드 어레이 반도체 패키지의 단면도,2 is a cross-sectional view of the ball grid array semiconductor package of the present invention,
제3도는 본 발명의 볼 그리드 어레이 반도체 패키지 가 마더 보드에 실장된 상태를 도시한 단면도,3 is a cross-sectional view showing a state in which the ball grid array semiconductor package of the present invention is mounted on a motherboard;
제4도는 본 발명의 볼 그리드 어레이 반도체 패키지의 열 방출구조로 사용되는 히트싱크의 단면도4 is a cross-sectional view of a heat sink used as a heat dissipation structure of the ball grid array semiconductor package of the present invention.
Claims (11)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950025172A KR100186759B1 (en) | 1995-08-16 | 1995-08-16 | Heat radiating structure of ball grid array semiconductor package using solder ball as input-output |
JP7352583A JP2727435B2 (en) | 1995-08-16 | 1995-12-28 | Thin ball grid array semiconductor package with externally exposed heat sink attached |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950025172A KR100186759B1 (en) | 1995-08-16 | 1995-08-16 | Heat radiating structure of ball grid array semiconductor package using solder ball as input-output |
Publications (2)
Publication Number | Publication Date |
---|---|
KR970013134A true KR970013134A (en) | 1997-03-29 |
KR100186759B1 KR100186759B1 (en) | 1999-04-15 |
Family
ID=19423577
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019950025172A KR100186759B1 (en) | 1995-08-16 | 1995-08-16 | Heat radiating structure of ball grid array semiconductor package using solder ball as input-output |
Country Status (2)
Country | Link |
---|---|
JP (1) | JP2727435B2 (en) |
KR (1) | KR100186759B1 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20010057046A (en) * | 1999-12-17 | 2001-07-04 | 이형도 | Package substrate having cavity |
KR100474193B1 (en) * | 1997-08-11 | 2005-07-21 | 삼성전자주식회사 | BG Package and Manufacturing Method |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100649878B1 (en) * | 2000-12-29 | 2006-11-24 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor package |
KR20030066996A (en) * | 2002-02-06 | 2003-08-14 | 주식회사 칩팩코리아 | Ball grid array package with improved thermal emission property |
CN100364076C (en) * | 2003-09-08 | 2008-01-23 | 日月光半导体制造股份有限公司 | Bridging chip package structure |
CN103531549A (en) * | 2013-10-24 | 2014-01-22 | 桂林微网半导体有限责任公司 | Semiconductor chip packaging structure and packaging method |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61260699A (en) * | 1985-05-14 | 1986-11-18 | 三菱電線工業株式会社 | Electronic circuit apparatus |
JP2660295B2 (en) * | 1988-08-24 | 1997-10-08 | イビデン株式会社 | Substrate for mounting electronic components |
JP2958380B2 (en) * | 1990-03-12 | 1999-10-06 | 株式会社日立製作所 | Semiconductor device |
-
1995
- 1995-08-16 KR KR1019950025172A patent/KR100186759B1/en not_active IP Right Cessation
- 1995-12-28 JP JP7352583A patent/JP2727435B2/en not_active Expired - Fee Related
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100474193B1 (en) * | 1997-08-11 | 2005-07-21 | 삼성전자주식회사 | BG Package and Manufacturing Method |
KR20010057046A (en) * | 1999-12-17 | 2001-07-04 | 이형도 | Package substrate having cavity |
Also Published As
Publication number | Publication date |
---|---|
KR100186759B1 (en) | 1999-04-15 |
JPH09186272A (en) | 1997-07-15 |
JP2727435B2 (en) | 1998-03-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP3627158B2 (en) | Low profile ball grid array semiconductor package and manufacturing method thereof | |
JP2570498B2 (en) | Integrated circuit chip carrier | |
JP2570499B2 (en) | Back ground of flip chip integrated circuit | |
US5646828A (en) | Thin packaging of multi-chip modules with enhanced thermal/power management | |
US6657311B1 (en) | Heat dissipating flip-chip ball grid array | |
JP2881575B2 (en) | Ball grid array semiconductor package with heat sink | |
JP4476482B2 (en) | Low profile ball grid array semiconductor package, integrated circuit, printed circuit board, processor system, method for manufacturing low profile ball grid array semiconductor package, and method for mounting semiconductor die | |
US6681482B1 (en) | Heatspreader for a flip chip device, and method for connecting the heatspreader | |
US6303992B1 (en) | Interposer for mounting semiconductor dice on substrates | |
KR20040009679A (en) | Stacked semiconductor module and manufacturing method thereof | |
US6560108B2 (en) | Chip scale packaging on CTE matched printed wiring boards | |
KR970013134A (en) | Heat Dissipation Structure of Ball Grid Array (BGA) Semiconductor Package Using Solder Ball as Input / Output Terminal | |
JPH0883865A (en) | Resin sealed semiconductor device | |
US20060103032A1 (en) | Die attach material for TBGA or flexible circuitry | |
JP2891426B2 (en) | Semiconductor device | |
JPH09331004A (en) | Semiconductor device | |
KR200254077Y1 (en) | A printed circuit board for a window chip scale package having copper lands for heat radiation | |
KR100203932B1 (en) | BGA package having thermal emissive substrate attached to chip | |
KR100216820B1 (en) | Bga semiconductor package | |
KR100218633B1 (en) | Ball grid array package having a carrier frame | |
US6541844B2 (en) | Semiconductor device having substrate with die-bonding area and wire-bonding areas | |
KR20020088300A (en) | Semiconductor package with heat spreader using cooling material | |
KR100612761B1 (en) | Chip scale stack chip package | |
KR100225236B1 (en) | Bga semiconductor package | |
Schueller et al. | New chip scale package with CTE matching to the board |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
N231 | Notification of change of applicant | ||
E902 | Notification of reason for refusal | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20121212 Year of fee payment: 15 |
|
FPAY | Annual fee payment |
Payment date: 20131213 Year of fee payment: 16 |
|
LAPS | Lapse due to unpaid annual fee |