KR970013134A - Heat Dissipation Structure of Ball Grid Array (BGA) Semiconductor Package Using Solder Ball as Input / Output Terminal - Google Patents

Heat Dissipation Structure of Ball Grid Array (BGA) Semiconductor Package Using Solder Ball as Input / Output Terminal Download PDF

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KR970013134A
KR970013134A KR1019950025172A KR19950025172A KR970013134A KR 970013134 A KR970013134 A KR 970013134A KR 1019950025172 A KR1019950025172 A KR 1019950025172A KR 19950025172 A KR19950025172 A KR 19950025172A KR 970013134 A KR970013134 A KR 970013134A
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bga
grid array
ball grid
heat sink
heat dissipation
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KR1019950025172A
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KR100186759B1 (en
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심일권
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황인길
아남산업 주식회사
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Priority to JP7352583A priority patent/JP2727435B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

본 발명은 솔더볼을 입출력 단자로 사용하는 볼 그리드 어레이(BGA: Ball Grid Array) 반도체 패키지의 열방출구조에 관한 것으로, 저면에 다수의 솔더볼이 부착된 PCB기판 중앙부에 공간부를 형성하고, 그 저면으로 외부 노출형 히트싱크를 부착하며, 상기 히트싱크 상부에 직접 반도체 칩을 부착시킴으로써 반도체 칩에서 발생되는 열을 히트싱크를 통하여 마더 보드(MOTHER BOARD)로 직접 방출되도록 하므로서 반도체 칩에서 방출되는 열을 보다 효과적으로 방출시킬수 있는 동시에 박형 패키지와 할수 있는 볼 그리드 어레이 반도체 패키지에 관한 것이다.The present invention relates to a heat dissipation structure of a ball grid array (BGA) semiconductor package using solder balls as input / output terminals. The present invention relates to a heat dissipation structure of a PCB substrate having a plurality of solder balls attached to a bottom thereof. By attaching an external exposed heat sink and attaching a semiconductor chip directly on top of the heat sink, the heat generated from the semiconductor chip is discharged directly to the motherboard through the heat sink, thereby allowing more heat to be emitted from the semiconductor chip. The present invention relates to a thin-walled package and a ball grid array semiconductor package that can be effectively released.

Description

솔더볼을 입출력 단자로 사용하는 볼 그리드 어레이(BGA) 반도체 패키지 열 방출구조Ball Grid Array (BGA) Semiconductor Package Heat Dissipation Structure Using Solder Ball as Input / Output Terminal

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 볼 그리드 어레이 반도체 패키지의 단면도,2 is a cross-sectional view of the ball grid array semiconductor package of the present invention,

제3도는 본 발명의 볼 그리드 어레이 반도체 패키지 가 마더 보드에 실장된 상태를 도시한 단면도,3 is a cross-sectional view showing a state in which the ball grid array semiconductor package of the present invention is mounted on a motherboard;

제4도는 본 발명의 볼 그리드 어레이 반도체 패키지의 열 방출구조로 사용되는 히트싱크의 단면도4 is a cross-sectional view of a heat sink used as a heat dissipation structure of the ball grid array semiconductor package of the present invention.

Claims (11)

솔더볼을 입출력 단자로 사용하는 볼 그리드 어레이(BGA) 반도체 패키지를 구성함에 있어서, 저면에 다수의 솔더볼이 부착된 PCB기판에 반도체 칩이 부착되는 부위를 공간부로 형성하고, 상기 공간부의 하부에 위치되도록 히트싱크를 PCB기판의 저면에 접착수단을 이용하여 접착하되, 상기 히트싱크의 상면에는 반도체 칩을 에폭시등의 접착수단으로 부착됨을 특징으로 하는 솔더볼을 입촐력 단자로 사용하는 볼 그리드 어레이(BGA) 반도체 패키지의 열 방출구조.In constructing a ball grid array (BGA) semiconductor package using solder balls as an input / output terminal, a portion in which a semiconductor chip is attached to a PCB substrate having a plurality of solder balls attached to a bottom thereof is formed as a space portion, and positioned below the space portion. A ball grid array (BGA) using a solder ball as an input / output terminal, wherein a heat sink is attached to a bottom surface of a PCB board by using an adhesive means, and a semiconductor chip is attached to an upper surface of the heat sink by an adhesive means such as epoxy. Heat dissipation structure of semiconductor package. 제1항에 있어서, 상기 볼 그리드 어레이(BGA) 반도체 패키지를 마더 보드에 실장시 히트싱크가 직접 솔더 죠인트(Solder Joint)되어 반도체 칩에서 방출된 열이 마더 보드로 방출되도록 함을 특징으로 하는 솔더볼을 입출력 단자로 볼 그리드 어레이(BGA) 반도체 패키지의 열 방출구조.The solder ball of claim 1, wherein when the ball grid array (BGA) semiconductor package is mounted on a motherboard, a heat sink is directly solder-joined so that heat emitted from the semiconductor chip is discharged to the motherboard. Heat dissipation structure of a ball grid array (BGA) semiconductor package. 제1항에 있어서, 상기 히트싱크의 상부면에는 PCB기판과의 접착강도를 높이기 위하여 흑색 또는 갈색 산화물(Black or Brown oxide)을 처리한 것을 특징으로 하는 솔더볼을 입출력 단자로 사용하는 볼 그리드 어레이(BGA) 반도체 패키지의 열 방출구조.The ball grid array using solder balls as input / output terminals of claim 1, wherein the upper surface of the heat sink is treated with black or brown oxide in order to increase adhesive strength with the PCB. BGA) Heat dissipation structure of semiconductor package. 제1항에 있어서, 상기 히트싱크의 상부면에는 그라운드 본드(Ground Bond)를 위한 실버 플레이틴(Silver Plating)됨을 특징으로 하는 솔더볼을 입출력 단자로 사용하는 볼 그리드 어레이(BGA) 반도체 패키지의 열 방출구조.The heat dissipation of a ball grid array (BGA) semiconductor package using solder balls as input / output terminals according to claim 1, wherein the upper surface of the heat sink is silver plated for ground bonds. rescue. 제1항 내지 2항에 있어서, 상기 히트싱크의 하부면에는 패키지를 마더보드에 실장시 히트싱크가 마도 보드와 직접 솔더링이 되도록 팔라디움(Pd)층을 형성함을 특징을 하는 솔더볼을 입출력 단자로 사용하는 볼 그리드 어레이(BGA) 반도체 패키지의 열 방출구조.The solder ball of claim 1, wherein a palladium (Pd) layer is formed on a lower surface of the heat sink so that the heat sink is directly soldered to the magic board when the package is mounted on the motherboard. Heat dissipation structure of ball grid array (BGA) semiconductor packages. 제1항 내지 제2항에 있어서, 상기 히트싱크의 하부면에는 패키지를 마더 보드에 실장시 히트싱크가 마더 보드와 솔더링이 되도록 솔더 플레이틴 처리됨을 특징으로 하는 솔더볼을 입출력 단자로 사용하는 볼 그리드 어레이(BGA) 반도체 패키지의 열 방출구조.The ball grid according to claim 1, wherein the lower surface of the heat sink is solder plated so that the heat sink is soldered with the motherboard when the package is mounted on the motherboard. Heat dissipation structure of array (BGA) semiconductor packages. 제1항에 있어서, 상기 히트싱크의 높이(두께)는 패키지가 마더 보드에 실장될때 솔더볼이 타원형으로 찌그러지면서 죠인트 되는 높이와 일치됨을 특징으로 하는 솔더볼을 입출력 단자로 사용하는 볼 그리드 어레이(BGA) 반도체 패키지의 열 방출구조.The ball grid array (BGA) according to claim 1, wherein the height (thickness) of the heat sink is matched to a height at which solder balls are joined while being elliptically distorted when the package is mounted on the motherboard. Heat dissipation structure of semiconductor package. 제1항에 있어서, 상기 히트싱크의 크기는 PCB기판에 형성된 공간부 보다 큰 것을 특징으로 하는 솔더볼을 입출력 단자로 사용하는 볼 그리드 어레이(BGA) 반도체 패키지의 열 방출구조.The heat dissipation structure of a ball grid array (BGA) semiconductor package using a solder ball as an input / output terminal according to claim 1, wherein a size of the heat sink is larger than a space formed in the PCB. 제1항에 있어서, 상기 히트싱크를 PCB기판의 저면에 접착하는 접착수단으로는 접착재 또는 접착테이프를 사용하여 그 접착 강도를 증대시켜 박리 및 열적스트레스에 대한 변형을 방지함을 특징으로 하는 솔더볼을 입출력 단자로 사용하는 볼 그리드 어레이(BGA) 반도체 패키지의 열 방출구조.The method of claim 1, wherein the adhesive means for bonding the heat sink to the bottom surface of the PCB substrate using an adhesive or adhesive tape to increase the adhesive strength of the solder ball, characterized in that to prevent the deformation of the peeling and thermal stress Heat dissipation structure of ball grid array (BGA) semiconductor packages used as input / output terminals. 제9항에 있어서, 상기 접착테이프는 양면테이프 내지 3면테이프로 됨을 특징으로 하는 솔더볼을 입출력단자로 사용하는 볼 그리드 어레이(BGA) 반도체 패키지의 열 방출구조.10. The heat dissipation structure of a ball grid array (BGA) semiconductor package according to claim 9, wherein the adhesive tape is a double-sided tape or a three-sided tape. 제1항에 있어서, 상기 히트싱크는 솔더볼이 위치한 면에 부착됨을 특징으로 하는 솔더볼을 입출력 단자로 사용하는 볼 그리드 어레이(BGA) 반도체 패키지의 열 방출구조.The heat dissipation structure of a ball grid array (BGA) semiconductor package according to claim 1, wherein the heat sink is attached to a surface on which the solder balls are located.
KR1019950025172A 1995-08-16 1995-08-16 Heat radiating structure of ball grid array semiconductor package using solder ball as input-output KR100186759B1 (en)

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JP7352583A JP2727435B2 (en) 1995-08-16 1995-12-28 Thin ball grid array semiconductor package with externally exposed heat sink attached

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KR20010057046A (en) * 1999-12-17 2001-07-04 이형도 Package substrate having cavity
KR100474193B1 (en) * 1997-08-11 2005-07-21 삼성전자주식회사 BG Package and Manufacturing Method

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KR100649878B1 (en) * 2000-12-29 2006-11-24 앰코 테크놀로지 코리아 주식회사 Semiconductor package
KR20030066996A (en) * 2002-02-06 2003-08-14 주식회사 칩팩코리아 Ball grid array package with improved thermal emission property
CN100364076C (en) * 2003-09-08 2008-01-23 日月光半导体制造股份有限公司 Bridging chip package structure
CN103531549A (en) * 2013-10-24 2014-01-22 桂林微网半导体有限责任公司 Semiconductor chip packaging structure and packaging method

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JP2660295B2 (en) * 1988-08-24 1997-10-08 イビデン株式会社 Substrate for mounting electronic components
JP2958380B2 (en) * 1990-03-12 1999-10-06 株式会社日立製作所 Semiconductor device

Cited By (2)

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Publication number Priority date Publication date Assignee Title
KR100474193B1 (en) * 1997-08-11 2005-07-21 삼성전자주식회사 BG Package and Manufacturing Method
KR20010057046A (en) * 1999-12-17 2001-07-04 이형도 Package substrate having cavity

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JPH09186272A (en) 1997-07-15
JP2727435B2 (en) 1998-03-11
KR100186759B1 (en) 1999-04-15

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