TW421835B - Semiconductor package with enhanced heat dissipation and electric properties - Google Patents

Semiconductor package with enhanced heat dissipation and electric properties Download PDF

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Publication number
TW421835B
TW421835B TW88105918A TW88105918A TW421835B TW 421835 B TW421835 B TW 421835B TW 88105918 A TW88105918 A TW 88105918A TW 88105918 A TW88105918 A TW 88105918A TW 421835 B TW421835 B TW 421835B
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TW
Taiwan
Prior art keywords
heat dissipation
scope
semiconductor package
patent application
item
Prior art date
Application number
TW88105918A
Other languages
Chinese (zh)
Inventor
Cheng-Lang Liou
Original Assignee
Caesar Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Caesar Technology Inc filed Critical Caesar Technology Inc
Priority to TW88105918A priority Critical patent/TW421835B/en
Application granted granted Critical
Publication of TW421835B publication Critical patent/TW421835B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
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    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

A semiconductor package with enhanced heat dissipation and electric properties is constructed on a BGA substrate or laminate substrate. The BGA substrate or laminate substrate at least has a plurality of circuit junctions and a plurality of heat dissipation junctions thereon. A chip is placed on the substrate. The pad thereon forms an electric connection with the circuit junctions. The chip and the heat dissipation junctions are also connected together. The electric connection can be carried out by wire bonding or flip chip. A liquid packaging material is used to cover the chip, the circuit junctions, the heat dissipation junctions and the connection parts between the pad and the circuit junctions. The heat dissipation conductive cover has an recess cavity covering on the liquid packaging material and is combined with the substrate so that the liquid packaging material is located in the recess cavity, and the liquid packaging material and the heat dissipation conductive cover are combined together.

Description

經濟部智慧財產局員工消費合作社印製 421835 4492twf./005 A7 B7 五、發明Λ明（I ) 本發明是有關於一種加強散熱及電性之半導體封裝， 且特別是有關於一種結合液態封裝材料及散熱導電蓋以加 強散熱及電性之半導體封裝。 半導體產品發展至今，實已深入每個人的生活中，無 論食衣住行育樂均有半導體產品之運用。然而半導體產品 在經過半導體廠複雜之製程，而獲得晶圓或晶片之半成 品’常常還需經過封裝(Package)的步驟，透過一適當承載 器（Carder)及包裝，才能應用於最後之電子產品上。一般 實裝技術可大略分爲幾階段： 1. 承載器(Carrier)之選擇：依照產品之需求選擇適當之 晶片承載器，比如導線架(Lead Frame)、軟片式承載器(film carrier)或積層板(Laminate Substrate)等。其中軟片式承載 器大多用於軟片自動接合（Tape Automatic Bonding, TAB) 技術。 2. 晶片與承載器之電性接合：目前之技術包括打導線 (wire bonding)、軟片自動接合（TAB)及覆晶技術（flip chip or controlled collapse chip connection, C4)。 3. 包裝及成型··將晶片及晶片與承載器接合部份以樹 脂、陶瓷或其他包裝材質覆蓋，以保護元件及接合部份。 由於半導體技術日新月異，積集度不斷提高，如今線 寬0.18 micron的生產技術已能量產，許多技術無不朝向 「輕、薄、短、小」的趨勢進展。相對地，半導體封裝技 術也開始面對高腳數（high pin count)，小間距(fine pitch) 的挑戰。球格狀陣列式封裝(Ball Grid Array, BGA)，是現 3 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐） 裝------訂------線^. - ' (#先閏讀背面之注意事項r^.寫本頁-) 經濟部智慧財產局員工消費合作社印製 42183 5 4492twf./005 A7 --B7____ 五、發明説明（> ) 今常用於高腳數、小間距元件之封裝方式。請參照第1圖’ 其所繪示爲習知球格狀陣列式封裝之剖面示意圖。球格狀 陣列式封裝主要係建構在一基板l〇(substrate)上，而基板 10乃由多層絕緣層U與圖案化之銅薄膜13疊合而形成； 基板10之線路則是由圖案化銅薄膜13及貫孔14(via)所連 接形成。作爲訊號傳遞的線路在基板10表面露出的部分 形成線路接點16a;而作爲接地或導熱用的線路在基板10 表面則形成散熱接點16b。封裝時晶片18係以一銀膠 20(silver paste)與散熱接點16b(此部份一般又稱晶片座)連 接’接著進行打導線步驟，以導線22將晶片18上之焊墊 (bonding pad)與線路接點i6a電性連接。再則進行封膠製 手壬（molding)’以封裝材料^(molding compound)覆蓋晶片 I8、導線22及線路接點16a。之後，在基板1〇的背面對 應之接點16c放置錫球26(solder ball)，則完成球格狀陣 列式封裝。 習知的封裝方式’由於未來腳位數逐漸增高，線路接 點及導線間距相對降低，若以傳統封膠方式，模流會造成 導線因變形而短路，降低產品良率。再則習知封裝材料熱 導性較差，對於將來高積集度晶片之散熱，恐怕不敷需求， 相對地會降低產品之效能(performance)。而且對於將來高 頻之兀件，由於其對於外界之干擾(noise)十分敏感，因此 如何有效隔離外界干擾亦成爲一重要課題。 因此本發明的觀點之一在於提供一種半導體封裝結 構’利用點膠或網版印刷的方式進行封裝，以提高產品之 4 本紙張尺度國家標準（CNS ) A4規格（210X297公釐1 ' ----------^------ir------線 (請先閲讀背面之注意事項/也寫本頁) 421835 4492twf./005 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明铳明（令） 良率以及生產效率並降低成本。 本發明的觀點之二在於提供一種半導體封裝結構，利 用液態封裝材料以及散熱導電蓋，改善封裝之散熱效率。 本發明的觀點之三在於提供一種半導體封裝結構，利 用散熱導電蓋，改善封裝之電性’有效隔離外界之干擾。 爲達成本發明之上述和其他觀點與目的，本發明提出 一種加強散熱及電性之半導體封裝，其建構在一 BGA基 板或積層板上，BGA基板或積層板上至少具有多個線路接 點以及多個散熱接點。晶片固定於基板上，其上之焊墊與 線路接點電性連接’而晶片亦與散熱接點連接，然而可以 採用打導線或覆晶方式進行電性連接。液態封裝材料則覆 蓋晶片、線路接點、散熱接點及焊墊與線路接點連接的部 分。散熱導電蓋具有一凹穴，覆蓋於液態封裝材料上，並 與基板接合，使得液態封裝材料位於凹穴中，且液態封裝 材料與散熱導電蓋接合。 依照本發明的一較佳實施例，散熱導電蓋較佳是與基 板中接地線路電性連接，不但可以提供良好之散熱路徑， 並能對於外界干擾形成良好之遮蔽。此外由於採用液態封 裝材料可以提高生產良率，並由於其與散熱導電蓋連接， 能降低熱阻，提高散熱效率。如需更加強散熱效能，可以 在散熱導電蓋頂面及側面增加鰭片或凹槽，以增加散熱面 積。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 5 (請先閲讀背面之注意事項?·\寫本頁0 -裝. -線 本纸張尺度適用中國國家標準（CNS ) A4規格（21 〇 X 297公釐） 42^835 4492twf./005 A 7 B7 經濟部智慧財產局員工消費合作社印製 五、發明铳明（f) 細說明如下： 圖式之簡單說明： 第1圖所繪示爲習知球格狀陣列式封裝之剖面示意 圖。 第2A圖繪示依照本發明一較佳實施例的一種加強散 熱及電性之半導體封裝剖面示意圖。 第2B圖所繪示爲依照本發明另一較佳實施例的一種 加強散熱及電性之半導體封裝剖面示意圖。 第3A、3B圖所繪示爲對應第2A、2B圖之具有鰭片 的散熱導電蓋剖面結構圖。 第4A、4B圖所繪示爲對應第2A、2B圖之具有凹槽 的散熱導電蓋剖面結構圖。 圖式之標示說明： 10 :基板 13、33 :銅薄膜 16a ' 36a :線路接點 18、38 :晶片 22、42 :導線 16c、36c :接點 30 : BGA基板 40 :導電及導熱樹脂 44 :液態封裝材料 66 :凹穴 6 12、32 :絕緣層 14、34a、34b :貫孔 16b ' 36b :散熱接點 20 :銀膠 24 :封裝材料 26、50 :錫球 60、62 :晶片表面 64 :焊墊 48 :散熱導電蓋 68、70 :散熱導電蓋表面 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X297公釐） (請先閲讀背面之注意事項^,..寫本頁) 經濟部智慧財產局員工消費合作社印製 421835 4492twf./〇〇5 A 7 B7 五、發明説明（f) 72 :散熱導電蓋側面 74 :線路接點 46 :導熱封裝材料 52 :凸塊 76 :鰭片 78 :凹槽 窗施例· 請參照第2A圖，其繪示依照本發明一較佳實施例的 一種加強散熱及電性之半導體封裝剖面示意圖。本發明之 半導體封裝結構，係建構在積層板(laminate substrate)上， 不但可以建構在一般BGA基板上，亦可以建構在印刷電 路板(print circuit board, PCB)，以形成「電路板晶片封裝」 (Chip on Board)結構。以球格狀陣列式封裝結構爲例，本 發明之封裝建構在一BGA基板30上，基板30乃由多層 絕緣層32與圖案化之銅薄膜33疊合而形成；BGA基板3〇 之線路則是由圖案化銅薄膜33及貫孔34a、34b(via)所壤 接形成。作爲訊號傳遞(包括I/O, Vcc，Vss等）的線路在 基板3〇表面露出的部分形成線路接點36a ;而作爲接 導熱用的線路在BGA基板30表面則形成散熱接點36b。 晶片38在其一表面6〇上具有多個焊墊64,封裝時晶片3§ 之另一表面62係以一導熱及導電樹脂40，比如銀膨，_ 散熱接點36b(此部份一般又稱晶片座）連接。本實施例中 係以打導線方式爲例，以導線42，比如金線、鋁線或銅線， 將晶片38上之焊墊64與線路接點36a電性連接。 液態封裝材料44(Liquid Compound)，則覆蓋晶片、 線路接點36a及導線42，以保護晶片38與BGA基扳3〇 I--------裝-----—訂------線 - (請先閲讀背面之注意事項/乂寫本頁} 經濟部智慧財產局員工消費合作社印製 421835 4492twf./00 5 _____B7 五、發明説明（乙） 電性連接的部分。液態封裝材料44的封膠方法包括以點 膠（glob-top or dispense)的方式，或者是網版印刷（screen printing)的方式來進行。無論點膠或者是網版印刷的方式， 均可以提高生產良率及量產速率。並由於不必投資於模具 之製造，故可以降低生產成本。 散熱導電蓋48在其~表面70具有一凹穴66，用以容 納晶片38 ’以及液態封裝材料44，散熱導電蓋48之材質 包括鋁、銅、一般導熱陶瓷材料或導電陶瓷複合材料等。 散熱導電蓋48並以表面70與BGA基板30相接，比如是 以導電及導熱性樹脂(conductive epoxy)黏合。爲了進一步 加強散熱導電蓋48的散熱效率，以及障蔽外界干擾的效 果’較佳的是將散熱導電蓋48與BGA基板30上之線路 接點74(比如爲接地接點)連接。此時晶片38所產生之熱 能不但可以透過散熱導電蓋48，傳導至積層板(未繪示）， 同時讓散熱導電蓋48接地，可以提高1〇〜15%的干擾遮蔽 效果。然而，根據封裝之需求，散熱導電蓋48可以選擇 性的僅具導熱功能、僅具導電功能或者兼具導熱及導電功 能’以因應各種元件之應用。 至於液―封裝材料44與散熱導電蓋48之間的連接， 可以透過二導熱封裝材料46(Thermal c〇mp〇und)使其相 連。導熱!封裝材料46亦爲一種液態封裝材料，然其導熱 係數較一般液態封裝材料爲高，有助於散熱效率之提昇。 液態封裝材料44可以充滿於散熱導電蓋48之凹穴Μ中， 亦苛以僅覆蓋晶片38、.導線42 I線路接點36a的部分，Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 421835 4492twf./005 A7 B7 V. Invention 发 明明 (I) The present invention relates to a semiconductor package with enhanced heat dissipation and electrical properties, and more particularly to a combination of liquid packaging materials And thermally conductive conductive cover to enhance heat dissipation and electrical semiconductor packaging. So far, the development of semiconductor products has really penetrated into everyone's life. Regardless of food, clothing, living, and travel, Yule has used semiconductor products. However, semiconductor products undergo a complex process in a semiconductor factory, and obtaining wafers or semi-finished products of wafers often needs to go through a package step before they can be applied to the final electronic product through a suitable carder and packaging. . The general mounting technology can be roughly divided into several stages: 1. Carrier selection: Select the appropriate wafer carrier according to the needs of the product, such as lead frame, film carrier, or lamination Laminate Substrate, etc. Among them, the film carrier is mostly used for Tape Automatic Bonding (TAB) technology. 2. Electrical bonding of chip and carrier: current technologies include wire bonding, TAB, and flip chip or controlled collapse chip connection (C4). 3. Packaging and molding ... Cover the wafers and the joints between the wafers and the carrier with resin, ceramic or other packaging materials to protect the components and joints. Due to the rapid development of semiconductor technology and the increasing degree of accumulation, today's 0.18 micron line production technology has been produced, and many technologies have all progressed towards the trend of "light, thin, short, and small." In contrast, semiconductor packaging technology is also beginning to face the challenge of high pin count and fine pitch. Ball Grid Array (BGA) is a 3 paper standard that is applicable to China National Standard (CNS) A4 (210 X 297 mm). Line ^.-'(# 先 闰 Read the notes on the back r ^ .Write this page-) Printed by the Intellectual Property Bureau Staff Consumer Cooperatives of the Ministry of Economic Affairs 42183 5 4492twf./005 A7 --B7 ____ V. Description of the Invention (>) Today it is often used for high pin count, small pitch component packaging. Please refer to FIG. 1 'for a schematic cross-sectional view of a conventional ball grid array package. The ball grid array package is mainly constructed on a substrate 10 (substrate), and the substrate 10 is formed by stacking a plurality of insulating layers U and a patterned copper film 13; the lines of the substrate 10 are patterned copper The thin film 13 and the via 14 are connected to each other. A portion of the circuit that is transmitted as a signal is exposed on the surface of the substrate 10 to form a circuit contact 16a, and a circuit for grounding or heat conduction is formed on the surface of the substrate 10 to form a thermal contact 16b. When packaging, the chip 18 is connected with a silver paste 20 (silver paste) and the heat dissipation contact 16b (this part is also commonly referred to as a chip holder). Then the wire bonding step is performed, and the bonding pad on the chip 18 is bonded with the wire 22 ) Is electrically connected to the line contact i6a. Then, a molding compound is used to cover the chip I8, the wires 22, and the circuit contacts 16a with a molding compound. Thereafter, a solder ball 26 (solder ball) is placed on the rear surface of the substrate 10 corresponding to the contact 16c, and a ball grid array package is completed. The conventional packaging method ', because the number of pins will gradually increase in the future, the circuit contacts and the distance between the wires will be relatively reduced. If the traditional sealing method is used, the mold flow will cause the wires to be short-circuited due to deformation and reduce the product yield. Furthermore, it is known that the thermal conductivity of packaging materials is poor. For the heat dissipation of high-integration chips in the future, I am afraid that they will not meet the demand, and will relatively reduce the performance of the product. And for future high-frequency components, because it is very sensitive to external noise, how to effectively isolate external interference has become an important issue. Therefore, one of the viewpoints of the present invention is to provide a semiconductor packaging structure that uses packaging or screen printing for packaging to improve the product's 4 national paper standard (CNS) A4 specifications (210X297 mm 1 '--- ------- ^ ------ ir ------ line (please read the precautions on the back / also write this page) 421835 4492twf./005 A7 B7 Staff Consumption of Intellectual Property Bureau, Ministry of Economic Affairs Cooperative printed 5. Invented the Ming Yi (Order) yield and production efficiency and reduce costs. The second aspect of the present invention is to provide a semiconductor packaging structure, using liquid packaging materials and heat dissipation conductive cover, to improve the heat dissipation efficiency of the package. The third point is to provide a semiconductor package structure that uses a heat-dissipating conductive cover to improve the electrical properties of the package and effectively isolate external interference. In order to achieve the above and other viewpoints and objectives of the invention, the present invention proposes a method for enhancing heat dissipation and electrical properties. A semiconductor package is constructed on a BGA substrate or a multilayer board. The BGA substrate or the multilayer board has at least a plurality of circuit contacts and a plurality of heat dissipation contacts. The chip is fixed on the substrate. The solder pads are electrically connected to the circuit contacts, and the chip is also connected to the heat sink contacts. However, the wires or chip-on-chip methods can be used for electrical connection. The liquid packaging material covers the chip, circuit contacts, heat sink contacts, and The part where the solder pad is connected to the circuit contact. The heat-dissipating conductive cover has a cavity covering the liquid packaging material and is bonded to the substrate so that the liquid packaging material is located in the cavity and the liquid packaging material is connected to the heat-dissipating conductive cover. In a preferred embodiment of the present invention, the heat-dissipating conductive cover is preferably electrically connected to the ground line in the substrate, which can not only provide a good heat dissipation path, but also form a good shield against external interference. In addition, the use of a liquid packaging material can improve Production yield, and because it is connected to the heat conductive cover, it can reduce thermal resistance and improve heat dissipation efficiency. If you need to enhance heat dissipation efficiency, you can add fins or grooves on the top and side of the heat conductive cover to increase the heat dissipation area. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred implementation is given below. , And in accordance with the attached drawings, make details 5 (Please read the precautions on the back first? \\ Write this page 0 -pack. -The size of the paper is applicable to the Chinese National Standard (CNS) A4 specification (21 〇X 297 公) (%) 42 ^ 835 4492twf./005 A 7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. The invention is detailed (f) The detailed description is as follows: A brief description of the diagram: Figure 1 shows a conventional ball grid Sectional schematic diagram of an array package. Figure 2A illustrates a schematic cross-sectional diagram of a semiconductor package with enhanced heat dissipation and electrical properties according to a preferred embodiment of the present invention. Figure 2B illustrates a schematic diagram of a semiconductor package according to another preferred embodiment of the present invention. A schematic cross-sectional view of a semiconductor package with enhanced heat dissipation and electrical properties. Figures 3A and 3B are cross-sectional structural diagrams of the heat-dissipating conductive cover with fins corresponding to Figures 2A and 2B. Figures 4A and 4B are cross-sectional structural diagrams of the heat-dissipating conductive cover with grooves corresponding to Figures 2A and 2B. Description of the drawings: 10: Substrate 13, 33: Copper film 16a '36a: Circuit contact 18, 38: Wafer 22, 42: Wire 16c, 36c: Contact 30: BGA substrate 40: Conductive and thermally conductive resin 44: Liquid packaging material 66: Cavities 6 12, 32: Insulating layers 14, 34a, 34b: Through holes 16b '36b: Thermal contact 20: Silver glue 24: Packaging materials 26, 50: Tin balls 60, 62: Wafer surface 64 : Welding pad 48: Thermal conductive cover 68, 70: Surface of thermal conductive cover The paper size is applicable to Chinese National Standard (CNS) Λ4 specification (210X297 mm) (Please read the precautions on the back ^, .. write this page) Economy Printed by the Consumer Cooperative of the Ministry of Intellectual Property Bureau 421835 4492twf./〇〇5 A 7 B7 V. Description of the Invention (f) 72: Side of the heat-dissipating conductive cover 74: Line contact 46: Thermally conductive packaging material 52: Bump 76: Fin 78: Example of a recessed window. Please refer to FIG. 2A, which is a schematic cross-sectional view of a semiconductor package with enhanced heat dissipation and electrical properties according to a preferred embodiment of the present invention. The semiconductor package structure of the present invention is constructed on a laminate substrate, which can be constructed not only on a general BGA substrate, but also on a printed circuit board (PCB) to form a "circuit board chip package." (Chip on Board) structure. Taking the ball grid array package structure as an example, the package of the present invention is constructed on a BGA substrate 30. The substrate 30 is formed by stacking a plurality of insulating layers 32 and a patterned copper film 33; the circuit of the BGA substrate 30 is It is formed by the patterned copper thin film 33 and the through holes 34a, 34b (via). The circuit for signal transmission (including I / O, Vcc, Vss, etc.) forms a circuit contact 36a on the exposed portion of the surface of the substrate 30; and the circuit for heat conduction forms a heat dissipation contact 36b on the surface of the BGA substrate 30. The chip 38 has a plurality of bonding pads 64 on one surface 60, and the other surface 62 of the chip 3§ is packaged with a thermally and electrically conductive resin 40, such as silver, and a thermal contact 36b (this part is generally (Called wafer holder) connection. In this embodiment, the method of conducting wires is used as an example. The wires 42 such as gold wires, aluminum wires, or copper wires are used to electrically connect the pads 64 on the chip 38 to the line contacts 36a. The liquid packaging material 44 (Liquid Compound) covers the chip, the circuit contact 36a, and the wire 42 to protect the chip 38 and the BGA base board. ---- Line-(Please read the notes on the back / write this page first) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 421835 4492twf./00 5 _____B7 V. Description of the Invention (B) Electrical connection. The sealing method of the liquid packaging material 44 includes a glob-top or dispense method or a screen printing method. Regardless of the dispense method or the screen printing method, it can be improved. Production yield and mass production rate. And because there is no need to invest in the manufacture of molds, production costs can be reduced. The heat-dissipating conductive cover 48 has a cavity 66 on its surface 70 to accommodate the wafer 38 'and the liquid packaging material 44, The material of the heat-dissipating conductive cover 48 includes aluminum, copper, general heat-conductive ceramic material or conductive ceramic composite material, etc. The heat-dissipating conductive cover 48 is connected to the BGA substrate 30 by the surface 70, for example, it is bonded with a conductive and thermally conductive resin (conductive epoxy). In order to add further The heat dissipation efficiency of the heat dissipation conductive cover 48 and the effect of shielding external interference 'It is better to connect the heat dissipation conductive cover 48 to the line contact 74 (such as a ground contact) on the BGA substrate 30. At this time, the chip 38 generates Thermal energy can not only be conducted to the laminated board (not shown) through the heat-dissipating conductive cover 48, but also ground the heat-dissipating conductive cover 48, which can improve the interference shielding effect of 10-15%. However, according to the requirements of the package, the heat-dissipating conductive cover 48 It can selectively have only thermal conductivity function, only conductive function, or both thermal conductivity and conductivity function to meet the application of various components. As for the connection between the liquid-encapsulating material 44 and the heat-dissipating conductive cover 48, the second thermally conductive packaging material can be passed through. 46 (Thermal commpund) to connect them. Thermally conductive! The packaging material 46 is also a liquid packaging material, but its thermal conductivity is higher than the general liquid packaging material, which helps to improve heat dissipation efficiency. The liquid packaging material 44 can It is filled in the cavity M of the heat-dissipating conductive cover 48, and also covers only the part of the chip 38, the wire 42 and the line contact 36a.

S 本紙張尺度適用中國國家> A4規格（公釐]- -- n-^n I I 裝 I I I ! J ^ 訂 I It I 線 (請先聞讀背面之注意事項爭4寫本頁) 經濟部智慧財產局員工消費合作社印製 421835 4492twf./005 pj _______B7 五、發明説明（7 ) 而留一空隙於凹穴66中。此時，晶片38之散熱有兩條路 徑：（1)對於晶片38具有元件之表面60所散發之大量熱源 係透過液態封裝材料44、導熱封裝材料46，從散熱導電 蓋48向外界發散，或藉由線路接點74及錫球50導入積 .層板。（2)晶片38之背面62亦可以傳導部分元件所產生之 熱量’透過散熱接點36b及錫球50傳導至積層板。 同樣的’在基板30的背面對應之接點36c放置錫球 50，以作爲對積層板電性連接之用。散熱導電蓋48除了 可以提高封裝之散熱及干擾隔離能力，由於BGA基板30 係固定於其上，因此可以加強BGA基板30之剛性，使 得封裝中錫球50平面度的誤差縮小，以符合規格要求， 提高產品良率。尤其對於未來BGA基板厚度逐漸降低， 相對的剛性上亦會隨之下降，因此散熱導電蓋之設計，將 對未來量產之良率，有顯著之助益。 請參照第2B圖，其所繪示爲依照本發明另一較佳實 施例的一種加強散熱及電性之半導體封裝剖面示意圖。此 實施例主要是針對覆晶技術應用於BGA封裝(即承載器上 之覆晶封裝技術，flip chip on carrier)，以及應用於印刷電 路板的部分(flip chip on board)作說明。以BGA封裝爲例， 同樣地建構在BGA基板10上’晶片38在其一表面60上 具有多個焊墊64，其在每一焊墊64上均配置一凸塊 52(bump)，其材質包括金、錫鉛合金 '導電性環氧樹脂 (conductive epoxy)等。封裝時晶片38之每~焊塾64均以 凸塊52,與BGA基板30之線路接點36a、：36b電性連接， 9 本紙張尺度適用中國國家榡準（CNS ) A4規格（210x297公逢） ----------餐------、訂------I ' - (請先閲讀背面之注意事項/ 寫本頁) 經濟部智慧財產局員工消費合作社印製 421835 4492twf./005 A7 B7五、發明铳明（2) 形成覆晶結構。當然熟習該技術者應知，此部份亦可以運 用異方性導電膠（Anisotropic Conductive Paste，ACP)或異 方性導電膜（Anisotropic Conductive Film，ACF)，配合凸塊 52作爲焊墊64與線路接點36a、36b之電性連接。然而， 還需要在晶片38與BGA基板30之間塡入塡充材料 54(underfill)，分散晶片38與BGA基板30之間的熱應力 (thermal stress)，以避免因熱膨脹循環（Thermal Expanding Cycle)所造成凸塊52之熱疲勞破壞（Thermal Fatigue Failure)。 至於晶片38的另一表面62，則以一導熱封裝材料46 與散熱導電蓋48連接。導熱封裝材料46，可以充滿整個 凹穴66，或者僅連接晶片38之表面62與散熱導電蓋48。 其他有關散熱導電蓋48之結構部分’與前述之實施例類 似，在此不再贅述。此時，晶片38之散熱有兩條路徑：（1) 對於晶片38具有元件之表面60所散發之大量熱源係透過 散熱接點36b及錫球50傳導至積層板。（2)晶片38之背 面62亦可以傳導部分元件所產生之熱量’透過導熱封裝 材料46，從散熱導電蓋48向外界發散’或藉由線路接點 74及錫球50導入積層板。 除了上述之結構外，爲了提昇散熱導電蓋之散熱效果’ 可以增加散熱導電蓋之表面積，以提高散熱效率。請同時 參照第3A、3B圖，其所繪示爲對應第2A、2B圖之另一 種散熱導電蓋剖面結構圖。吾人可以在散熱導電蓋48之 頂面68及側面72形成多個鰭片76，以增加散熱面積，提 m f n I i I I I 訂 11 I I I 線 (請先w讀背面之注意事項寫本頁) 本紙浪尺度適用中國國家標準（CNS ) A4規格（2iOX297公釐） 42彳835 4492twf./005 A7 B7 經濟部智慧財產局S工消費合作社印製 五、發明説明（？） 高散熱效率。請再參照第4A、4B圖，其所繪示爲對應第 2A、2B圖之另一種散熱導電蓋剖面結構圖。吾人亦可以 在散熱導電蓋48之頂面68及側面72形成多個凹槽78， 其圖案可以爲環形，條狀，或是陣列式方形/圓形凹槽 (dimple)等，以增加散熱面積，提高散熱效率。當然，無 論鰭片或是凹槽的表面結構，均可在頂面68或側面72搭 配運用。 雖然上述實施例中僅以BGA基板之結構爲例以作說 明，至於印刷電路板部分，熟習該技術者應知可以仿此實 施例達成，在此不再贅述。 綜上所述，本發明至少具有下列優點： 1_本發明之半導體封裝結構，採用液態封裝材料，並 利用點膠或網版印刷的方式進行封裝，以提高產品之良率 以及生產效率並降低成本。 2. 本發明之半導體封裝結構，利用液態封裝材料以及 散熱導電蓋，提供晶片較佳之散熱路徑，改善封裝之散熱 效率。 3. 本發明之半導體封裝結構’由於散熱導電蓋之設計’ 再加上將散熱導電蓋接地，使其呈主動接地狀態（active ground)，可以改善封裝之電性，有效隔離外界之干擾。 4·本發明中散熱導電蓋的設計可以加強BGA基板之 剛性，使得封裝中錫球平面度的誤差縮小’以符合規格要 求，有效提高產品量產良率。 雖然本發明已以一較佳實施例揭露如上，然其並非用 (請先閲讀背面之注意Ϋ項η, '寫本頁) 裝. 訂 本紙張尺度適用中國國家標準（CNS ) A4規格（2丨0 X 297公釐） A7 B7 ^ ；835 4^92twf./〇〇5 五、發明k明（/。） 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內’當可作些許之更動與潤飾，因此本發明之保 護範圔當視後附之申請專利範圍所界定者爲準。 (請先閱讀背面之注意事項-">，寫本頁〕S The size of this paper is applicable to Chinese country > A4 size (mm) --- n- ^ n II Pack III! J ^ Order I It I line (please read the precautions on the back first and write 4 on this page) Ministry of Economic Affairs Printed by the Intellectual Property Bureau employee consumer cooperative 421835 4492twf./005 pj _______B7 V. Description of the invention (7) and leave a gap in the cavity 66. At this time, the heat dissipation of the chip 38 has two paths: (1) For the chip 38 A large amount of heat emitted from the surface 60 having the components is emitted from the heat-dissipating conductive cover 48 to the outside through the liquid encapsulation material 44 and the heat-conducting encapsulation material 46, or is introduced into the laminate through the circuit contact 74 and the solder ball 50. (2 ) The back surface 62 of the chip 38 can also conduct the heat generated by some components' to the multilayer board through the heat dissipation contact 36b and the solder ball 50. Similarly, the solder ball 50 is placed on the corresponding contact 36c on the back surface of the substrate 30 as the For the electrical connection of laminated boards. In addition to the heat-dissipating conductive cover 48, which can improve the heat dissipation and interference isolation capabilities of the package, since the BGA substrate 30 is fixed to it, the rigidity of the BGA substrate 30 can be strengthened, so that the ball 50 in the package is flat. The degree of error is reduced to Meet the specifications and improve the yield of the product. Especially in the future, the thickness of the BGA substrate will gradually decrease, and the relative rigidity will also decrease accordingly. Therefore, the design of the heat-dissipating conductive cover will significantly help the yield of future mass production. Please refer to FIG. 2B, which is a schematic cross-sectional view of a semiconductor package with enhanced heat dissipation and electrical properties according to another preferred embodiment of the present invention. This embodiment is mainly for flip-chip technology applied to BGA packages (ie, carriers). The above-mentioned flip-chip packaging technology, flip chip on carrier, and the part applied to printed circuit boards (flip chip on board) will be described. Taking the BGA package as an example, it is also constructed on the BGA substrate 10, and the chip 38 is one of them. There are a plurality of solder pads 64 on the surface 60, and a bump 52 (bump) is arranged on each solder pad 64, and the material includes gold, tin-lead alloy 'conductive epoxy, and the like. Each of the chip 38 to the solder pad 64 is electrically connected to the line contacts 36a, 36b of the BGA substrate 30 by a bump 52. 9 This paper size applies to China National Standard (CNS) A4 (210x297).- ---------meal------, ------ I '-(Please read the precautions on the back / write this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 421835 4492twf./005 A7 B7 V. Invention of Ming (2) Formation of flip chip Structure. Of course, those familiar with this technology should know that this part can also use Anisotropic Conductive Paste (ACP) or Anisotropic Conductive Film (ACF), with the bump 52 as the solder pad 64. Electrical connection with line contacts 36a, 36b. However, an underfill material needs to be inserted between the wafer 38 and the BGA substrate 30 to disperse the thermal stress between the wafer 38 and the BGA substrate 30 to avoid thermal expansion cycles. Thermal Fatigue Failure of the bumps 52 caused. As for the other surface 62 of the chip 38, a heat-conducting packaging material 46 is connected to the heat-dissipating conductive cover 48. The heat-conducting packaging material 46 may fill the entire cavity 66 or connect only the surface 62 of the chip 38 and the heat-dissipating conductive cover 48. The other structural parts of the heat-dissipating conductive cover 48 are similar to the foregoing embodiments, and will not be repeated here. At this time, the heat dissipation of the wafer 38 has two paths: (1) A large amount of heat emitted from the surface 60 of the chip 38 having components is conducted to the laminated board through the heat dissipation contact 36b and the solder ball 50. (2) The back surface 62 of the chip 38 can also conduct the heat generated by some components 'through the heat-conducting packaging material 46 and dissipate from the heat-dissipating conductive cover 48 to the outside' or through the circuit contacts 74 and the solder balls 50 to the laminated board. In addition to the structure described above, in order to improve the heat dissipation effect of the heat dissipation conductive cover, the surface area of the heat dissipation conductive cover can be increased to improve the heat dissipation efficiency. Please also refer to Figures 3A and 3B, which are shown as cross-sectional structural diagrams of another heat-dissipating conductive cover corresponding to Figures 2A and 2B. I can form multiple fins 76 on the top surface 68 and the side surface 72 of the thermal conductive cover 48 to increase the heat dissipation area and to increase the mfn I i III order 11 III line (please read the precautions on the back to write this page) Standards are applicable to Chinese National Standard (CNS) A4 specifications (2iOX297 mm) 42 彳 835 4492twf./005 A7 B7 Printed by S Industrial Consumer Cooperatives, Bureau of Intellectual Property, Ministry of Economic Affairs 5. Description of invention (?) High heat dissipation efficiency. Please refer to Figs. 4A and 4B again, which are shown as cross-sectional structural diagrams of another heat dissipation conductive cover corresponding to Figs. 2A and 2B. I can also form a plurality of grooves 78 on the top surface 68 and the side surface 72 of the heat-dissipating conductive cover 48. The pattern can be circular, stripe, or array square / circular dimples to increase the heat dissipation area. To improve heat dissipation efficiency. Of course, regardless of the surface structure of the fins or grooves, it can be used on the top surface 68 or the side surface 72. Although the above embodiments only take the structure of the BGA substrate as an example for explanation, as for the printed circuit board part, those skilled in the art should know that this embodiment can be achieved by following this embodiment, and will not be repeated here. To sum up, the present invention has at least the following advantages: 1_ The semiconductor packaging structure of the present invention adopts liquid packaging materials and uses the method of dispensing or screen printing for packaging, so as to improve product yield and production efficiency and reduce cost. 2. The semiconductor package structure of the present invention uses a liquid packaging material and a heat-dissipating conductive cover to provide a better heat dissipation path for the chip and improve the heat dissipation efficiency of the package. 3. The semiconductor package structure of the present invention ‘due to the design of the heat-dissipating conductive cover’ and the grounding of the heat-dissipating conductive cover to make it active ground can improve the electrical properties of the package and effectively isolate external interference. 4. The design of the heat-dissipating conductive cover in the present invention can strengthen the rigidity of the BGA substrate, reduce the error of the flatness of the solder balls in the package 'to meet the specifications, and effectively improve the yield of mass production. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to be used (please read the note on the back, η, 'write this page). The size of the paper is applicable to the Chinese National Standard (CNS) A4 specification (2丨 0 X 297 mm) A7 B7 ^; 835 4 ^ 92twf. / 〇〇05 5. Invention k Ming (/.) To limit the present invention, anyone skilled in the art will not depart from the spirit and scope of the present invention. 'When some modifications and retouching can be made, the protection scope of the present invention shall be determined by the scope of the attached patent application. (Please read the notes on the back- " > first, write this page)

T 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準{ CNS ) Λ4規格（210X297公釐）T Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper size applies the Chinese National Standard {CNS) Λ4 specification (210X297 mm)

Claims (1)

421835 4492twf./005 A8 B8 C8 D8 六、申請專利範圍 1. 一種加強散熱及電性之半導體封裝，包括： 一基板，該基板至少具有複數個線路接點以及複數個 散熱接點； 一晶片，該晶片具有一第一表面及一第二表面，該晶 片以該第二表面面向該基板的方式配置於該基板上，其中 該第一表面至少具有複數個焊墊，且每一該些焊墊分別與 該些線路接點以一導線電性連接，該第二表面則與該些散 熱接點連接； 一液態封裝材料，覆蓋該晶片、該些導線、該些線路 接點及該些散熱接點；以及 一散熱導電蓋，該散熱導電蓋具有一凹穴，該散熱導 電蓋覆蓋於該液態封裝材料上，並與該基板接合，使得該 液態封裝材料位於該凹穴中，且該液態封裝材料與該散熱 導電蓋接合。 2. 如申請專利範圍第1項所述加強散熱及電性之半導 體封裝，其中該基板包括積層板。 3. 如申請專利範圍第1項所述加強散熱及電性之半導 體封裝，其中該基板包括球格狀陣列式封裝基板。 經濟部中央標隼局員工消費合作社印製 ·(請先閲讀背面之注意事項再真寫本頁) 4. 如申請專利範圍第1項所述加強散熱及電性之半導 體封裝，其中該液態封裝材料充滿該凹穴。 5. 如申請專利範圍第1項所述加強散熱及電性之半導 體封裝，其中該液態封裝材料與該凹穴間具有一空隙，且 該液態封裝材料與該散熱導電蓋以一導熱封裝材料接合。 6. 如申請專利範圍第1項所述加強散熱及電性之半導 本紙張尺度適用中國國家標準（CNS ) A4洗格（2I0X297公釐） 421835 六、申請專利範圍 體封裝，其中該散熱導電蓋與該些線路接點之一電性連 接。 7. 如申請專利範圍第1項所述加強散熱及電性之半導 體封裝，其中該散熱導電蓋更包括一第一表面、一第二表 面及一側面，該凹穴係配置於該第一表面，而該第二表面 具有複數個鰭片。 8. 如申請專利範圍第7項所述加強散熱及電性之半導 體封裝，其中該側面具有複數個鰭片。 9. 如申請專利範圍第7項所述加強散熱及電性之半導 體封裝，其中該側面具有複數個凹槽。 10. 如申請專利範圍第1項所述加強散熱及電性之半導 體封裝，其中該散熱導電蓋更包括一第一表面、一第二表 面及一側面，該凹穴係配置於該第一表面，而該第二表面 具有複數個凹槽。 11. 如申請專利範圍第10項所述加強散熱及電性之半 導體封裝，其中該側面具有複數個凹槽。 12. 如申請專利範圍第10項所述加強散熱及電性之半 導體封裝，其中該側面具有複數個鰭片。 經濟部中史標隼局員工消費合作社印裝 '(請先閲讀背面之注意事項"I寫本頁) 13. 如申請專利範圍第1項所述加強散熱及電性之半導 體封裝，其中該散熱導電蓋僅具散熱功能。 14. 如申請專利範圍第1項所述加強散熱及電性之半導 體封裝，其中該散熱導電蓋僅具導電功能。 15. 如申請專利範圍第1項所述加強散熱及電性之半導 體封裝，其中該散熱導電蓋兼具散熱及導電功能。 14 本纸張尺度適用中國國家標準（CNS ) 格（210X297公釐） 經濟部中央榡率局貝工消費合作社印装 42183 5 Ag 4492twf./005 B8 C8 D8 六、申請專利範圍 16. —種加強散熱及電性之半導體封裝，包括： 一基板，該基板至少具有複數個線路接點以及複數個 散熱接點； 一晶片，該晶片具有一第一表面及一第二表面，該晶 片以該第一表面面向該基板的方式配置於該基板上，其中 該第一表面至少具有複數個焊墊，每一該些焊墊上分別配 置有一凸塊，且部分該些焊墊分別與該些線路接點以該些 凸塊電性連接，而部分該些焊墊則分別與該些散熱接點以 該些凸塊連接； 一塡充材料，充滿於該晶片之該第一表面與該基板之 間； 一散熱導電蓋，該散熱導電蓋具有一凹穴，該散熱導 電蓋覆蓋於該晶片上，並與該基板接合，使得該晶片位於 該凹穴中；以及 一導熱封裝材料，配置於該晶片之該第二表面，使得 該晶片之該第二表面與該散熱導電蓋接合。 17. 如申請專利範圍第16項所述加強散熱及電性之半 導體封裝，其中該基板包括積層板。 18. 如申請專利範圍第16項所述加強散熱及電性之半 導體封裝，其中該基板包括球格狀陣列式封裝基板。 19. 如申請專利範圍第16項所述加強散熱及電性之半 導體封裝，其中該導熱封裝材料充滿該凹穴。 20. 如申請專利範圍第16項所述加強散熱及電性之半 導體封裝，其中該晶片及該導熱封裝材料與該凹穴間具有 I i I 1 裝 訂 ·~線 (請先閱讀背面之注意事項，埃寫本頁) . 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 經濟部中央標率局貝工消費合作社印製 42 183 5 A8 4492twf./〇〇5 B8 C8 D8 六、申請專利範圍 一空隙。 21. 如申請專利範圍第I6項所述加強散熱及電性之半 導體封裝，其中該散熱導電蓋與該些線路接點之一電性連 接。 22. 如申請專利範圍第Ιό項所述加強散熱及電性之半 導體封裝，其中該散熱導電蓋更包括一第一表面、一第二 表面及一側面，該凹穴係配置於該第一表面，而該第二表 面具有複數個鰭片。 23. 如申請專利範圍第22項所述加強散熱及電性之半 導體封裝，其中該側面具有複數個鰭片。 24·如申請專利範圍第22項所述加強散熱及電性之半 導體封裝，其中該側面具有複數個凹槽。 25_如申請專利範圍第Ιό項所述加強散熱及電性之半 導體封裝，其中該散熱導電蓋更包括一第一表面、一第二 表面及一側面，該凹穴係配置於該第一表面，而該第二表 面具有複數個凹槽。 26·如申請專利範圍第25項所述加強散熱及電性之半 導體封裝，其中該側面具有複數個凹槽。 27·如申請專利範圍第25項所述加強散熱及電性之半 導體封裝，其中該側面具有複數個鰭片。 28.如申請專利範圍第16項所述加強散熱及電性之半 導體封裝，其中該散熱導電蓋僅具散熱功能。 29·如申請專利範圍第16項所述加強散熱及電性之半 導體封裝，其中該散熱導電蓋僅具導電功能。 ---；------寒------ir----- (請先《讀背面之注意事項，，-埃寫本頁) 本紙涑尺度逋用中國國家樣準{ CNS ) ΑΊ说格（210Χ297公釐） 421835 A8 4492twf.y〇05 Βδ C8 D8 六、申請專利範圍3〇·如申請專利範圍第16項所述加強散熱及電性之半 導體封裝，其中該散熱導電蓋兼具散熱及導電功能。 ---------i------ΐτ----- I > (請先閲讀背面之注意事項埃寫本頁) 經濟部中央標準局員工消f合作，杜印製 本紙伕尺度適用中國國家標準（CNS ) A4規格（2丨OX297公釐）421835 4492twf./005 A8 B8 C8 D8 Application scope 1. A semiconductor package with enhanced heat dissipation and electrical properties, comprising: a substrate, the substrate having at least a plurality of circuit contacts and a plurality of heat dissipation contacts; a chip, The wafer has a first surface and a second surface, and the wafer is disposed on the substrate with the second surface facing the substrate, wherein the first surface has at least a plurality of pads, and each of the pads A wire is electrically connected to the line contacts, and the second surface is connected to the heat-dissipating contacts. A liquid packaging material covers the chip, the wires, the line-contacts, and the heat-dissipating connections. And a heat-dissipating conductive cover, the heat-dissipating conductive cover has a cavity, the heat-dissipating conductive cover covers the liquid packaging material and is bonded to the substrate, so that the liquid packaging material is located in the cavity, and the liquid package A material is bonded to the heat-dissipating conductive cover. 2. The semiconductor package with enhanced heat dissipation and electrical properties as described in item 1 of the scope of patent application, wherein the substrate includes a laminated board. 3. The semiconductor package with enhanced heat dissipation and electrical properties as described in item 1 of the scope of the patent application, wherein the substrate includes a ball grid array package substrate. Printed by the Consumers' Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs · (Please read the precautions on the back and then write this page) The cavity is filled with material. 5. The semiconductor package with enhanced heat dissipation and electrical properties as described in item 1 of the scope of patent application, wherein a gap is formed between the liquid packaging material and the cavity, and the liquid packaging material and the heat dissipation conductive cover are joined by a thermally conductive packaging material . 6. The semi-conducting paper with enhanced heat dissipation and electrical properties as described in item 1 of the scope of the patent application is applicable to the Chinese National Standard (CNS) A4 wash case (2I0X297 mm) 421835 6. The scope of the patent application is packaged, where the heat dissipation is conductive The cover is electrically connected to one of the line contacts. 7. The semiconductor package with enhanced heat dissipation and electrical properties as described in item 1 of the scope of the patent application, wherein the heat dissipation conductive cover further includes a first surface, a second surface, and a side surface, and the cavity is disposed on the first surface. , And the second surface has a plurality of fins. 8. The semiconductor package with enhanced heat dissipation and electrical properties as described in item 7 of the scope of patent application, wherein the side has a plurality of fins. 9. The semiconductor package with enhanced heat dissipation and electrical properties as described in item 7 of the scope of patent application, wherein the side has a plurality of grooves. 10. The semiconductor package with enhanced heat dissipation and electrical properties as described in item 1 of the scope of the patent application, wherein the heat dissipation conductive cover further includes a first surface, a second surface, and a side surface, and the cavity is disposed on the first surface. , And the second surface has a plurality of grooves. 11. The semiconductor package with enhanced heat dissipation and electrical properties as described in item 10 of the scope of patent application, wherein the side has a plurality of grooves. 12. The semiconductor package with enhanced heat dissipation and electrical properties as described in item 10 of the scope of patent application, wherein the side surface has a plurality of fins. Printed by the Consumers' Cooperatives of the Shibuya Bureau of the Ministry of Economic Affairs (please read the precautions on the back & I write this page) 13. A semiconductor package with enhanced heat dissipation and electrical properties as described in item 1 of the scope of patent application, where The heat-dissipating conductive cover only has a heat-dissipating function. 14. The semiconductor package with enhanced heat dissipation and electrical properties as described in item 1 of the scope of patent application, wherein the heat dissipation conductive cover only has a conductive function. 15. The semiconductor package with enhanced heat dissipation and electrical properties as described in item 1 of the scope of the patent application, wherein the heat dissipation conductive cover has both heat dissipation and conductivity functions. 14 This paper size applies the Chinese National Standard (CNS) grid (210X297 mm). Printed by the Bayer Consumer Cooperative of the Central Bureau of the Ministry of Economic Affairs. 42183 5 Ag 4492twf./005 B8 C8 D8. 6. The scope of patent application 16. — Strengthening A heat-dissipating and electrical semiconductor package includes: a substrate having at least a plurality of circuit contacts and a plurality of heat-dissipating contacts; a wafer having a first surface and a second surface; A surface is disposed on the substrate with the surface facing the substrate, wherein the first surface has at least a plurality of pads, and each of the pads is provided with a bump, and some of the pads are respectively connected to the circuit contacts. The bumps are electrically connected, and some of the pads are respectively connected to the heat dissipation contacts by the bumps; a filling material is filled between the first surface of the wafer and the substrate; A heat-dissipating conductive cover having a cavity, the heat-dissipating conductive cover covering the wafer and being bonded to the substrate so that the wafer is located in the cavity; and a heat-conducting packaging material, It is arranged on the second surface of the wafer such that the second surface of the wafer is engaged with the heat-dissipating conductive cover. 17. The semiconductor package with enhanced heat dissipation and electrical properties as described in item 16 of the scope of patent application, wherein the substrate includes a laminated board. 18. The semiconductor package with enhanced heat dissipation and electrical properties as described in item 16 of the scope of patent application, wherein the substrate comprises a ball grid array package substrate. 19. The semiconductor package with enhanced heat dissipation and electrical properties as described in item 16 of the scope of patent application, wherein the thermally conductive packaging material fills the cavity. 20. The semiconductor package with enhanced heat dissipation and electrical properties as described in item 16 of the scope of the patent application, wherein the chip and the thermally conductive packaging material and the cavity have I i I 1 binding · ~ lines (please read the precautions on the back first) (This page is written in Egypt). This paper size is in accordance with the Chinese National Standard (CNS) A4 (210X297 mm). Printed by the Shell Standard Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 42 183 5 A8 4492twf./〇〇5 B8 C8 D8 A gap in the scope of patent application. 21. The semiconductor package with enhanced heat dissipation and electrical properties as described in item I6 of the scope of patent application, wherein the heat conductive cover is electrically connected to one of the line contacts. 22. The semiconductor package with enhanced heat dissipation and electrical properties as described in item 1 of the patent application scope, wherein the heat-dissipating conductive cover further includes a first surface, a second surface, and a side surface, and the recess is disposed on the first surface. , And the second surface has a plurality of fins. 23. The semiconductor package with enhanced heat dissipation and electrical properties as described in item 22 of the scope of patent application, wherein the side surface has a plurality of fins. 24. The semiconductor package with enhanced heat dissipation and electrical properties as described in item 22 of the scope of patent application, wherein the side surface has a plurality of grooves. 25_ The semiconductor package with enhanced heat dissipation and electrical properties as described in item 1 of the patent application scope, wherein the heat dissipation conductive cover further includes a first surface, a second surface, and a side surface, and the recess is disposed on the first surface , And the second surface has a plurality of grooves. 26. The semiconductor package with enhanced heat dissipation and electrical properties as described in item 25 of the scope of patent application, wherein the side surface has a plurality of grooves. 27. The semiconductor package with enhanced heat dissipation and electrical properties as described in item 25 of the scope of patent application, wherein the side surface has a plurality of fins. 28. The semiconductor package with enhanced heat dissipation and electrical properties as described in item 16 of the scope of patent application, wherein the heat dissipation conductive cover only has a heat dissipation function. 29. The semiconductor package with enhanced heat dissipation and electrical properties as described in item 16 of the scope of patent application, wherein the heat dissipation conductive cover only has a conductive function. ---; ------ cold ------ ir ----- (Please read the "Cautions on the back, -Egypt write this page") The standard of this paper is based on Chinese national standards { CNS) AA grid (210 × 297 mm) 421835 A8 4492twf.y005 Βδ C8 D8 6. Application for patent scope 30. The semiconductor package with enhanced heat dissipation and electrical properties as described in item 16 of the scope of patent application, wherein the heat dissipation is conductive The cover has both heat dissipation and conductive functions. --------- i ------ ΐτ ----- I > (Please read the notes on the back first and write this page) Staff of the Central Bureau of Standards of the Ministry of Economic Affairs cooperate with Du Yin The paper scale of the paper is applicable to the Chinese National Standard (CNS) A4 (2 丨 OX297 mm)
TW88105918A 1999-04-14 1999-04-14 Semiconductor package with enhanced heat dissipation and electric properties TW421835B (en)

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