JPH04119653A - Integrated circuit element - Google Patents
Integrated circuit elementInfo
- Publication number
- JPH04119653A JPH04119653A JP24028290A JP24028290A JPH04119653A JP H04119653 A JPH04119653 A JP H04119653A JP 24028290 A JP24028290 A JP 24028290A JP 24028290 A JP24028290 A JP 24028290A JP H04119653 A JPH04119653 A JP H04119653A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- metal plate
- insulator
- circuit chip
- wiring lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910052751 metal Inorganic materials 0.000 claims abstract description 22
- 239000002184 metal Substances 0.000 claims abstract description 22
- 239000012212 insulator Substances 0.000 claims abstract description 12
- 238000005530 etching Methods 0.000 claims abstract description 7
- 238000007650 screen-printing Methods 0.000 claims description 4
- 238000000034 method Methods 0.000 abstract description 13
- 239000011347 resin Substances 0.000 abstract description 7
- 229920005989 resin Polymers 0.000 abstract description 7
- 229920001721 polyimide Polymers 0.000 abstract description 5
- 238000007789 sealing Methods 0.000 abstract description 4
- 239000004065 semiconductor Substances 0.000 abstract description 4
- 229910000679 solder Inorganic materials 0.000 abstract description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052782 aluminium Inorganic materials 0.000 abstract description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 2
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 229910052709 silver Inorganic materials 0.000 abstract description 2
- 239000004332 silver Substances 0.000 abstract description 2
- 230000000630 rising effect Effects 0.000 abstract 1
- 239000011295 pitch Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 238000004080 punching Methods 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】 〈産業上の利用分野〉 本発明は、集積回路素子の改善に関する。[Detailed description of the invention] <Industrial application field> The present invention relates to improvements in integrated circuit devices.
〈従来の技術〉
半導体集積回路、特に特定用途向は半導体集積回路のよ
うな多機能を有する半導体集積回路の分野では、端子数
が増加する傾向にある。<Prior Art> In the field of semiconductor integrated circuits, especially multifunctional semiconductor integrated circuits such as semiconductor integrated circuits for specific applications, the number of terminals tends to increase.
これに伴なって集積回路チップでは、高集積化が望まれ
、サイズ面での制約を受けており、ワイヤーボンディン
グ用配線バッドのサイズ及びピッチも減少傾向をたどっ
ている。Along with this, integrated circuit chips are desired to be highly integrated and are subject to size constraints, and the size and pitch of wiring pads for wire bonding are also on the decline.
また、それに対応するリードフレームも、リードの多ビ
ン化、並びにインナーリードの狭ピッチ化の要求が高ま
っており、インナーリード部平坦幅も減少しでいる。In addition, there is an increasing demand for lead frames to have more bins of leads and narrower pitches of inner leads, and the flat width of the inner lead portions is also decreasing.
ところで、リードフレームの作製方法には、：レス打ち
抜きによるスタンピング法あるいは、＝オドエンチング
プロセス法の三方法がある。スづンピング法は、ｌｏｏ
ピン程度までの少ピンリードフレームには対応できるが
、それ以上になっズくると困難となってくる。また、金
型は非常に正価であり、劣化も激しくコスト面で問題が
ある。By the way, there are three methods for producing a lead frame: a stamping method using non-less punching, and an odo-enching process method. The szumping method is loo
Although it can be used for lead frames with a small number of pins, it becomes difficult when the number of pins increases beyond that. In addition, the mold is very expensive and deteriorates rapidly, creating a problem in terms of cost.
エツチング法については、多ビン化には対応ｉ能である
が、フォトファプリケージタンの工程力レジスト塗付、
露光、現像、レジスト剥離などユ程が多く複雑であり、
やはりコストの面から間層がある。As for the etching method, it is capable of handling a large number of bins, but the process strength of photofabrication resist coating,
There are many steps such as exposure, development, and resist peeling, which are complicated.
There is still a gap in terms of cost.
多ビン、狭ピッチのリードフレームにおいては集積回路
チップとリードフレームとのＳａを図るために行われる
自動ワイヤーポンディングの際、特に、インナーリード
位置精度の高さ、安定化が要求されてくる。ところが、
リードフレーム材料の板厚はサイドエッチを少なくする
ために薄板化し、また、インナーリード部の平坦幅も減
少し、インナーリードの位１精度は逆に低くなる要素が
多くなってきている。In a multi-bin, narrow-pitch lead frame, high accuracy and stability in inner lead position are particularly required during automatic wire bonding performed to improve Sa between the integrated circuit chip and the lead frame. However,
The thickness of the lead frame material has become thinner in order to reduce side etching, and the flat width of the inner lead portion has also been reduced, resulting in an increasing number of factors that are decreasing the accuracy of the inner lead.
第２回に示すように、従来の集積回路素子は、鉄−二、
ケル合金や銅合金等を、打ち抜きあるいはフォトエンチ
ングプロセスにより作製されたリードフレーム９のアイ
ランド部に集積回路チップｌＯが導電性ペースト等を用
いたダイポンディングにより設置された構成となってい
る。As shown in Part 2, conventional integrated circuit devices are
The integrated circuit chip 1O is installed by die bonding using a conductive paste or the like on the island portion of a lead frame 9 made of Kell alloy, copper alloy, etc., by punching or photo-etching process.
集積回路チップとＩＪ−ドフレームとの導通は、集積回
路チンプ上のバンド電極とリードフレームのインナーリ
ードとが、金線等１１を用いたワイヤーポンディングに
よって得られている。Conductivity between the integrated circuit chip and the IJ-deframe is obtained by wire bonding between the band electrode on the integrated circuit chip and the inner lead of the lead frame using a gold wire or the like 11.
その後、集積回路チップ、ワイヤー インナーリード部
は樹脂１２でモールドされ、最後にプリント配線板等へ
の実装のためトリムアンドフオームによってアウターリ
ードを各々に切り離し、先端曲げ加工を行っている。Thereafter, the integrated circuit chip and wire inner lead portions are molded with resin 12, and finally, the outer leads are separated into individual parts by trim and form for mounting on a printed wiring board, etc., and the ends are bent.
プリント板への実装は、アウターリード部に半田めっき
層を形成後、プリント配線板への接続を行うのが通常の
方法であった。The usual method for mounting on a printed circuit board is to form a solder plating layer on the outer lead portion and then connect to the printed wiring board.
〈発明が解決しようとする課題〉
近年、集積回路チップの高集積化に伴い、チップ内で発
生する熱量も増加しリードフレームによる放熱だけでは
、素子内部が高温化するという熱放散性の問題も出てき
ている。<Problems to be solved by the invention> In recent years, as integrated circuit chips have become more highly integrated, the amount of heat generated within the chips has also increased, and heat dissipation problems have arisen in which the internal temperature of the elements increases if heat is dissipated only by lead frames. It's coming out.
プリント配線板への実装においても、多ピン化狭ピッチ
化が進むにつれて、アウターリード先端部の位置不安定
さによって配線パターンへの位置合わせが困難となって
きている。In mounting on printed wiring boards, as the number of pins increases and the pitch becomes narrower, alignment with the wiring pattern is becoming difficult due to the instability of the position of the tip of the outer lead.
〈課題を解決するための手段〉
すなわち本発明は、
集積回路チップが金属板上に設置され、前記チップを包
囲するように絶縁体が前記金属板上に積層された構成で
あり、
プリント配線板等の外部回路との電気的導通を得るため
の配線リードパターンが前記絶縁体表面に形成されたこ
とを特徴とする集積回路素子である。<Means for Solving the Problems> That is, the present invention has a configuration in which an integrated circuit chip is installed on a metal plate, and an insulator is laminated on the metal plate so as to surround the chip, and a printed wiring board. The integrated circuit element is characterized in that a wiring lead pattern is formed on the surface of the insulator to obtain electrical continuity with an external circuit such as the above.
〈発明の詳述〉
本発明は、従来の金属製リードフレームに替わるものと
して、
樹脂フィルム、シート等の絶縁体上に、スクリーン印刷
、めっき等により、絶縁体上に支持・固定された配線リ
ードパターンを形成することにより、作製工程の短縮、
容易化、コストａ減、インナーリード、アウターリード
の位置精度の確保を図ったものである。<Detailed Description of the Invention> The present invention provides a wiring lead that is supported and fixed on an insulator such as a resin film or sheet by screen printing, plating, etc., as an alternative to a conventional metal lead frame. By forming a pattern, the manufacturing process can be shortened,
This is intended to simplify the process, reduce costs, and ensure positional accuracy of the inner and outer leads.
また、集積回路チップを金属板上に設置し、前記チップ
と逆側の金属表面を露出し、更には、前記表面をハーフ
エンチング等の方法で、金属板の板厚方向の途中まで溝
を設け、金属部表面積を増加させたことにより、集積回
路素子内部に発生した熱の放散性を向上させたものであ
る。In addition, an integrated circuit chip is placed on a metal plate, the metal surface on the opposite side of the chip is exposed, and a groove is formed halfway in the thickness direction of the metal plate by half-etching or other methods. By increasing the surface area of the metal part, the dissipation of heat generated inside the integrated circuit element is improved.
更に、配線リードパターン上への半田等にょるバンプ形
成は、プリント配線板等外部回路への接続の簡略化を図
るものである。Furthermore, forming bumps using solder or the like on the wiring lead pattern is intended to simplify connection to an external circuit such as a printed wiring board.
加えて、表裏両面からの絶縁体により、穴を設けた金属
板をはめ込むことにより、絶縁板である配線リードパタ
ーン支持体と金属板との密着力を高めることができる。In addition, by fitting the metal plate provided with holes with insulators on both the front and back sides, it is possible to increase the adhesion between the wiring lead pattern support, which is an insulating plate, and the metal plate.
〈実施例〉 以下、実施例により本発明をさらに詳細に説明する。<Example> Hereinafter, the present invention will be explained in more detail with reference to Examples.
第１図に示すような集積回路素子を試作した。An integrated circuit device as shown in FIG. 1 was prototyped.
以下に製造工程を簡単に示す。The manufacturing process is briefly shown below.
まず、貫通孔２、およびハーフエツチングにより裏面に
溝３を形成した金属板１（４２合金０゜１ｍｍ厚）に、
１３ｍｍ角の穴を設けたポリイミドフィルム４ （０，
７ｍｍ厚）を熱圧着した。First, a metal plate 1 (alloy 42, 0°1 mm thick) with through holes 2 and grooves 3 formed on the back surface by half etching,
Polyimide film 4 with 13 mm square holes (0,
7 mm thick) was thermocompression bonded.
そのポリイミドフィルム表面に導電性ペーストを用いて
スクリーン印刷を行い、胴厚３０μｍ。Screen printing was performed on the surface of the polyimide film using conductive paste, and the body thickness was 30 μm.
リードピッチ２２０μｍ、リード幅１００μｍの配線リ
ードパターン５を形成した。A wiring lead pattern 5 having a lead pitch of 220 μm and a lead width of 100 μm was formed.
集積回路チップ６を金属板１上に、銀ペーストを用いて
グイポンディングを行った。The integrated circuit chip 6 was bonded onto the metal plate 1 using silver paste.
ロ チ プの
パッド数 ２０８
チップサイズ １１．２ Ｘ １０．９２ （ｍｍ２）
チップ厚 ５２５（μｍ）
バッドサイズ １１０．６ ｘ １１０．６ （μｍ
２ ）バッドピッチ １８０（μｍ）
次に、集積回路チップのアルミバッド電極と配線リード
パターン５とを、自動ワイヤーボンダーを用いて、金線
７（３０μｍφ）でワイヤーポンディングを行った。Number of pads on chip 208 Chip size 11.2 x 10.92 (mm2)
Chip thickness 525 (μm) Bud size 110.6 x 110.6 (μm
2) Pad pitch: 180 (μm) Next, wire bonding was performed between the aluminum pad electrodes of the integrated circuit chip and the wiring lead pattern 5 using a gold wire 7 (30 μmφ) using an automatic wire bonder.
次いで、封止用樹脂を用いて、両面から同時に８ａ、ａ
ｂ部の樹脂封止を行った。Next, using sealing resin, seal 8a and a from both sides at the same time.
Part b was sealed with resin.
最後に、半田ペーストを用いてボッティング法によりバ
ンプ９を形成し、プリント配線板への実装を行った。Finally, bumps 9 were formed by a botting method using solder paste, and mounting on a printed wiring board was performed.
〈発明の効果〉
本発明の集積回路素子により、以下のような効果が得ら
れた。<Effects of the Invention> The following effects were obtained by the integrated circuit device of the present invention.
■配線リードパターンの形成が、スクリーン印刷による
ため容易であった。■The wiring lead pattern was easily formed by screen printing.
■配線リードパターンが、絶縁体上に支持・固定されて
いるため、自動ワイヤーポンディング時ならびにバンプ
形成と合わせて、プリント配線板への実装時に有利であ
った。■Since the wiring lead pattern is supported and fixed on the insulator, it is advantageous during automatic wire bonding and bump formation, as well as when mounting on printed wiring boards.
■金属板からの熱放出性にも大きな効果が得られた。■A great effect was also obtained on heat release from the metal plate.
第１図は、本発明による集積回路素子の断面構造を示す
説明図であり、第２図は、従来の集積回路素子の断面構
造を示す説明図であるウド・・金属板
２・・・貫通孔
３・・・溝（ハーフエツチング）
４・・・絶縁体（ポリイミドフィルム）５・・・配線リ
ードパターン
６．１１・・・集積回路チ、７ブ
７．１２・・・ワイヤー
８ａ、８ｂ・・・封止用樹脂
９・・・バンブ
ｌＯ・・・リードフレーム
１３・・・樹脂封止部FIG. 1 is an explanatory diagram showing the cross-sectional structure of an integrated circuit element according to the present invention, and FIG. 2 is an explanatory diagram showing the cross-sectional structure of a conventional integrated circuit element. Hole 3...Groove (half etching) 4...Insulator (polyimide film) 5...Wiring lead pattern 6.11...Integrated circuit chip, 7b 7.12...Wire 8a, 8b. ...Sealing resin 9...Bumble lO...Lead frame 13...Resin sealing part
Claims (1)
を包囲するように絶縁体が前記金属板上に積層された構
成であり、 プリント配線板等の外部回路との電気的導通を得るため
の配線リードパターンが前記絶縁体表面に形成されたこ
とを特徴とする集積回路素子。 ２）配線リード部分にバンプが形成されていることを特
徴とする請求項１記載の集積回路素子。 ３）配線リードパターンの形成された絶縁体が、金属板
を介して逆側に形成された絶縁体と、金属板に設けられ
た貫通孔を通して一体となって固定されていることを特
徴とする請求項１または請求項２に記載の集積回路素子
。 ４）集積回路チップが設置された逆側の金属板表面に、
ハーフエッチングにより溝部が形成されたことを特徴と
する請求項１〜請求項３のいずれかに記載の集積回路素
子。 ５）配線リードパターンが、スクリーン印刷によって形
成されたことを特徴とする請求項１〜請求項４のいずれ
かに記載の集積回路素子。[Claims] 1) An integrated circuit chip is installed on a metal plate, and an insulator is laminated on the metal plate so as to surround the chip, and there is no connection with an external circuit such as a printed wiring board. An integrated circuit device characterized in that a wiring lead pattern for obtaining electrical continuity is formed on the surface of the insulator. 2) The integrated circuit device according to claim 1, wherein bumps are formed on the wiring lead portions. 3) The insulator on which the wiring lead pattern is formed is fixed integrally with the insulator formed on the opposite side of the metal plate through a through hole provided in the metal plate. An integrated circuit device according to claim 1 or claim 2. 4) On the surface of the metal plate on the opposite side where the integrated circuit chip is installed,
4. The integrated circuit device according to claim 1, wherein the groove portion is formed by half etching. 5) The integrated circuit device according to claim 1, wherein the wiring lead pattern is formed by screen printing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24028290A JPH04119653A (en) | 1990-09-11 | 1990-09-11 | Integrated circuit element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24028290A JPH04119653A (en) | 1990-09-11 | 1990-09-11 | Integrated circuit element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04119653A true JPH04119653A (en) | 1992-04-21 |
Family
ID=17057170
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24028290A Pending JPH04119653A (en) | 1990-09-11 | 1990-09-11 | Integrated circuit element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04119653A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1997044822A1 (en) * | 1995-05-11 | 1997-11-27 | National Semiconductor Corporation | Ultra thin ball grid array package using a flex tape or printed wiring board substrate and method |
| WO1999044233A1 (en) * | 1998-02-24 | 1999-09-02 | Micron Technology, Inc. | Low profile ball grid array package |
| US6060778A (en) * | 1997-05-17 | 2000-05-09 | Hyundai Electronics Industries Co. Ltd. | Ball grid array package |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5631894A (en) * | 1979-08-18 | 1981-03-31 | Isao Okamoto | Diving system |
| JPS595977U (en) * | 1982-07-02 | 1984-01-14 | 菅原 通明 | Indoor ring for children |
| JPS6432652A (en) * | 1987-07-29 | 1989-02-02 | Hitachi Chemical Co Ltd | Manufacture of wiring board for loading semiconductor element |
-
1990
- 1990-09-11 JP JP24028290A patent/JPH04119653A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5631894A (en) * | 1979-08-18 | 1981-03-31 | Isao Okamoto | Diving system |
| JPS595977U (en) * | 1982-07-02 | 1984-01-14 | 菅原 通明 | Indoor ring for children |
| JPS6432652A (en) * | 1987-07-29 | 1989-02-02 | Hitachi Chemical Co Ltd | Manufacture of wiring board for loading semiconductor element |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1997044822A1 (en) * | 1995-05-11 | 1997-11-27 | National Semiconductor Corporation | Ultra thin ball grid array package using a flex tape or printed wiring board substrate and method |
| US6060778A (en) * | 1997-05-17 | 2000-05-09 | Hyundai Electronics Industries Co. Ltd. | Ball grid array package |
| WO1999044233A1 (en) * | 1998-02-24 | 1999-09-02 | Micron Technology, Inc. | Low profile ball grid array package |
| US6172419B1 (en) | 1998-02-24 | 2001-01-09 | Micron Technology, Inc. | Low profile ball grid array package |
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