JPH04119653A - Integrated circuit element - Google Patents
Integrated circuit elementInfo
- Publication number
- JPH04119653A JPH04119653A JP24028290A JP24028290A JPH04119653A JP H04119653 A JPH04119653 A JP H04119653A JP 24028290 A JP24028290 A JP 24028290A JP 24028290 A JP24028290 A JP 24028290A JP H04119653 A JPH04119653 A JP H04119653A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- metal plate
- circuit chip
- bonded
- lead pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910052751 metal Inorganic materials 0.000 abstract 5
- 239000002184 metal Substances 0.000 abstract 5
- 229920001721 Polyimide Polymers 0.000 abstract 2
- 239000012212 insulator Substances 0.000 abstract 2
- 229910052782 aluminium Inorganic materials 0.000 abstract 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminum Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 238000005530 etching Methods 0.000 abstract 1
- 238000005755 formation reaction Methods 0.000 abstract 1
- 239000011347 resin Substances 0.000 abstract 1
- 229920005989 resin Polymers 0.000 abstract 1
- 230000000630 rising Effects 0.000 abstract 1
- 238000007789 sealing Methods 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 abstract 1
- BQCADISMDOOEFD-UHFFFAOYSA-N silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 abstract 1
- 229910052709 silver Inorganic materials 0.000 abstract 1
- 239000004332 silver Substances 0.000 abstract 1
- 229910000679 solder Inorganic materials 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Abstract
PURPOSE: To improve an integrated circuit element in heat dissipating properties so as to prevent it from rising in temperature by a method wherein an insulator is laminated on a metal plate so as to surround the integrated circuit chip, and a wiring lead pattern is formed on the surface of the insulator to electrically connect the integrated circuit chip to an outer circuit such as a printed wiring board or the like.
CONSTITUTION: A through-holes 2 are provided to a metal plate 1, a groove 3 is provided to the rear of the plate 1 through half-etching, and a polyimide film 4 is bonded to the plate 1 through thermocompression. Conductive paste is printed on the surface of the polyimide film 4 for the formation of a wiring lead pattern 5. An integrated circuit chip 6 is bonded to the metal plate 1 with silver paste. In succession, the aluminum pad electrode of the integrated circuit chip 6 is wire-bonded to the wiring lead pattern 5. Then, the rear and the front of the metal plate 1 are sealed up with sealing resin (8a and 8b), and last of all, bumps 9 are formed of solder paste. By this setup, a semiconductor integrated circuit element of this design can be improved in heat dissipating properties through a metal plate.
COPYRIGHT: (C)1992,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24028290A JPH04119653A (en) | 1990-09-11 | 1990-09-11 | Integrated circuit element |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24028290A JPH04119653A (en) | 1990-09-11 | 1990-09-11 | Integrated circuit element |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04119653A true JPH04119653A (en) | 1992-04-21 |
Family
ID=17057170
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP24028290A Pending JPH04119653A (en) | 1990-09-11 | 1990-09-11 | Integrated circuit element |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04119653A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1997044822A1 (en) * | 1995-05-11 | 1997-11-27 | National Semiconductor Corporation | Ultra thin ball grid array package using a flex tape or printed wiring board substrate and method |
WO1999044233A1 (en) * | 1998-02-24 | 1999-09-02 | Micron Technology, Inc. | Low profile ball grid array package |
US6060778A (en) * | 1997-05-17 | 2000-05-09 | Hyundai Electronics Industries Co. Ltd. | Ball grid array package |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5631894A (en) * | 1979-08-18 | 1981-03-31 | Isao Okamoto | Diving system |
JPS595977U (en) * | 1982-07-02 | 1984-01-14 | ||
JPS6432652A (en) * | 1987-07-29 | 1989-02-02 | Hitachi Chemical Co Ltd | Manufacture of wiring board for loading semiconductor element |
-
1990
- 1990-09-11 JP JP24028290A patent/JPH04119653A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5631894A (en) * | 1979-08-18 | 1981-03-31 | Isao Okamoto | Diving system |
JPS595977U (en) * | 1982-07-02 | 1984-01-14 | ||
JPS6432652A (en) * | 1987-07-29 | 1989-02-02 | Hitachi Chemical Co Ltd | Manufacture of wiring board for loading semiconductor element |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1997044822A1 (en) * | 1995-05-11 | 1997-11-27 | National Semiconductor Corporation | Ultra thin ball grid array package using a flex tape or printed wiring board substrate and method |
US6060778A (en) * | 1997-05-17 | 2000-05-09 | Hyundai Electronics Industries Co. Ltd. | Ball grid array package |
WO1999044233A1 (en) * | 1998-02-24 | 1999-09-02 | Micron Technology, Inc. | Low profile ball grid array package |
US6172419B1 (en) | 1998-02-24 | 2001-01-09 | Micron Technology, Inc. | Low profile ball grid array package |
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