TW201405718A - Substrate structure and die package integrating the substrate structure - Google Patents
Substrate structure and die package integrating the substrate structure Download PDFInfo
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- TW201405718A TW201405718A TW101125980A TW101125980A TW201405718A TW 201405718 A TW201405718 A TW 201405718A TW 101125980 A TW101125980 A TW 101125980A TW 101125980 A TW101125980 A TW 101125980A TW 201405718 A TW201405718 A TW 201405718A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Abstract
Description
本發明係有關於一種基板結構及封裝件，尤指一種用於覆晶封裝之基板結構及封裝件。 The invention relates to a substrate structure and a package, in particular to a substrate structure and a package for a flip chip package.
一般覆晶封裝件包括覆晶球柵陣列(FCBGA)封裝(如第1圖所示)及覆晶晶片尺寸封裝(flip chip chip scale package，FCCSP)兩種，其兩者差異在於：覆晶球柵陣列(FCBGA)封裝之封裝基板較大且厚度高，故剛性較強，而多使用在中央處理單元(CPU)及圖形處理單元(GPU)之承載及電性連接上，通常覆晶球柵陣列(FCBGA)封裝之製法係先將半導體晶片11接置於封裝基板10上，並於半導體晶片11與封裝基板10間以毛細底部填充(CUF)技術填充有保護膠材12，以保護銲球13並使該半導體晶片11之非主動面111裸露，俾使該非主動面111做為接置散熱件(未圖示)之用。 Generally, the flip chip package includes a flip chip ball grid array (FCBGA) package (as shown in FIG. 1 ) and a flip chip chip scale package (FCCSP), the difference between the two being: a flip chip The package array of the gate array (FCBGA) package is large and has a high thickness, so the rigidity is strong, and it is often used in the bearing and electrical connection of a central processing unit (CPU) and a graphics processing unit (GPU), usually a flip-chip ball grid. The array (FCBGA) package is formed by first attaching the semiconductor wafer 11 to the package substrate 10, and filling the protective paste 12 between the semiconductor wafer 11 and the package substrate 10 by capillary underfill (CUF) technology to protect the solder balls. 13 and the inactive surface 111 of the semiconductor wafer 11 is exposed, and the inactive surface 111 is used as a heat sink (not shown).
相對地，如第2A與2B圖所示，分別係習知覆晶晶片尺寸封裝(FCCSP)之封裝件的剖視圖與封裝基板的俯視圖，覆晶晶片尺寸封裝(FCCSP)係用於面積較小且薄的封裝基板20，一般係用於行動式電子產品中，其封裝方式係採用所謂的模塑底部填充(MUF)技術，亦即無須如前述覆晶球柵陣列(FCBGA)封裝地於半導體晶片與封裝基板間填充有保護膠材，而是直接以封裝材料(Molding compound)22直接將半導體晶片21完全包覆於封裝基板20上，並使 該封裝材料22填充於半導體晶片21與封裝基板20間。覆晶晶片尺寸封裝(FCCSP)係無需另填充底充保護膠材於半導體晶片與封裝基板間，以節省工時及成本，又能直接用封裝材料22完全包覆半導體晶片21以保護半導體晶片21不受外界環境破壞，且該封裝材料22之剛性較強，所以可使得整個覆晶封裝件不易翹曲，進而改善可靠度問題。 In contrast, as shown in FIGS. 2A and 2B, respectively, a cross-sectional view of a package of a conventional flip chip size package (FCCSP) and a top view of a package substrate, and a flip chip size package (FCCSP) is used for a small area and The thin package substrate 20 is generally used in mobile electronic products in a packaged manner using so-called molded underfill (MUF) technology, that is, without the need to package a semiconductor wafer as described above in a flip chip array (FCBGA) package. The protective substrate is filled with the package substrate, and the semiconductor wafer 21 is directly coated on the package substrate 20 directly by the molding compound 22, and The encapsulation material 22 is filled between the semiconductor wafer 21 and the package substrate 20. The flip chip size package (FCCSP) eliminates the need to additionally fill the underfill protection between the semiconductor wafer and the package substrate to save man-hours and cost, and can completely encapsulate the semiconductor wafer 21 with the package material 22 to protect the semiconductor wafer 21. It is not damaged by the external environment, and the rigidity of the encapsulating material 22 is strong, so that the entire flip chip package is not easily warped, thereby improving the reliability problem.
於某些情況下，覆晶晶片尺寸封裝(FCCSP)用之封裝基板20的中央區域的銅層201需部分顯露於絕緣保護層23外，以供散熱、電性傳導或接地等用途。 In some cases, the copper layer 201 in the central region of the package substrate 20 for flip chip size package (FCCSP) needs to be partially exposed outside the insulating protective layer 23 for heat dissipation, electrical conduction, or grounding.
惟，覆晶晶片尺寸封裝(FCCSP)中的半導體晶片21投影至銅層201之邊緣位置A處具有較大之應力，故於溫度可靠度測試時，該邊緣位置A常會發生封裝材料22與銅層201剝離之問題，而導致整個封裝基板20無法通過可靠度測試。 However, the semiconductor wafer 21 in the flip chip size package (FCCSP) has a large stress projected to the edge position A of the copper layer 201. Therefore, when the temperature reliability test is performed, the edge position A often occurs with the package material 22 and copper. The problem of layer 201 peeling causes the entire package substrate 20 to fail the reliability test.
因此，如何避免上述習知技術中之種種問題，實已成為目前亟欲解決的課題。 Therefore, how to avoid various problems in the above-mentioned prior art has become a problem that is currently being solved.
有鑒於上述習知技術之缺失，本發明提供一種基板結構，係包括：基板結構，係包括：基板本體；金屬層，係形成於該基板本體之一表面上；絕緣保護層，係形成於該基板本體之該表面上，且具有外露該金屬層之至少一開口；以及至少一置晶區，係定義於該基板本體之該表面，以供於該表面上接置一半導體晶片，其中，一該置晶區係對應一該開口，一該置晶區之範圍係涵蓋一該開口之全 部，或者，該金屬層係未超出該置晶區之範圍。 The present invention provides a substrate structure, comprising: a substrate structure, comprising: a substrate body; a metal layer formed on a surface of the substrate body; and an insulating protective layer formed on the substrate The surface of the substrate body has at least one opening exposing the metal layer; and at least one crystal region is defined on the surface of the substrate body for receiving a semiconductor wafer on the surface, wherein The crystallographic region corresponds to an opening, and a range of the crystallographic region covers the entire opening Or, the metal layer does not extend beyond the crystallographic zone.
本發明復提供一種封裝件，係包括：基板本體；金屬層，係形成於該基板本體之一表面上；絕緣保護層，係形成於該基板本體之該表面上，且具有外露該金屬層之至少一開口；以及至少一半導體晶片，係接置於該金屬層上，其中，一該半導體晶片係對應一該開口，一該半導體晶片在該基板本體之該表面的投影範圍係涵蓋一該開口之全部，或者，該金屬層係未超出該半導體晶片在該基板本體之該表面的投影範圍。 The present invention further provides a package comprising: a substrate body; a metal layer formed on a surface of the substrate body; and an insulating protective layer formed on the surface of the substrate body and having the exposed metal layer At least one opening; and at least one semiconductor wafer is attached to the metal layer, wherein a semiconductor wafer corresponds to the opening, and a projection range of the semiconductor wafer on the surface of the substrate body covers the opening All or alternatively, the metal layer does not extend beyond the projection range of the semiconductor wafer on the surface of the substrate body.
由上可知，因為本發明係使半導體晶片投影至基板本體表面處未存在有外露之金屬層，並減少金屬層之整體外露面積，所以後續於該金屬層上覆蓋封裝材料後，不易發生習知之封裝材料與金屬層間的異質接面處的脫層現象(原理為金屬與封裝材料係為異質，其接著性較同質之高分子間之接著性為差，例如：封裝材料、絕緣保護層或基板本體表面之介電層(同質類)之間的接著性佳)，進而提升整體良率。 As can be seen from the above, since the present invention is such that the semiconductor wafer is projected onto the surface of the substrate body without the exposed metal layer, and the overall exposed area of the metal layer is reduced, subsequent covering of the metal layer with the packaging material is less likely to occur. The delamination phenomenon at the heterojunction between the encapsulating material and the metal layer (the principle is that the metal and the encapsulating material are heterogeneous, and the adhesion between the encapsulating material and the homogenous polymer is poor, for example, a packaging material, an insulating protective layer or a substrate The adhesion between the dielectric layers (homogeneous) on the surface of the body is good, which in turn improves overall yield.
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。 The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定 條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「上」、「中央」、「投影範圍」及「一」等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。 It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. Limited The conditions are not technically meaningful, and any modification of the structure, change of the proportional relationship or adjustment of the size should remain in the present invention without affecting the effects and the achievable objectives of the present invention. The technical content revealed can be covered. In the meantime, the terms "upper", "central", "projection" and "one" are used in this specification for the purpose of description and are not intended to limit the scope of the invention. Changes or adjustments to the relative relationship are considered to be within the scope of the invention without departing from the scope of the invention.
第3圖所示者，係本發明之基板結構及封裝件的第一實施例之剖視圖。其係先提供一種基板結構，該基板結構係包括：基板本體30，其材質可為ABF(Ajinomoto Build-up Film)、BCB(Benzocyclo-buthene)、LCP(Liquid Crystal Polymer)、PI(Poly-imide)、PPE(Poly(phenylene ether))、PTFE(Poly(tetra-fluoroethylene))、FR4、FR5、BT(Bismaleimide Triazine)、芳香尼龍(Aramide)、或混合環氧樹脂玻璃纖維(Glass fiber)；金屬層31，係形成於該基板本體30之一表面30a；絕緣保護層32(如防銲綠漆)，係形成於該基板本體30之該表面30a上，且具有外露該金屬層31之開口320；以及置晶區300，係定義於該基板本體30之該表面30a，以供於該表面30a上接置一半導體晶片33，其中，一該置晶區300係對應一該開口320，該置晶區300之範圍係涵蓋一該開口320之全部，且該置晶區300係較佳位於該開口320中央。 Figure 3 is a cross-sectional view showing a first embodiment of the substrate structure and package of the present invention. The substrate structure includes a substrate body 30, and the material thereof can be ABF (Ajinomoto Build-up Film), BCB (Benzocyclo-buthene), LCP (Liquid Crystal Polymer), PI (Poly-imide). ), PPE (Poly (phenylene ether)), PTFE (Poly (tetra-fluoroethylene)), FR4, FR5, BT (Bismaleimide Triazine), aromatic nylon (Aramide), or mixed epoxy glass fiber (Glass fiber); metal The layer 31 is formed on one surface 30a of the substrate body 30; an insulating protective layer 32 (such as a solder resist green paint) is formed on the surface 30a of the substrate body 30 and has an opening 320 for exposing the metal layer 31. And the crystallized area 300 is defined on the surface 30a of the substrate body 30 for attaching a semiconductor wafer 33 to the surface 30a, wherein the crystallizing area 300 corresponds to the opening 320. The extent of the crystal region 300 encompasses all of the opening 320, and the crystallographic region 300 is preferably located at the center of the opening 320.
本實施例之封裝件係於前述基板結構的置晶區300處接置半導體晶片33，使得該半導體晶片33係位於該開口320中央，其中，一該半導體晶片33係對應一該開口320，該半導體晶片33在該基板本體30之該表面30a的投影範圍係涵蓋一該開口320之全部，且該半導體晶片33的平面尺寸係大於該開口320之尺寸。 The package of the present embodiment is connected to the semiconductor wafer 33 at the crystallizing region 300 of the substrate structure, such that the semiconductor wafer 33 is located at the center of the opening 320, wherein the semiconductor wafer 33 corresponds to the opening 320. The projection range of the semiconductor wafer 33 on the surface 30a of the substrate body 30 covers all of the openings 320, and the planar size of the semiconductor wafer 33 is larger than the size of the opening 320.
於前述之封裝件中，復包括封裝材料34，係形成於該基板本體30之該表面30a上，以包覆該半導體晶片33。 In the foregoing package, a package material 34 is formed on the surface 30a of the substrate body 30 to cover the semiconductor wafer 33.
所述之封裝件中，該半導體晶片33係以覆晶方式接置於該金屬層31上，且該金屬層31之材質係為銅。 In the package, the semiconductor wafer 33 is placed on the metal layer 31 in a flip chip manner, and the material of the metal layer 31 is copper.
本實施例之封裝件中，該基板本體30之另一表面30b復具有複數銲球墊35，且復包括銲球36，係接置於各該銲球墊35上。 In the package of the embodiment, the other surface 30b of the substrate body 30 has a plurality of solder ball pads 35, and further includes solder balls 36, which are attached to the solder ball pads 35.
第4圖所示者，係本發明之基板結構及封裝件的第二實施例之剖視圖。其係先提供一種基板結構，該基板結構係包括：基板本體30；金屬層31，係形成於該基板本體30之一表面30a；絕緣保護層32，係形成於該基板本體30之該表面30a上，且具有外露該金屬層31之開口320；以及置晶區300，係定義於該基板本體30之該表面30a，以供於該表面30a上接置半導體晶片33，其中，該金屬層31係未超出該置晶區300之範圍，且該置晶區300係較佳位於該開口320中央。 Fig. 4 is a cross-sectional view showing a second embodiment of the substrate structure and package of the present invention. The substrate structure includes a substrate body 30, a metal layer 31 formed on one surface 30a of the substrate body 30, and an insulating protection layer 32 formed on the surface 30a of the substrate body 30. And having an opening 320 for exposing the metal layer 31; and the crystallizing region 300 is defined on the surface 30a of the substrate body 30 for receiving the semiconductor wafer 33 on the surface 30a, wherein the metal layer 31 The range of the crystallographic region 300 is not exceeded, and the crystallographic region 300 is preferably located at the center of the opening 320.
本實施例之封裝件係於前述基板結構的置晶區300處 接置半導體晶片33，使得該半導體晶片33係位於該開口320中央，其中，該金屬層31係未超出該半導體晶片33在該基板本體30之該表面30a的投影範圍。 The package of this embodiment is attached to the crystal former 300 of the substrate structure The semiconductor wafer 33 is attached such that the semiconductor wafer 33 is located in the center of the opening 320, wherein the metal layer 31 does not extend beyond the projection range of the semiconductor wafer 33 on the surface 30a of the substrate body 30.
本實施例之其他特徵大致與前一實施例相同，故不在此加以贅述。 Other features of this embodiment are substantially the same as those of the previous embodiment, and thus will not be described again.
要注意的是，於本發明之基板結構與封裝件中，該開口320復可外露該基板本體30表面之介電層(未圖示)，且該金屬層31復可包括線路(未圖示)與散熱墊(未圖示)。 It should be noted that, in the substrate structure and the package of the present invention, the opening 320 may expose a dielectric layer (not shown) on the surface of the substrate body 30, and the metal layer 31 may include a circuit (not shown). ) with a cooling pad (not shown).
綜上所述，相較於習知技術，由於本發明係使半導體晶片投影至基板本體表面處未存在有外露之金屬層，並減少金屬層之整體外露面積，所以後續於該金屬層上覆蓋封裝材料後，不易發生習知之封裝材料與金屬層間的異質接面處的脫層現象(原理為金屬與封裝材料係為異質，其接著性較同質之高分子間之接著性為差，例如：封裝材料、絕緣保護層或基板本體表面之介電層(同質類)之間的接著性佳)，進而提升整體良率。 In summary, compared with the prior art, since the present invention projects the semiconductor wafer to the surface of the substrate body without the exposed metal layer and reduces the overall exposed area of the metal layer, it is subsequently covered on the metal layer. After the encapsulation material, delamination at the heterojunction between the conventional encapsulation material and the metal layer is less likely to occur (the principle is that the metal and the encapsulation material are heterogeneous, and the adhesion between the polymer and the homogenous polymer is poor, for example: The encapsulation material, the insulating protective layer or the dielectric layer (homogeneous type) on the surface of the substrate body is excellent in adhesion, thereby improving the overall yield.
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。 The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.
10,20‧‧‧封裝基板 10,20‧‧‧Package substrate
11,21,33‧‧‧半導體晶片 11,21,33‧‧‧ semiconductor wafer
111‧‧‧非主動面 111‧‧‧Inactive surface
12‧‧‧保護膠材 12‧‧‧Protective glue
13,36‧‧‧銲球 13,36‧‧‧ solder balls
22,34‧‧‧封裝材料 22,34‧‧‧Encapsulation materials
201‧‧‧銅層 201‧‧‧ copper layer
23,32‧‧‧絕緣保護層 23,32‧‧‧Insulating protective layer
A‧‧‧邊緣位置 A‧‧‧ edge position
30‧‧‧基板本體 30‧‧‧Substrate body
30a,30b‧‧‧表面 30a, 30b‧‧‧ surface
300‧‧‧置晶區 300‧‧‧Setting area
31‧‧‧金屬層 31‧‧‧metal layer
320‧‧‧開口 320‧‧‧ openings
35‧‧‧銲球墊 35‧‧‧ solder ball mat
第1圖所示者係習知覆晶球柵陣列封裝件的剖視圖； 第2A與2B圖所示者分別係習知覆晶晶片尺寸封裝之封裝件的剖視圖與封裝基板的俯視圖；第3圖所示者係本發明之基板結構及封裝件的第一實施例之剖視圖；以及第4圖所示者係本發明之基板結構及封裝件的第二實施例之剖視圖。 Figure 1 is a cross-sectional view of a conventional flip chip ball grid array package; 2A and 2B are respectively a cross-sectional view of a package of a conventional flip chip size package and a top view of the package substrate; and FIG. 3 is a cross-sectional view of the first embodiment of the substrate structure and package of the present invention. And FIG. 4 is a cross-sectional view showing a second embodiment of the substrate structure and package of the present invention.
30‧‧‧基板本體 30‧‧‧Substrate body
30a,30b‧‧‧表面 30a, 30b‧‧‧ surface
300‧‧‧置晶區 300‧‧‧Setting area
31‧‧‧金屬層 31‧‧‧metal layer
32‧‧‧絕緣保護層 32‧‧‧Insulation protective layer
320‧‧‧開口 320‧‧‧ openings
33‧‧‧半導體晶片 33‧‧‧Semiconductor wafer
34‧‧‧封裝材料 34‧‧‧Packaging materials
35‧‧‧銲球墊 35‧‧‧ solder ball mat
36‧‧‧銲球 36‧‧‧ solder balls
Claims (13)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW101125980A TWI463610B (en) | 2012-07-19 | 2012-07-19 | Substrate structure and die package integrating the substrate structure |
| CN201210275824.0A CN103579168B (en) | 2012-07-19 | 2012-08-03 | Substrate structure and packaging piece with same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW101125980A TWI463610B (en) | 2012-07-19 | 2012-07-19 | Substrate structure and die package integrating the substrate structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201405718A true TW201405718A (en) | 2014-02-01 |
| TWI463610B TWI463610B (en) | 2014-12-01 |
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|---|---|---|---|
| TW101125980A TWI463610B (en) | 2012-07-19 | 2012-07-19 | Substrate structure and die package integrating the substrate structure |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN103579168B (en) |
| TW (1) | TWI463610B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI569339B (en) * | 2015-01-06 | 2017-02-01 | 矽品精密工業股份有限公司 | Method of fabricating a package structure and a package substrate thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| TWI629756B (en) * | 2017-08-14 | 2018-07-11 | 矽品精密工業股份有限公司 | Package structure and its package substrate |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6291268B1 (en) * | 2001-01-08 | 2001-09-18 | Thin Film Module, Inc. | Low cost method of testing a cavity-up BGA substrate |
| JP2004063770A (en) * | 2002-07-29 | 2004-02-26 | Fujitsu Ltd | Method of forming connection structure between electrodes |
| JP4052237B2 (en) * | 2003-12-12 | 2008-02-27 | ソニー株式会社 | Semiconductor device and manufacturing method thereof |
| JP4528062B2 (en) * | 2004-08-25 | 2010-08-18 | 富士通株式会社 | Semiconductor device and manufacturing method thereof |
| CN100485894C (en) * | 2005-09-20 | 2009-05-06 | 全懋精密科技股份有限公司 | Flip chip packaging method and packaging structure thereof |
| DE102005055280B3 (en) * | 2005-11-17 | 2007-04-12 | Infineon Technologies Ag | Connecting elements for semiconductor components have mushroom shape with first metal area filling out indentations on top of insulating layer and with second metal area on containing refractory inter-metallic phases of metals of solder |
| CN101064259A (en) * | 2006-04-25 | 2007-10-31 | 矽品精密工业股份有限公司 | Semiconductor package and its chip bearing structure and production method |
| CN101364582A (en) * | 2007-08-10 | 2009-02-11 | 全懋精密科技股份有限公司 | Loading board construction embedded with chip and preparation thereof |
| TWI389220B (en) * | 2007-10-22 | 2013-03-11 | 矽品精密工業股份有限公司 | Semiconductor package and method for fabricating the same |
| TWI349994B (en) * | 2008-01-30 | 2011-10-01 | Advanced Semiconductor Eng | Package process for embedded semiconductor device |
-
2012
- 2012-07-19 TW TW101125980A patent/TWI463610B/en active
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|---|---|---|---|---|
| TWI569339B (en) * | 2015-01-06 | 2017-02-01 | 矽品精密工業股份有限公司 | Method of fabricating a package structure and a package substrate thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103579168A (en) | 2014-02-12 |
| TWI463610B (en) | 2014-12-01 |
| CN103579168B (en) | 2016-05-04 |
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