TWI569339B - Method of fabricating a package structure and a package substrate thereof - Google Patents

Description

Method for manufacturing package structure and package substrate thereof

The invention relates to a packaging technology, in particular to a method for manufacturing a flip chip package structure and a package substrate used therefor.

With the development of the electronics industry, today's electronic products have been designed in a light, short, and versatile manner, and semiconductor packaging technologies have also developed different packaging types. In order to meet the high integration and miniaturization requirements of semiconductor devices, in addition to the conventional semiconductor technology of wire bonding, Flip chip can also be used to increase the wiring density. .

FIG. 1A is a schematic cross-sectional view of a conventional flip chip package structure 1. As shown in FIG. 1A, a semiconductor wafer 13 is bonded to the electrical contact pads 110 of the circuit layer 11 of the package substrate 10 by a plurality of solder bumps 130 and electrically connected to the conductive traces 111 of the circuit layer 11. An insulating material 14 forming an encapsulant or a primer is interposed between the semiconductor wafer 13 and the package substrate 10 to encapsulate the solder bumps 130.

However, as shown in FIG. 1A', the insulating protective layer 12 of the package substrate 10 is formed with a plurality of openings corresponding to the exposed respective electrical contact pads 110. 120, when the insulating material 14 flows between the semiconductor wafer 13 and the package substrate 10, it is easy to cause a large filler in the insulating material 14 to pass through, thereby creating voids, so that it is easy in subsequent processes. The occurrence of popcorn (Popcorn) results in a decrease in product yield.

Fig. 1B is a schematic cross-sectional view showing a conventional flip chip package structure 1'. As shown in FIGS. 1B and 1B', the process is the same as that shown in FIG. 1A, but the insulating protective layer 12 forms a single opening 120', and the electrical contact pads 110 and a portion of the conductive traces are exposed. 111, the insulating contact layer 12 is not blocked between the electrical contact pads 110, so that larger particles in the insulating material 14 can easily pass between the semiconductor wafer 13 and the package substrate 10 to prevent the insulating material 14 from occurring. The problem of voids.

However, since the bonding force between the copper wiring layer 11 and the insulating material 14 is not good, the insulating material 14 contacts the more bonding circuit layer 11 and contacts the less insulating protective layer 12 in the crystal-crystalline region. The bonding strength of the insulating material 14 is poor, resulting in a problem that delamination is liable to occur.

Therefore, how to overcome the various problems of the above-mentioned prior art has become a difficult problem to be overcome in the industry.

In view of the above-mentioned various deficiencies of the prior art, the present invention provides a package substrate, comprising: a substrate body provided with at least one crystallizing region; a circuit layer formed on the substrate body and formed in the crystallizing region a plurality of electrical contact pads; and an insulating protective layer formed on the substrate body and the circuit layer, and the insulating protective layer has a plurality of openings in the crystallizing region, so that the electrical contact pads are exposed to each The opening, wherein the insulating protective layer is complex A channel is formed between at least two of the openings, such that the channel and the openings through which the openings are formed form a slot on the crystallographic region, such that a portion of the surface of the circuit layer is exposed to the slot.

The present invention provides a method for fabricating a package structure, comprising: bonding at least one electronic component to an electrical contact pad of a crystal region of the package substrate; and filling the insulating material along the trench to form the insulating material The electronic component is between the package substrate.

In the above method, the electronic component is electrically connected to the electrical contact pads by a plurality of conductive components, and the insulating material covers the conductive components.

In the above method, the direction of the groove is the same as the direction in which the insulating material is filled.

In the foregoing method for manufacturing a package structure and a package substrate thereof, the insulation protection layer has a plurality of the grooves. For example, the slotted fabrics are arranged side by side, or the slotted fabrics are staggered.

In the method for manufacturing the package structure and the package substrate thereof, the slot has a guiding channel connecting the edge of the crystal region, so that the insulating material is formed between the electronic component and the package substrate via the guiding channel.

In the method for fabricating the package structure and the package substrate thereof, the area occupied by the insulating protective layer is larger than the area of the circuit layer exposed on the surface of the groove.

In the method for fabricating the package structure and the package substrate thereof, the ratio of the first area of the crystallographic region to the second area of the circuit layer exposed on the surface of the groove is less than 44%.

The method for fabricating the foregoing package structure and the package substrate thereof, the slotted phase The interconnection is made such that the insulating protective layer assumes an island shape.

In the method for manufacturing the package structure and the package substrate thereof, the connection channel is connected to the slot and is interlaced with the slot.

It can be seen that the manufacturing method of the package structure and the package substrate thereof of the present invention mainly replace the conventional opening or opening by slotting, so as to facilitate the filling of the insulating material between the electronic component and the package substrate, and reduce the circuit layer. Because of the exposed area, the present invention can avoid the formation of voids and delamination of the insulating material compared to the prior art, thereby improving product yield.

1,1',9‧‧‧Package structure

10,2‧‧‧Package substrate

11, 21‧‧‧ circuit layer

110,210‧‧‧Electrical contact pads

111,211‧‧‧ conductive traces

12,22,32‧‧‧Insulating protective layer

120,22a‧‧‧Opening

120’‧‧‧ openings

13‧‧‧Semiconductor wafer

130‧‧‧ solder bumps

14,4‧‧‧Insulation

20‧‧‧Substrate body

20a‧‧‧ first surface

20b‧‧‧second surface

220,220’‧‧‧ slotting

220"‧‧‧Connected

22b‧‧‧ channel

22c‧‧‧ Guided Road

3‧‧‧Electronic components

3a‧‧‧Action surface

3b‧‧‧Non-active surface

30‧‧‧Conductive components

D‧‧‧ crystal zone

Y‧‧·Mold flow direction

1A to 1A' are cross-sectional and top views of a conventional flip-chip package structure; FIGS. 1B to 1B' are cross-sectional and top views of another conventional flip chip package structure; BRIEF DESCRIPTION OF THE DRAWINGS FIG. 2A to 2C are top views of different embodiments of the package substrate of FIG. 2; and FIG. 3 is a method for fabricating the package structure of the present invention. The actual state of the flow of the insulating material is shown above.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

It should be noted that the structures, proportions, sizes, etc. shown in the drawings of the present specification are only used in conjunction with the contents disclosed in the specification to familiarize themselves with the art. The understanding and reading of the person is not intended to limit the conditions for the implementation of the present invention, and therefore does not have technical significance. Any modification of the structure, change of the proportional relationship or adjustment of the size may not be affected by the present invention. The efficacies and the achievable objectives should still fall within the scope of the technical content disclosed in the present invention. In the meantime, the terms "upper", "first", "second", "one" and "the" are used in the description, and are not intended to limit the scope of the invention. Changes or adjustments in the relative relationship are considered to be within the scope of the invention without substantial changes.

2 and 2A are schematic views showing the manufacturing method of the package structure 9 of the present invention. In this embodiment, the package structure 9 is a flip chip type.

As shown in FIG. 2, an electronic component 3 is bonded to a package substrate 2, and an insulating material 4 is formed between the electronic component 3 and the package substrate 2. Specifically, the package substrate 2 has a substrate body 20, a circuit layer 21, and an insulating protective layer 22.

The substrate body 20 has a first surface 20a and a second surface 20b opposite thereto, and a crystal region D is defined on the first surface 20a, as shown in FIG. 2A.

The circuit layer 21 is disposed on the first surface 20a of the substrate body 20, and has a plurality of conductive traces 211 and a plurality of electrical contact pads 210 on the crystallized region D, wherein the conductive traces 211 is connected to each of the electrical contact pads 210.

The insulating protective layer 22 is disposed on the first surface 20a of the substrate body 20 and the circuit layer 21, and the insulating protective layer 22 has a plurality of bits. a portion of the surface of the circuit layer 21 (including the conductive traces 211 and the electrical contact pads 210) and a portion of the first surface 20a are exposed to the slots 220, such as the second portion. The figure shows. Specifically, the slot 220 includes a plurality of openings 22a corresponding to the exposed electrical contact pads 210, and a channel 22b formed between at least two of the openings 22a, that is, the channel 22b and the connected channel The openings 22a form the slots 220.

In this embodiment, the material of the substrate body 20 may be a dielectric material or other conventional materials, and is not particularly limited, and the package substrate 2 may have an internal circuit electrically connected to the circuit layer 21 (not shown). The insulating protective layer 22 is a solder resist layer such as green lacquer.

Furthermore, the shapes of the slots 220 are strips (which may be regular or irregular strips), and the layouts are longitudinally and side by side, preferably parallel to each other; in other embodiments, As shown in FIG. 2B, some of the slots 220' may also be laterally disposed such that the slots 220, 220' are arranged in a staggered manner; or, as shown in FIG. 2C, the plurality of channels 220" are connected to each other. The slot 220 is interleaved with the slot 220, but the connecting channels 220" are not aligned with the opening 22a.

Moreover, the area of the insulating layer 22 is larger than the surface of the circuit layer 21 exposed on the surface of the slot 220 (ie, the exposed top surface of the conductive trace 211 and the electrical contact pad 210). The area of the exposed top surface, and the first area of the crystal zone D (such as the dotted rectangular area of FIG. 2A, denoted by the symbol A below) and the second layer of the circuit layer 21 exposed on the surface of the slot 220 The ratio of the area (hereinafter indicated by the symbol B) is less than 44% (ie, B/A <44%), so the insulating protective layer 22 can be opened according to requirements. The number of the slots 220 and the number of the openings 22a are as shown in FIG. 2B, and some of the openings 22a are not in communication with the slots 220.

Therefore, the method of the present invention is to bond the electronic component 3 to the electrical contact pad 210 of the crystallographic region D of the package substrate 2, and then fill the insulating material 4 along the slot 220 to form the insulating material 4. Between the electronic component 3 and the package substrate 2.

In this embodiment, the electronic component 3 is an active component, a passive component or a combination thereof, and the active component is, for example, a wafer, and the passive component is, for example, a resistor, a capacitor, and an inductor. Specifically, the electronic component 3 has an opposite active surface 3a and a non-active surface 3b, and the active surface 3a is combined and electrically connected to the electrical contact pads 210 by a plurality of conductive components 30, wherein the conductive components The 30 series is, for example, a block (such as a bump) containing a solder material.

Furthermore, the range of the crystallographic region D depends on the size of the electronic component 3, and the range of the crystallographic region D is approximately equal to the layout range of the insulating material 4, so that the range of the crystallographic region D is larger than the electron. The area of component 3.

Moreover, the insulating material 4 is a primer or an encapsulant, and the insulating material 4 covers the conductive elements 30.

In addition, the slot 220 has a guiding channel 22c that communicates with the edge of the crystallizing region D. As shown in FIG. 2A, the insulating material 4 flows into the electronic component 3 and the package substrate 2 via the guiding channel 22c. In order to facilitate the filling of the insulating material 4.

In the manufacturing method of the present invention, when the process of filling the insulating material 4 is performed, the guiding channel 22c of the slot 220 corresponds to the filling direction of the insulating material 4, that is, the direction of the slot 220 and the direction of the mold flow Y. (as shown in Figure 3) is the same, The insulating material 4 flows in the mold flow direction Y, and flows along the slit 220 to the other end. In an embodiment, because the slots 220 are connected to each other, the insulating protective layer 32 has an island shape in the crystallizing region D, as shown in FIG. 3, so when the insulating material 4 is larger When the particles touch the insulating protective layer 32 such as an island, the material can be bypassed by the insulating protective layer 32 and continue to flow along the slit 220 without being blocked, so that no void is generated.

Moreover, in the crystallizing region D, most of the conductive traces 211 are covered with the insulating protective layer 22, and only a small portion of the conductive traces 211 do not cover the insulating protective layer 22, so in the crystallizing region D The area occupied by the insulating protective layer 22 is larger than the area exposed by the circuit layer 21 on the surface of the slot 220, so that the insulating material 4 contacts the more insulating protective layer 22 and contacts less of the circuit layer 21. The bonding force of the insulating material 4 can be increased to avoid delamination of the insulating material 4.

In summary, the method for manufacturing the package structure of the present invention and the package substrate thereof are designed to avoid the formation of voids in the insulating material and avoid delamination of the insulating material, thereby improving product yield.

The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

2‧‧‧Package substrate

20a‧‧‧ first surface

21‧‧‧Line layer

210‧‧‧Electrical contact pads

211‧‧‧ conductive traces

22‧‧‧Insulating protective layer

220‧‧‧ slotting

22a‧‧‧Opening

22b‧‧‧ channel

22c‧‧‧ Guided Road

D‧‧‧ crystal zone

Claims (20)

A package substrate includes: a substrate body having at least one crystallizing region; a circuit layer formed on the substrate body; and a plurality of electrical contact pads formed in the crystallizing region; and an insulating protective layer Formed on the substrate body and the circuit layer, and the insulating protective layer has a plurality of openings on the crystallizing region, so that the electrical contact pads are exposed to the openings, wherein the insulating protective layer is repeated At least two channels are formed between the openings, such that the channels and the openings through which the openings are formed form a slot on the crystallographic region, such that a portion of the surface of the circuit layer is exposed to the slot. The package substrate of claim 1, wherein the insulating protective layer has a plurality of the grooves. The package substrate of claim 2, wherein the slotted layouts are arranged side by side. The package substrate of claim 2, wherein the slots are arranged in a staggered manner. The package substrate of claim 1, wherein the slotted portion has a guide track that communicates with an edge of the crystallographic region. The package substrate of claim 1, wherein the area of the insulating layer occupies an area larger than an area of the circuit layer exposed on the surface of the groove. The package substrate of claim 1, wherein the first area of the crystallographic region and the surface of the circuit layer are exposed on the surface of the groove The ratio of the two areas is less than 44%. The package substrate according to claim 1, wherein the slots are connected to each other such that the insulating protective layer has an island shape. The package substrate according to claim 1, further comprising a connecting passage connecting the slot and being staggered with the slot. A method for fabricating a package structure includes: bonding at least one electronic component to an electrical contact pad of a crystallographic region of a package substrate as described in claim 1; and filling the insulating material along the slot An insulating material is formed between the electronic component and the package substrate. The method of fabricating a package structure according to claim 10, wherein the insulating protective layer has a plurality of the grooves. The method for manufacturing a package structure according to claim 11, wherein the slotted layouts are arranged side by side. The method for manufacturing a package structure according to claim 11, wherein the slotted layouts are staggered. The method of manufacturing a package structure according to claim 10, wherein the slotted portion has a guide track connecting the edge of the crystallizing region for filling the insulating material. The method for manufacturing a package structure according to claim 10, wherein, in the range of the crystallographic region, the area occupied by the insulating protective layer is larger than the area of the circuit layer exposed on the surface of the groove. The method for manufacturing a package structure according to claim 10, wherein the first area of the crystallizing region and the circuit layer are exposed to the groove The ratio of the second area of the surface is less than 44%. The method for manufacturing a package structure according to claim 10, wherein the slots are connected to each other such that the insulating protective layer has an island shape. The method of manufacturing a package structure according to claim 10, wherein the package substrate comprises a connecting passage connecting the slot and interlaced with the slot. The method of manufacturing a package structure according to claim 10, wherein the electronic component is electrically connected to the electrical contact pads by a plurality of conductive components, and the insulating material covers the conductive components. The method for manufacturing a package structure according to claim 10, wherein the direction of the groove is the same as the direction in which the insulating material is filled.