TWI569339B - Method of fabricating a package structure and a package substrate thereof - Google Patents
Method of fabricating a package structure and a package substrate thereof Download PDFInfo
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- TWI569339B TWI569339B TW104100212A TW104100212A TWI569339B TW I569339 B TWI569339 B TW I569339B TW 104100212 A TW104100212 A TW 104100212A TW 104100212 A TW104100212 A TW 104100212A TW I569339 B TWI569339 B TW I569339B
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- package substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
- H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Description
本發明係有關一種封裝技術,尤指一種覆晶式封裝結構之製法及其所用之封裝基板。 The invention relates to a packaging technology, in particular to a method for manufacturing a flip chip package structure and a package substrate used therefor.
隨著電子產業的發達,現今的電子產品已趨向輕薄短小與功能多樣化的方向設計,半導體封裝技術亦隨之開發出不同的封裝型態。為滿足半導體裝置之高積集度(Integration)以及微型化(Miniaturization)需求,除傳統打線式(Wire bonding)之半導體封裝技術外,亦可藉由覆晶(Flip chip)方式,以提升佈線密度。 With the development of the electronics industry, today's electronic products have been designed in a light, short, and versatile manner, and semiconductor packaging technologies have also developed different packaging types. In order to meet the high integration and miniaturization requirements of semiconductor devices, in addition to the conventional semiconductor technology of wire bonding, Flip chip can also be used to increase the wiring density. .
第1A圖係為習知覆晶式封裝結構1之剖視示意圖。如第1A圖所示,一半導體晶片13藉由複數銲錫凸塊130結合至一封裝基板10之線路層11之電性接觸墊110上並電性連接該線路層11之導電跡線111,再形成封裝膠體或底膠之絕緣材14於該半導體晶片13與該封裝基板10之間,以包覆該些銲錫凸塊130。 FIG. 1A is a schematic cross-sectional view of a conventional flip chip package structure 1. As shown in FIG. 1A, a semiconductor wafer 13 is bonded to the electrical contact pads 110 of the circuit layer 11 of the package substrate 10 by a plurality of solder bumps 130 and electrically connected to the conductive traces 111 of the circuit layer 11. An insulating material 14 forming an encapsulant or a primer is interposed between the semiconductor wafer 13 and the package substrate 10 to encapsulate the solder bumps 130.
然而,如第1A’圖所示,該封裝基板10之絕緣保護層12係形成有複數對應外露各該電性接觸墊110之開孔 120,故於該絕緣材14流入該半導體晶片13與該封裝基板10間時,容易導致該絕緣材14中較大的顆粒(filler)無法通過而產生空隙(void),以致於後續製程中容易發生爆米花現象(Popcorn),致使產品良率降低。 However, as shown in FIG. 1A', the insulating protective layer 12 of the package substrate 10 is formed with a plurality of openings corresponding to the exposed respective electrical contact pads 110. 120, when the insulating material 14 flows between the semiconductor wafer 13 and the package substrate 10, it is easy to cause a large filler in the insulating material 14 to pass through, thereby creating voids, so that it is easy in subsequent processes. The occurrence of popcorn (Popcorn) results in a decrease in product yield.
第1B圖係為習知覆晶式封裝結構1’之剖視示意圖。如第1B及1B’圖所示,其製程與第1A圖所示之製程相同,但該絕緣保護層12係形成單一開口120’,以外露各該電性接觸墊110與部分該導電跡線111,使各該電性接觸墊110間沒有該絕緣保護層12阻隔,故該絕緣材14中較大的顆粒能輕易通過該半導體晶片13與該封裝基板10間,以避免該絕緣材14發生空隙之問題。 Fig. 1B is a schematic cross-sectional view showing a conventional flip chip package structure 1'. As shown in FIGS. 1B and 1B', the process is the same as that shown in FIG. 1A, but the insulating protective layer 12 forms a single opening 120', and the electrical contact pads 110 and a portion of the conductive traces are exposed. 111, the insulating contact layer 12 is not blocked between the electrical contact pads 110, so that larger particles in the insulating material 14 can easily pass between the semiconductor wafer 13 and the package substrate 10 to prevent the insulating material 14 from occurring. The problem of voids.
惟,由於銅質線路層11與該絕緣材14之間結合力不佳,故於置晶區中,該絕緣材14接觸結合較多的線路層11而接觸較少的絕緣保護層12,因而該絕緣材14的結合力不佳,導致容易發生脫層(delamination)之問題。 However, since the bonding force between the copper wiring layer 11 and the insulating material 14 is not good, the insulating material 14 contacts the more bonding circuit layer 11 and contacts the less insulating protective layer 12 in the crystal-crystalline region. The bonding strength of the insulating material 14 is poor, resulting in a problem that delamination is liable to occur.
因此,如何克服上述習知技術之種種問題,實已成為目前業界亟待克服之難題。 Therefore, how to overcome the various problems of the above-mentioned prior art has become a difficult problem to be overcome in the industry.
鑑於上述習知技術之種種缺失,本發明提供一種封裝基板,係包括:基板本體,係設有至少一置晶區;線路層,係形成於該基板本體上,且於該置晶區形成有複數電性接觸墊;以及絕緣保護層,係形成於該基板本體與該線路層上,且該絕緣保護層具有複數位於該置晶區上之開孔,令各該電性接觸墊外露於各該開孔,其中,該絕緣保護層復 於至少二該開孔之間形成有一通道,使該通道及其所連通之該些開孔形成一位於該置晶區上之開槽,令該線路層之部分表面外露於該開槽。 In view of the above-mentioned various deficiencies of the prior art, the present invention provides a package substrate, comprising: a substrate body provided with at least one crystallizing region; a circuit layer formed on the substrate body and formed in the crystallizing region a plurality of electrical contact pads; and an insulating protective layer formed on the substrate body and the circuit layer, and the insulating protective layer has a plurality of openings in the crystallizing region, so that the electrical contact pads are exposed to each The opening, wherein the insulating protective layer is complex A channel is formed between at least two of the openings, such that the channel and the openings through which the openings are formed form a slot on the crystallographic region, such that a portion of the surface of the circuit layer is exposed to the slot.
本發明復提供一種封裝結構之製法,係包括:將至少一電子元件結合至前述之封裝基板之置晶區之電性接觸墊上;以及沿該開槽填入絕緣材,使該絕緣材形成於該電子元件與該封裝基板之間。 The present invention provides a method for fabricating a package structure, comprising: bonding at least one electronic component to an electrical contact pad of a crystal region of the package substrate; and filling the insulating material along the trench to form the insulating material The electronic component is between the package substrate.
前述之製法中,該電子元件係藉由複數導電元件電性連接該些電性接觸墊,且該絕緣材係包覆該些導電元件。 In the above method, the electronic component is electrically connected to the electrical contact pads by a plurality of conductive components, and the insulating material covers the conductive components.
前述之製法中,該開槽之方向與該絕緣材之填入方向相同。 In the above method, the direction of the groove is the same as the direction in which the insulating material is filled.
前述之封裝結構之製法及其封裝基板中,該絕緣保護層具有複數條該開槽。例如,該些開槽之佈設係並排設置、或者該些開槽之佈設係交錯設置。 In the foregoing method for manufacturing a package structure and a package substrate thereof, the insulation protection layer has a plurality of the grooves. For example, the slotted fabrics are arranged side by side, or the slotted fabrics are staggered.
前述之封裝結構之製法及其封裝基板中,該開槽復具有連通該置晶區邊緣之導引道,使該絕緣材經由該導引道形成於該電子元件與該封裝基板之間。 In the method for manufacturing the package structure and the package substrate thereof, the slot has a guiding channel connecting the edge of the crystal region, so that the insulating material is formed between the electronic component and the package substrate via the guiding channel.
前述之封裝結構之製法及其封裝基板中,該置晶區之範圍內,該絕緣保護層所佔之面積大於該線路層外露於該開槽之表面之面積。 In the method for fabricating the package structure and the package substrate thereof, the area occupied by the insulating protective layer is larger than the area of the circuit layer exposed on the surface of the groove.
前述之封裝結構之製法及其封裝基板中,該置晶區之第一面積與該線路層外露於該開槽之表面之第二面積的比值係小於44%。 In the method for fabricating the package structure and the package substrate thereof, the ratio of the first area of the crystallographic region to the second area of the circuit layer exposed on the surface of the groove is less than 44%.
前述之封裝結構之製法及其封裝基板中,該些開槽相 互連通,使該絕緣保護層呈現島狀。 The method for fabricating the foregoing package structure and the package substrate thereof, the slotted phase The interconnection is made such that the insulating protective layer assumes an island shape.
前述之封裝結構之製法及其封裝基板中,復包括連通道,係連通該開槽並與該開槽交錯設置。 In the method for manufacturing the package structure and the package substrate thereof, the connection channel is connected to the slot and is interlaced with the slot.
由上可知,本發明之封裝結構之製法及其封裝基板,主要藉由開槽取代習知開孔或開口,以利於絕緣材填入該電子元件與該封裝基板之間,且減少該線路層之外露面積,故相較於習知技術,本發明可避免該絕緣材形成空隙及發生脫層,因而能提高產品良率。 It can be seen that the manufacturing method of the package structure and the package substrate thereof of the present invention mainly replace the conventional opening or opening by slotting, so as to facilitate the filling of the insulating material between the electronic component and the package substrate, and reduce the circuit layer. Because of the exposed area, the present invention can avoid the formation of voids and delamination of the insulating material compared to the prior art, thereby improving product yield.
1,1’,9‧‧‧封裝結構 1,1',9‧‧‧Package structure
10,2‧‧‧封裝基板 10,2‧‧‧Package substrate
11,21‧‧‧線路層 11, 21‧‧‧ circuit layer
110,210‧‧‧電性接觸墊 110,210‧‧‧Electrical contact pads
111,211‧‧‧導電跡線 111,211‧‧‧ conductive traces
12,22,32‧‧‧絕緣保護層 12,22,32‧‧‧Insulating protective layer
120,22a‧‧‧開孔 120,22a‧‧‧Opening
120’‧‧‧開口 120’‧‧‧ openings
13‧‧‧半導體晶片 13‧‧‧Semiconductor wafer
130‧‧‧銲錫凸塊 130‧‧‧ solder bumps
14,4‧‧‧絕緣材 14,4‧‧‧Insulation
20‧‧‧基板本體 20‧‧‧Substrate body
20a‧‧‧第一表面 20a‧‧‧ first surface
20b‧‧‧第二表面 20b‧‧‧second surface
220,220’‧‧‧開槽 220,220’‧‧‧ slotting
220”‧‧‧連通道 220"‧‧‧Connected
22b‧‧‧通道 22b‧‧‧ channel
22c‧‧‧導引道 22c‧‧‧ Guided Road
3‧‧‧電子元件 3‧‧‧Electronic components
3a‧‧‧作用面 3a‧‧‧Action surface
3b‧‧‧非作用面 3b‧‧‧Non-active surface
30‧‧‧導電元件 30‧‧‧Conductive components
D‧‧‧置晶區 D‧‧‧ crystal zone
Y‧‧‧模流方向 Y‧‧·Mold flow direction
第1A至1A’圖係為習知覆晶式封裝結構的剖視與上視示意圖;第1B至1B’圖係為另一習知覆晶式封裝結構之剖視與上視示意圖;第2圖係為本發明封裝結構之製法之剖視示意圖;第2A至2C圖係為第2圖之封裝基板之不同實施例之上視示意圖;以及第3圖係為本發明之封裝結構之製法之絕緣材流動之實際狀態之上視示意圖。 1A to 1A' are cross-sectional and top views of a conventional flip-chip package structure; FIGS. 1B to 1B' are cross-sectional and top views of another conventional flip chip package structure; BRIEF DESCRIPTION OF THE DRAWINGS FIG. 2A to 2C are top views of different embodiments of the package substrate of FIG. 2; and FIG. 3 is a method for fabricating the package structure of the present invention. The actual state of the flow of the insulating material is shown above.
以下藉由特定的具體實施例說明本發明之實施方式,熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。 The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.
須知,本說明書所附圖式所繪示之結構、比例、大小等,均僅用以配合說明書所揭示之內容,以供熟悉此技藝 之人士之瞭解與閱讀,並非用以限定本發明可實施之限定條件,故不具技術上之實質意義,任何結構之修飾、比例關係之改變或大小之調整,在不影響本發明所能產生之功效及所能達成之目的下,均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時,本說明書中所引用之如“上”、“第一”、“第二”、及“一”等之用語,亦僅為便於敘述之明瞭,而非用以限定本發明可實施之範圍,其相對關係之改變或調整,在無實質變更技術內容下,當亦視為本發明可實施之範疇。 It should be noted that the structures, proportions, sizes, etc. shown in the drawings of the present specification are only used in conjunction with the contents disclosed in the specification to familiarize themselves with the art. The understanding and reading of the person is not intended to limit the conditions for the implementation of the present invention, and therefore does not have technical significance. Any modification of the structure, change of the proportional relationship or adjustment of the size may not be affected by the present invention. The efficacies and the achievable objectives should still fall within the scope of the technical content disclosed in the present invention. In the meantime, the terms "upper", "first", "second", "one" and "the" are used in the description, and are not intended to limit the scope of the invention. Changes or adjustments in the relative relationship are considered to be within the scope of the invention without substantial changes.
第2及2A圖係為本發明之封裝結構9之製法之示意圖。於本實施例中,該封裝結構9係為覆晶式。 2 and 2A are schematic views showing the manufacturing method of the package structure 9 of the present invention. In this embodiment, the package structure 9 is a flip chip type.
如第2圖所示,將一電子元件3結合至一封裝基板2上,再形成絕緣材4於該電子元件3與該封裝基板2之間。具體地,所述之封裝基板2具有一基板本體20、一線路層21、以及一絕緣保護層22。 As shown in FIG. 2, an electronic component 3 is bonded to a package substrate 2, and an insulating material 4 is formed between the electronic component 3 and the package substrate 2. Specifically, the package substrate 2 has a substrate body 20, a circuit layer 21, and an insulating protective layer 22.
所述之基板本體20具有相對之第一表面20a與第二表面20b,且於該第一表面20a上定義有一置晶區D,如第2A圖所示。 The substrate body 20 has a first surface 20a and a second surface 20b opposite thereto, and a crystal region D is defined on the first surface 20a, as shown in FIG. 2A.
所述之線路層21係設於該基板本體20之第一表面20a上,且具有複數導電跡線211與位於該置晶區D上之複數電性接觸墊210,其中,該些導電跡線211係連接各該電性接觸墊210。 The circuit layer 21 is disposed on the first surface 20a of the substrate body 20, and has a plurality of conductive traces 211 and a plurality of electrical contact pads 210 on the crystallized region D, wherein the conductive traces 211 is connected to each of the electrical contact pads 210.
所述之絕緣保護層22係設於該基板本體20之第一表面20a與該線路層21上,且該絕緣保護層22具有複數位 於該置晶區D上之開槽220,令該線路層21之部分表面(含導電跡線211與電性接觸墊210)與部分第一表面20a外露於該些開槽220,如第2A圖所示。具體地,該開槽220係包含對應外露各該電性接觸墊210之複數開孔22a、及形成於至少任二該開孔22a之間之一通道22b,亦即該通道22b及其所連通之該些開孔22a形成該開槽220。 The insulating protective layer 22 is disposed on the first surface 20a of the substrate body 20 and the circuit layer 21, and the insulating protective layer 22 has a plurality of bits. a portion of the surface of the circuit layer 21 (including the conductive traces 211 and the electrical contact pads 210) and a portion of the first surface 20a are exposed to the slots 220, such as the second portion. The figure shows. Specifically, the slot 220 includes a plurality of openings 22a corresponding to the exposed electrical contact pads 210, and a channel 22b formed between at least two of the openings 22a, that is, the channel 22b and the connected channel The openings 22a form the slots 220.
於本實施例中,該基板本體20之材質可為介電材或其它習知材質,並無特別限制,且該封裝基板2可具有電性連接該線路層21之內部線路(圖略),而該絕緣保護層22係為防銲層,如綠漆。 In this embodiment, the material of the substrate body 20 may be a dielectric material or other conventional materials, and is not particularly limited, and the package substrate 2 may have an internal circuit electrically connected to the circuit layer 21 (not shown). The insulating protective layer 22 is a solder resist layer such as green lacquer.
再者,該些開槽220之形狀係為條狀(可為規則或不規則條狀),且其佈設係呈現縱向且並排設置,較佳者為相互平行;於其它實施例中,如第2B圖所示,部分該些開槽220’亦可呈現橫向,使該些開槽220,220’之佈設係為交錯設置;或者,如第2C圖所示,復包括複數連通道220”,其連通該開槽220並與該開槽220交錯設置,但該些連通道220”不對齊該開孔22a之位置。 Furthermore, the shapes of the slots 220 are strips (which may be regular or irregular strips), and the layouts are longitudinally and side by side, preferably parallel to each other; in other embodiments, As shown in FIG. 2B, some of the slots 220' may also be laterally disposed such that the slots 220, 220' are arranged in a staggered manner; or, as shown in FIG. 2C, the plurality of channels 220" are connected to each other. The slot 220 is interleaved with the slot 220, but the connecting channels 220" are not aligned with the opening 22a.
又,該置晶區D之範圍內,該絕緣保護層22所佔之面積大於該線路層21外露於該開槽220之表面(即該導電跡線211之外露頂面與電性接觸墊210之外露頂面)之面積,且該置晶區D之第一面積(如第2A圖之虛線矩形面積,以下以符號A表示)與該線路層21外露於該開槽220之表面之第二面積(以下以符號B表示)的比值係小於44%(即B/A<44%),故該絕緣保護層22可依需求設定開 槽220之數量與開孔22a之數量,如第2B圖所示,部分該開孔22a並未與該開槽220相通。 Moreover, the area of the insulating layer 22 is larger than the surface of the circuit layer 21 exposed on the surface of the slot 220 (ie, the exposed top surface of the conductive trace 211 and the electrical contact pad 210). The area of the exposed top surface, and the first area of the crystal zone D (such as the dotted rectangular area of FIG. 2A, denoted by the symbol A below) and the second layer of the circuit layer 21 exposed on the surface of the slot 220 The ratio of the area (hereinafter indicated by the symbol B) is less than 44% (ie, B/A <44%), so the insulating protective layer 22 can be opened according to requirements. The number of the slots 220 and the number of the openings 22a are as shown in FIG. 2B, and some of the openings 22a are not in communication with the slots 220.
因此,本發明之製法係將該電子元件3結合至該封裝基板2之置晶區D之電性接觸墊210上,再沿該開槽220填入該絕緣材4,使該絕緣材4形成於該電子元件3與該封裝基板2之間。 Therefore, the method of the present invention is to bond the electronic component 3 to the electrical contact pad 210 of the crystallographic region D of the package substrate 2, and then fill the insulating material 4 along the slot 220 to form the insulating material 4. Between the electronic component 3 and the package substrate 2.
於本實施例中,該電子元件3係為主動元件、被動元件或其組合者,且該主動元件係例如晶片,而該被動元件係例如電阻、電容及電感。具體地,該電子元件3具有相對之作用面3a與非作用面3b,且該作用面3a藉由複數導電元件30結合並電性連接至該些電性接觸墊210,其中,該些導電元件30係為例如含有銲錫材料之塊體(如凸塊)。 In this embodiment, the electronic component 3 is an active component, a passive component or a combination thereof, and the active component is, for example, a wafer, and the passive component is, for example, a resistor, a capacitor, and an inductor. Specifically, the electronic component 3 has an opposite active surface 3a and a non-active surface 3b, and the active surface 3a is combined and electrically connected to the electrical contact pads 210 by a plurality of conductive components 30, wherein the conductive components The 30 series is, for example, a block (such as a bump) containing a solder material.
再者,該置晶區D之範圍係依據該電子元件3之尺寸而定,且該置晶區D之範圍約等於該絕緣材4之佈設範圍,使該置晶區D之範圍大於該電子元件3之面積。 Furthermore, the range of the crystallographic region D depends on the size of the electronic component 3, and the range of the crystallographic region D is approximately equal to the layout range of the insulating material 4, so that the range of the crystallographic region D is larger than the electron. The area of component 3.
又,該絕緣材4係為底膠或封裝膠體,且該絕緣材4係包覆該些導電元件30。 Moreover, the insulating material 4 is a primer or an encapsulant, and the insulating material 4 covers the conductive elements 30.
另外,該開槽220復具有連通該置晶區D邊緣之導引道22c,如第2A圖所示,使該絕緣材4經由該導引道22c流入該電子元件3與該封裝基板2之間,以利於該絕緣材4填入。 In addition, the slot 220 has a guiding channel 22c that communicates with the edge of the crystallizing region D. As shown in FIG. 2A, the insulating material 4 flows into the electronic component 3 and the package substrate 2 via the guiding channel 22c. In order to facilitate the filling of the insulating material 4.
本發明之製法中,於進行填入該絕緣材4之製程時,將該開槽220之導引道22c對應該絕緣材4之填入方向,即該開槽220之方向與模流方向Y(如第3圖所示)相同, 使該絕緣材4依模流方向Y流入,並沿著該開槽220向另一端流動。於一實施例中,由於該些開槽220相互連通之設計,使該絕緣保護層32於該置晶區D中呈現島狀,如第3圖所示,故當該絕緣材4中較大的顆粒碰觸到如島狀之絕緣保護層32時,可從該絕緣保護層32旁邊繞過並沿著該開槽220繼續流動,而不會受到阻擋,因而不會產生空隙。 In the manufacturing method of the present invention, when the process of filling the insulating material 4 is performed, the guiding channel 22c of the slot 220 corresponds to the filling direction of the insulating material 4, that is, the direction of the slot 220 and the direction of the mold flow Y. (as shown in Figure 3) is the same, The insulating material 4 flows in the mold flow direction Y, and flows along the slit 220 to the other end. In an embodiment, because the slots 220 are connected to each other, the insulating protective layer 32 has an island shape in the crystallizing region D, as shown in FIG. 3, so when the insulating material 4 is larger When the particles touch the insulating protective layer 32 such as an island, the material can be bypassed by the insulating protective layer 32 and continue to flow along the slit 220 without being blocked, so that no void is generated.
再者,於該置晶區D中,大部分之導電跡線211上覆蓋有該絕緣保護層22,僅少部分之導電跡線211未覆蓋該絕緣保護層22,故於該置晶區D中,該絕緣保護層22所佔之面積大於該線路層21外露於該開槽220之表面之面積,使該絕緣材4接觸結合較多的絕緣保護層22而接觸較少的線路層21,因而能增加該絕緣材4的結合力,以避免該絕緣材4發生脫層。 Moreover, in the crystallizing region D, most of the conductive traces 211 are covered with the insulating protective layer 22, and only a small portion of the conductive traces 211 do not cover the insulating protective layer 22, so in the crystallizing region D The area occupied by the insulating protective layer 22 is larger than the area exposed by the circuit layer 21 on the surface of the slot 220, so that the insulating material 4 contacts the more insulating protective layer 22 and contacts less of the circuit layer 21. The bonding force of the insulating material 4 can be increased to avoid delamination of the insulating material 4.
綜上所述,本發明之封裝結構之製法及其封裝基板,藉由該開槽之設計,以避免該絕緣材形成空隙,且避免該絕緣材發生脫層,故能提高產品良率。 In summary, the method for manufacturing the package structure of the present invention and the package substrate thereof are designed to avoid the formation of voids in the insulating material and avoid delamination of the insulating material, thereby improving product yield.
上述實施例係用以例示性說明本發明之原理及其功效,而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對上述實施例進行修改。因此本發明之權利保護範圍,應如後述之申請專利範圍所列。 The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.
2‧‧‧封裝基板 2‧‧‧Package substrate
20a‧‧‧第一表面 20a‧‧‧ first surface
21‧‧‧線路層 21‧‧‧Line layer
210‧‧‧電性接觸墊 210‧‧‧Electrical contact pads
211‧‧‧導電跡線 211‧‧‧ conductive traces
22‧‧‧絕緣保護層 22‧‧‧Insulating protective layer
220‧‧‧開槽 220‧‧‧ slotting
22a‧‧‧開孔 22a‧‧‧Opening
22b‧‧‧通道 22b‧‧‧ channel
22c‧‧‧導引道 22c‧‧‧ Guided Road
D‧‧‧置晶區 D‧‧‧ crystal zone
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TW200845346A (en) * | 2007-05-10 | 2008-11-16 | Siliconware Precision Industries Co Ltd | Flip-chip semiconductor package structure and package substrate applicable thereto |
TW201405718A (en) * | 2012-07-19 | 2014-02-01 | 矽品精密工業股份有限公司 | Substrate structure and die package integrating the substrate structure |
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TW200845346A (en) * | 2007-05-10 | 2008-11-16 | Siliconware Precision Industries Co Ltd | Flip-chip semiconductor package structure and package substrate applicable thereto |
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