JP6237969B1 - 中空封止デバイス及びその製造方法 - Google Patents
中空封止デバイス及びその製造方法 Download PDFInfo
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- JP6237969B1 JP6237969B1 JP2017536598A JP2017536598A JP6237969B1 JP 6237969 B1 JP6237969 B1 JP 6237969B1 JP 2017536598 A JP2017536598 A JP 2017536598A JP 2017536598 A JP2017536598 A JP 2017536598A JP 6237969 B1 JP6237969 B1 JP 6237969B1
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- bump
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- 238000007789 sealing Methods 0.000 title claims abstract description 119
- 238000004519 manufacturing process Methods 0.000 title claims description 17
- 239000000758 substrate Substances 0.000 claims abstract description 100
- 229910052751 metal Inorganic materials 0.000 claims abstract description 59
- 239000002184 metal Substances 0.000 claims abstract description 59
- 238000000059 patterning Methods 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims description 15
- 238000005304 joining Methods 0.000 claims description 12
- 239000002923 metal particle Substances 0.000 claims description 7
- 230000004048 modification Effects 0.000 description 14
- 238000012986 modification Methods 0.000 description 14
- 239000000463 material Substances 0.000 description 5
- 239000002245 particle Substances 0.000 description 5
- 229910052737 gold Inorganic materials 0.000 description 3
- 229910052763 palladium Inorganic materials 0.000 description 3
- 229910052697 platinum Inorganic materials 0.000 description 3
- 230000000052 comparative effect Effects 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- 239000012141 concentrate Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 238000003801 milling Methods 0.000 description 1
- 229910000510 noble metal Inorganic materials 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000009257 reactivity Effects 0.000 description 1
- 239000003566 sealing material Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000010301 surface-oxidation reaction Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
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- H—ELECTRICITY
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
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- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B2207/00—Microstructural systems or auxiliary parts thereof
- B81B2207/07—Interconnects
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B2207/00—Microstructural systems or auxiliary parts thereof
- B81B2207/09—Packages
- B81B2207/091—Arrangements for connecting external electrical signals to mechanical structures inside the package
- B81B2207/092—Buried interconnects in the substrate or in the lid
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B2207/00—Microstructural systems or auxiliary parts thereof
- B81B2207/09—Packages
- B81B2207/091—Arrangements for connecting external electrical signals to mechanical structures inside the package
- B81B2207/094—Feed-through, via
- B81B2207/095—Feed-through, via through the lid
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00261—Processes for packaging MEMS devices
- B81C1/00269—Bonding of solid lids or wafers to the substrate
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C2203/00—Forming microstructural systems
- B81C2203/01—Packaging MEMS
- B81C2203/0109—Bonding an individual cap on the substrate
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C2203/00—Forming microstructural systems
- B81C2203/01—Packaging MEMS
- B81C2203/0118—Bonding a wafer on the substrate, i.e. where the cap consists of another wafer
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C2203/00—Forming microstructural systems
- B81C2203/01—Packaging MEMS
- B81C2203/0172—Seals
- B81C2203/019—Seals characterised by the material or arrangement of seals between parts
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C2203/00—Forming microstructural systems
- B81C2203/03—Bonding two components
- B81C2203/033—Thermal bonding
- B81C2203/037—Thermal bonding techniques not provided for in B81C2203/035 - B81C2203/036
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C2203/00—Forming microstructural systems
- B81C2203/05—Aligning components to be assembled
- B81C2203/051—Active alignment, e.g. using internal or external actuators, magnets, sensors, marks or marks detectors
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- H01L2224/0556—Disposition
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Abstract
Description
図1は、本発明の実施の形態1に係る中空封止デバイスの製造方法を示す平面図である。図2から図4は、本発明の実施の形態1に係る中空封止デバイスの製造方法を示す断面図である。図2は図1のI−IIに沿った断面図である。
図17は、本発明の実施の形態2に係る中空封止デバイスを示す断面図である。実施の形態1とは異なり、バンプ4に接合される凸部9を設けない。従って、封止枠3に接合される凸部8に更に高い荷重をかけることができるため、更に封止性を向上させることができる。また、実施の形態1の凸部9はビア6を避けてレイアウトする必要があるが、本実施の形態ではそのようなレイアウトの考慮は不要となる。この結果、レイアウトの自由度を上げることができ、レイアウト面積の増大を抑制することができる。
図19は、本発明の実施の形態3に係る中空封止デバイスを示す断面図である。本実施の形態では凸部8,9を基板1側に形成している。この場合でも実施の形態1と同様に、凸部8,9の部分に選択的に高圧をかけることができるため、封止性を向上させることができる。また、実施の形態1と同様に、メタルペーストパターンの押し込み量に対して圧力が決まる。
Claims (9)
- 第1の基板の主面にリング状の封止枠とバンプをメタルペーストのパターニングにより同時に形成する工程と、
第2の基板の主面に前記封止枠の幅より狭い幅を持つリング状の凸部を形成する工程と、
前記第1の基板の前記主面と前記第2の基板の前記主面を対向させてアライメントして、前記封止枠と前記凸部を接合しつつ、前記バンプを前記第2の基板に電気接合する工程とを備え、
前記凸部の高さは、接合後の前記第1の基板と前記第2の基板との間隔の0.4〜0.7倍であり、
接合後の前記封止枠は、少なくとも前記凸部の直下において、メタル粒子間の空隙が孤立した状態であるか又は完全にバルク化していることを特徴とする中空封止デバイスの製造方法。 - 前記凸部を覆う第1の金属膜と、前記第2の基板のビアに電気的に接続された第2の金属膜とを前記第2の基板の前記主面に形成する工程を更に備え、
前記第1の金属膜を介して前記凸部を前記封止枠に接合させ、前記第2の金属膜を介して前記バンプを前記ビアに電気接合させることを特徴とする請求項1に記載の中空封止デバイスの製造方法。 - 第1の基板の主面にリング状の封止枠とバンプをメタルペーストのパターニングにより同時に形成する工程と、
第2の基板の主面に、前記封止枠の幅より狭い幅を持つリング状の第1の凸部と、前記バンプの幅より狭い幅を持つ第2の凸部とを形成する工程と、
前記第1の基板の前記主面と前記第2の基板の前記主面を対向させてアライメントして、前記封止枠と前記第1の凸部を接合し、前記バンプと前記第2の凸部を接合しつつ、前記バンプを前記第2の基板に電気接合する工程とを備え、
前記第1の凸部の高さは、接合後の前記第1の基板と前記第2の基板との間隔の0.4〜0.7倍であり、
接合後の前記封止枠は、少なくとも前記第1の凸部の直下において、メタル粒子間の空隙が孤立した状態であるか又は完全にバルク化していることを特徴とする中空封止デバイスの製造方法。 - 前記第2の凸部が前記バンプに完全に埋まりこんでいることを特徴とする請求項3に記載の中空封止デバイスの製造方法。
- 前記第1の凸部を覆う第1の金属膜と、前記第2の凸部を覆う第2の金属膜とを前記第2の基板の前記主面に形成する工程を更に備え、
前記第1の金属膜を介して前記第1の凸部を前記封止枠に接合させ、前記第2の金属膜を介して前記第2の凸部を前記バンプに接合させることを特徴とする請求項3又は4に記載の中空封止デバイスの製造方法。 - 前記第2の金属膜は前記第2の基板のビアに電気的に接続されていることを特徴とする請求項5に記載の中空封止デバイスの製造方法。
- 前記第1の基板の主面に金属膜を形成する工程を更に備え、
前記金属膜の上に前記封止枠と前記バンプを形成することを特徴とする請求項1〜6の何れか1項に記載の中空封止デバイスの製造方法。 - 第1の基板と、
前記第1の基板の主面に形成されたリング状の封止枠と、
前記第1の基板の前記主面に形成されたバンプと、
前記第1の基板の前記主面に対向する主面を持つ第2の基板と、
前記第2の基板の前記主面に形成され、前記封止枠の幅より狭い幅を持つリング状の凸部とを備え、
前記封止枠と前記凸部が接合し、
前記バンプが前記第2の基板に電気接合し、
前記凸部の高さは、前記第1の基板と前記第2の基板との間隔の0.4〜0.7倍であり、
前記封止枠と前記バンプはメタルペーストで形成され、
前記封止枠は、少なくとも前記凸部の直下において、メタル粒子間の空隙が孤立した状態であるか又は完全にバルク化していることを特徴とする中空封止デバイス。 - 第1の基板と、
前記第1の基板の主面に形成されたリング状の封止枠と、
前記第1の基板の前記主面に形成されたバンプと、
前記第1の基板の前記主面に対向する主面を持つ第2の基板と、
前記第2の基板の前記主面に形成され、前記封止枠の幅より狭い幅を持つリング状の第1の凸部と、
第2の基板の前記主面に形成され、前記バンプの幅より狭い幅を持つ第2の凸部とを備え、
前記封止枠と前記第1の凸部が接合し、
前記バンプと前記第2の凸部が接合し、
前記バンプが前記第2の基板に電気接合し、
前記第1の凸部の高さは、前記第1の基板と前記第2の基板との間隔の0.4〜0.7倍であり、
前記封止枠と前記バンプはメタルペーストで形成され、
前記封止枠は、少なくとも前記第1の凸部の直下において、メタル粒子間の空隙が孤立した状態であるか又は完全にバルク化していることを特徴とする中空封止デバイス。
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- 2017-03-29 DE DE112017007356.1T patent/DE112017007356T5/de not_active Withdrawn
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Also Published As
Publication number | Publication date |
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US10950567B2 (en) | 2021-03-16 |
TW201843748A (zh) | 2018-12-16 |
TWI666710B (zh) | 2019-07-21 |
US20200144210A1 (en) | 2020-05-07 |
DE112017007356T5 (de) | 2019-12-12 |
JPWO2018179153A1 (ja) | 2019-04-11 |
KR102336096B1 (ko) | 2021-12-06 |
WO2018179153A1 (ja) | 2018-10-04 |
CN110494963B (zh) | 2023-06-13 |
KR20190118634A (ko) | 2019-10-18 |
CN110494963A (zh) | 2019-11-22 |
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