CN110494963A - 中空封装器件及其制造方法 - Google Patents

中空封装器件及其制造方法 Download PDF

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Publication number
CN110494963A
CN110494963A CN201780088937.0A CN201780088937A CN110494963A CN 110494963 A CN110494963 A CN 110494963A CN 201780088937 A CN201780088937 A CN 201780088937A CN 110494963 A CN110494963 A CN 110494963A
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substrate
protrusion
interarea
convex block
package frame
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CN201780088937.0A
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CN110494963B (zh
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西泽弘一郎
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Mitsubishi Corp
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Mitsubishi Corp
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Abstract

通过金属膏的图案化在第1基板(1)的主面同时形成凸块(4)和环状的封装框(3)。在第2基板(5)的主面形成具有比封装框(3)的宽度窄的宽度的环状的凸部(8)。使基板(1)的主面和第2基板(5)的主面相对而进行对准，将封装框(3)和凸部(8)接合，并且将凸块(4)与第2基板(5)电接合。凸部(8)的高度是接合后的基板(1)和第2基板(5)的间隔的0.4～0.7倍。

Description

中空封装器件及其制造方法
技术领域
本发明涉及在2张基板间具有中空的中空封装器件及其制造方法。
背景技术
存在如下安装方法，即，为了提高可靠性和特性，在相对的基板间形成中空部而对半导体器件或者MEMS(Micro Electric Mechanical Systems)器件进行中空封装(例如，参照专利文献1、2)。就以往的器件而言，通过封装框对2个基板进行接合而形成气密中空部，从下侧的基板的电路向上侧的基板侧引出电极(例如，参照专利文献1)。在通过晶片工艺制作该构造的情况下，通过金属膏的图案化同时形成凸块和封装框，集中进行接合。该方法能够通过晶片级芯片规模封装(WLCSP)集中制作大量的器件，因此，生产效率高，近年来使用越发广泛。
但是，金属膏的图案化的精度差，难以精细地对图案的宽度进行控制。因此，接合图案的面积会变大，接合时的压力(将总负载除以图案面积而得到的值)不足，因此，存在封装性不够的问题。例如，在通过Au金属膏进行气密封装的情况下，作为接合时的压力需要大于或等于100MPa。在以4英寸晶片同时封装出5000个芯片的情况下，如果将封装框的宽度设为20μm，则封装框的图案面积大约是10％。如果以该条件进行计算，则为了确保接合压力100MPa，需要每个晶片78.5kN的负载。但是，在已有的加压装置中60kN左右是极限，因此，不能得到气密封装性。作为该问题的解决对策，存在在与封装框接合的部分设置环状的凸部而使压力集中的方法(例如，参照专利文献1)。
专利文献1：日本特开2014－22699号公报
专利文献2：日本特开2003－188294号公报
专利文献3：日本特开2016－197664号公报
发明内容
但是，如果将在与封装框接合的部分设置凸部的方法应用于使用了凸块的情况，则存在向凸块的负载分散，因此，气密性变差的问题。例如，如果从4英寸晶片以相同尺寸制作5000个芯片，在各芯片需要6个φ100μm的凸块，则凸块的图案面积大约为12％。如果以该条件进行计算，则即使在与封装框接合的部分设置了凸部，为了以100MPa进行加压，仅就凸块图案而言就需要94.2kN的负载。因此，依靠最大60kN的已有的加压装置，不能得到气密封装性。
本发明是为了解决上述课题而提出的，其目的在于得到能够通过凸块将基板间电连接并且使封装性提高的中空封装器件以及其制造方法。
本发明涉及的中空封装器件的制造方法的特征在于，具备以下工序：通过金属膏的图案化在第1基板的主面同时形成凸块和环状的封装框；在第2基板的主面形成具有比所述封装框的宽度窄的宽度的环状的凸部；以及使所述第1基板的所述主面和所述第2基板的所述主面相对而进行对准，将所述封装框和所述凸部接合，并且将所述凸块与所述第2基板电接合，所述凸部的高度是接合后的所述第1基板和所述第2基板的间隔的0.4～0.7倍。
发明的效果
在本发明中，能够通过凸块将基板间电连接。在接合时能够不对封装框的整个图案面积施加高压，而是对凸部的部分选择性地施加高压，因此能够施加高负载。凸部的高度是接合后的第1基板和第2基板的间隔的0.4～0.7倍。由此，在凸部的正下方，封装框的金属膏能够金属块化而使封装性提高。
附图说明
图1是表示本发明的实施方式1涉及的中空封装器件的制造方法的俯视图。
图2是表示本发明的实施方式1涉及的中空封装器件的制造方法的剖面图。
图3是表示本发明的实施方式1涉及的中空封装器件的制造方法的剖面图。
图4是表示本发明的实施方式1涉及的中空封装器件的制造方法的剖面图。
图5是表示对金属膏图案进行了加压变形时的状态变化的剖面图。
图6是将接合前后的凸块部分放大后的剖面图。
图7是表示Au膏的与加压相对的变形量的关系的图。
图8是表示本发明的实施方式1涉及的中空封装器件的变形例1的剖面图。
图9是沿图8的Ⅰ－Ⅱ的剖面图。
图10是表示本发明的实施方式1涉及的中空封装器件的变形例2的剖面图。
图11是表示本发明的实施方式1涉及的中空封装器件的封装框侧的凸部的变形例的俯视图。
图12是表示本发明的实施方式1涉及的中空封装器件的封装框侧的凸部的变形例的俯视图。
图13是表示本发明的实施方式1涉及的中空封装器件的封装框侧的凸部的变形例的俯视图。
图14是表示本发明的实施方式1涉及的中空封装器件的变形例3的剖面图。
图15是表示本发明的实施方式1涉及的中空封装器件的变形例4的剖面图。
图16是表示对比例涉及的中空封装器件的剖面图。
图17是表示本发明的实施方式2涉及的中空封装器件的剖面图。
图18是表示本发明的实施方式2涉及的中空封装器件的变形例的剖面图。
图19是表示本发明的实施方式3涉及的中空封装器件的剖面图。
具体实施方式
参照附图说明本发明的实施方式涉及的中空封装器件以及其制造方法。针对相同或者对应的结构要素标注相同的标号，有时省略重复的说明。
实施方式1
图1是表示本发明的实施方式1涉及的中空封装器件的制造方法的俯视图。图2至图4是表示本发明的实施方式1涉及的中空封装器件的制造方法的剖面图。图2是沿图1的Ⅰ－Ⅱ的剖面图。
首先，如图1以及图2所示，在基板1的上表面的中央部形成应中空封装的器件电路2。通过金属膏的图案化在基板1的上表面同时形成凸块4和环状的封装框3。封装框3和凸块4的厚度彼此相同。
例如，在通过抗蚀层进行图案化而形成了凹状的部位嵌入膏材料，使用剥离液等除去抗蚀层，能够得到封装框3和凸块4的图案。或者，也可以通过喷墨直接图案化。图案的高度根据器件的要求特性而不同，但高度越高越能够取得广阔的空间而提高气密可靠性。但是，图案越高则需要使抗蚀层越厚，图案精度以及高度的均匀性变差，为了折衷，所以需要选择适当的高度。例如，将图案的高度设为20μm左右。
然后，如图3所示，形成将相对基板5贯通的通路孔6，在相对基板5的上表面形成与通路孔6连接的引出电极7。在相对基板5的下表面，在与基板1的封装框3相对的位置形成环状的凸部8。在相对基板5的下表面，在与基板1的凸块4相对的位置形成凸部9。凸部8具有比封装框3的宽度窄的宽度。凸部9具有比凸块4的宽度窄的宽度。例如，将抗蚀层或者金属作为掩模，通过干蚀刻或者湿蚀刻对相对基板5的下表面进行加工而形成凸部8、9。另外，也可以通过蒸镀金属膜或者镀膜等形成凸部8、9。
然后，如图4所示，在进行升温而使金属膏的溶剂大体上挥发之后，使基板1的上表面和相对基板5的下表面相对而进行对准，在高温、加压下将两者接合。此时，将封装框3和凸部8接合，将凸块4和凸部9接合，并且将凸块4与相对基板5的通路孔6电接合。
通过与凸部8、9的接合而使封装框3以及凸块4的金属微粒被压缩，相邻的微粒彼此接合而块金属化。凸部8、9周边的金属膏图案也产生变形，封装框3以及凸块4与相对基板5的下表面密接。由此，制造中空封装器件。
就制造出的中空封装器件而言，经由凸块4、通路孔6以及引出电极7在器件电路2和外部之间进行电信号的输入输出。器件电路2或者通路孔6等可以形成于基板1和相对基板5的一方或者两方，也可以形成于上下两面。
图5是表示对金属膏图案进行了加压变形时的状态变化的剖面图。(a)在形成金属膏图案时，金属呈颗粒状，是在颗粒间存在空隙且空隙彼此相连的状态(open－cell；开放)。(b)如果逐步进行加压，则金属颗粒被压在一起，相邻颗粒间开始接合，变成空隙孤立的状态(closed－cell；闭合)。(c)最后，如果完全块状化，则不再进一步进行变形。如果将(a)中的图案的高度设为h，则(b)中的高度是0.4×h～0.6×h左右，(c)中的高度是0.3×h～0.5×h左右。为了确保中空部的气密性，空气等不得通过封装框3，因此，需要(b)或者(c)的状态。
图6是将接合前后的凸块部分进行放大后的剖面图。适当选择凸部9的高度m和凸块4的高度h，在接合后凸部9完全嵌入凸块4。由此，能够将凸块4与通路孔6可靠地电接合。接合后的基板间隔是h－δ。
另一方面，封装框3如上所述需要是(b)或者(c)的状态，因此，凸部8的正下方的x需要满足0.3×h≤x≤0.6×h。由于m+x＝h－δ，因此，0.4×h－δ≤m≤0.7×h－δ成立。因此，凸部8的高度m是接合后的基板1和相对基板5的间隔h－δ的0.4～0.7倍。此外，图案高度的变化δ波及到包含凸部8、9周边的封装框3以及凸块4全体，因此，如果有变化则负载分散，需要高负载。因此，δ＝0最佳，包含电接合的裕量而按0≤δ以最小值进行设计即可。
例如，在使用Au膏，将图案高度设为20μm的情况下，将凸部8的高度设为6μm～14μm，将接合后的高度调整为20μm左右即可。图7是表示Au膏的与加压相对的变形量的关系的图。在室温环境下测定出膏的厚度是20μm。例如，如果0≤δ≤1，则最终凸部8所承受的压力大于或等于100MPa，变形量是10μm。另一方面，凸部9所承受的压力小于或等于1MPa左右，变形量小，小于或等于1μm。因此，在施加了接合负载的情况下，负载大部分被封装框3的凸部8所承受。
在本实施方式中，能够通过凸块4将基板间电连接。能够在接合时不对封装框3的整个图案面积施加高压，而是对凸部8的部分选择性地施加高压。凸部8的高度是接合后的基板1和相对基板5的间隔的0.4～0.7倍。由此，在凸部8的正下方，封装框3的金属膏能够金属块化而使封装性提高。
另外，通过凸部8、9的锚定效应能够使相对基板5与凸块4、封装框3密接性良好地进行接合。凸块4和相对基板5的接合变牢固，因此，针对由于本装置的动作或者外部气氛引起的基板变形等导致的电接合的接触不良，耐受性变高。
在接合时通过凸部8实现封装，因此，凸部8的宽度越宽则封装性越好，如果过宽则接合时的负载不足。凸部8的宽度需要考虑该折衷关系进行设计，例如设为5μm～10μm左右。
图8是表示本发明的实施方式1涉及的中空封装器件的变形例1的剖面图。图9是沿图8的Ⅰ－Ⅱ的剖面图。图10是表示本发明的实施方式1涉及的中空封装器件的变形例2的剖面图。在图1中在封装框3内配置有凸块4，但也可以如图8～10所示在封装框3之外配置凸块4。另外，如图10所示每个芯片的封装框3的数量和凸块4的配置没有限制。
图11～13是表示本发明的实施方式1涉及的中空封装器件的封装框侧的凸部的变形例的俯视图。封装框3的凸部8除了连成环状以外没有限制。因此，也可以如图11所示蜿蜒曲折，或者如图12所示双重地形成，或者是如图13所示向双重环附加了分隔部的图案。由此，能够提高气密性。另外，封装框3的凸部8的形状也不受限制，也可以是圆筒状或者四棱柱等。
图14是表示本发明的实施方式1涉及的中空封装器件的变形例3的剖面图。在基板1之上形成金属膜10，通过金属膏的图案化在该金属膜10之上形成封装框3和凸块4。由此，金属膏和基板1的密接性良好。
图15是表示本发明的实施方式1涉及的中空封装器件的变形例4的剖面图。图16是表示对比例涉及的中空封装器件的剖面图。如果如图16所示金属膏图案即封装框3以及凸块4的接合时的变形不充分，则在接合时封装框3、凸块4与相对基板5的密接性差，不能将凸块4与通路孔6连接。因此，如图15所示，在相对基板5的下表面形成覆盖凸部8的金属膜11和覆盖凸部9的金属膜12。使凸部8、9分别隔着金属膜11、12与封装框3以及凸块4接合。由此，在接合时，封装框3、凸块4与相对基板5的密接性良好。另外，金属膜12与通路孔6电连接，因此，能够使凸块4隔着金属膜12与通路孔6可靠地电接合。
金属膜10～12将与金属膏相同材料、或者难以表面氧化的贵金属等用于与金属膏接触的最表层，将与基板1等基底的密接性高的材料用于最下层。例如，在将基板1和相对基板5设为Si的情况下，作为金属膜10～12而连续成膜出50nm厚的Ti膜和200nm厚的Au膜。作为金属膜10～12的图案化方法，存在基于抗蚀层图案化的蒸镀剥离、或者在金属溅射后进行抗蚀层图案化而通过研磨将不需要的部分蚀刻的方法等。
此外，也可以使基板1和相对基板5呈晶片形状而集中接合大量器件。例如，使用了Au金属膏的情况下的接合条件是温度300℃、压力100MPa等，温度、压力越高则接合性越好。作为金属膏材料，使用将Au、Ag、Cu、Pd、Pt的纳米级至亚微米级的颗粒溶解于溶剂的材料。Au、Ag、Cu、Pd、Pt的导电性良好，因此，能够使凸块4的导电性良好。特别是，Au、Pd、Pt的反应性低，难以进行表面氧化等变化，因此，接合时的块化良好，作为气密封装材料具有良好的特性。另外，为了使接合界面的密接性良好，优选在接合前进行Ar等离子体或者O2等离子体处理。
实施方式2
图17是表示本发明的实施方式2涉及的中空封装器件的剖面图。与实施方式1不同，没有设置与凸块4接合的凸部9。因此，能够在与封装框3接合的凸部8进一步施加高的负载，因此，能够进一步使封装性提高。另外，实施方式1的凸部9需要避开通路孔6进行布局，但在本实施方式中，不需要那样的布局考虑。其结果，能够提高布局的自由度，能够抑制布局面积的增大。
图18是表示本发明的实施方式2涉及的中空封装器件的变形例的剖面图。在相对基板5的下表面形成覆盖凸部8的金属膜11和与相对基板5的通路孔6电连接的金属膜12。使凸部8隔着金属膜11与封装框3接合，使凸块4隔着金属膜12与通路孔6电接合。由此，在接合时，金属膏图案和相对基板5的密接性良好，能够可靠地使凸块4与通路孔6电接合。
实施方式3
图19是表示本发明的实施方式3涉及的中空封装器件的剖面图。在本实施方式中，在基板1侧形成有凸部8、9。在该情况下也和实施方式1同样地，能够对凸部8、9的部分选择性地施加高压，因此，能够使封装性提高。另外，与实施方式1同样地，压力是相对于金属膏图案的压入量而决定的。
标号的说明
1基板，3封装框，4凸块，5相对基板，6通路孔，8、9凸部，11、12金属膜。

Claims (11)

1.一种中空封装器件的制造方法，其特征在于，具备以下工序：
通过金属膏的图案化在第1基板的主面同时形成凸块和环状的封装框；
在第2基板的主面形成具有比所述封装框的宽度窄的宽度的环状的凸部；以及
使所述第1基板的所述主面和所述第2基板的所述主面相对而进行对准，将所述封装框和所述凸部接合，并且将所述凸块与所述第2基板电接合，
所述凸部的高度是接合后的所述第1基板和所述第2基板的间隔的0.4～0.7倍。
2.根据权利要求1所述的中空封装器件的制造方法，其特征在于，
还具备在所述第2基板的所述主面形成覆盖所述凸部的第1金属膜和与所述第2基板的通路孔电连接的第2金属膜的工序，
使所述凸部隔着所述第1金属膜与所述封装框接合，使所述凸块隔着所述第2金属膜与所述通路孔电接合。
3.一种中空封装器件的制造方法，其特征在于，具备以下工序：
通过金属膏的图案化在第1基板的主面同时形成凸块和环状的封装框；
在第2基板的主面形成具有比所述封装框的宽度窄的宽度的环状的第1凸部和具有比所述凸块的宽度窄的宽度的第2凸部；以及
使所述第1基板的所述主面和所述第2基板的所述主面相对而进行对准，将所述封装框和所述第1凸部接合，将所述凸块和所述第2凸部接合，并且将所述凸块与所述第2基板电接合。
4.根据权利要求3所述的中空封装器件的制造方法，其特征在于，
所述第1凸部的高度是接合后的所述第1基板和所述第2基板的间隔的0.4～0.7倍。
5.根据权利要求3或4所述的中空封装器件的制造方法，其特征在于，
所述第2凸部完全嵌入所述凸块。
6.根据权利要求3至5中任一项所述的中空封装器件的制造方法，其特征在于，
还具备在所述第2基板的所述主面形成覆盖所述第1凸部的第1金属膜和覆盖所述第2凸部的第2金属膜的工序，
使所述第1凸部隔着所述第1金属膜与所述封装框接合，使所述第2凸部隔着所述第2金属膜与所述凸块接合。
7.根据权利要求6所述的中空封装器件的制造方法，其特征在于，
所述第2金属膜与所述第2基板的通路孔电连接。
8.根据权利要求1至7中任一项所述的中空封装器件的制造方法，其特征在于，
还具备在所述第1基板的主面形成金属膜的工序，
在所述金属膜之上形成所述封装框和所述凸块。
9.一种中空封装器件，其特征在于，具备：
第1基板；
环状的封装框，其形成于所述第1基板的主面；
凸块，其形成于所述第1基板的所述主面；
第2基板，其具有与所述第1基板的所述主面相对的主面；以及
环状的凸部，其形成于所述第2基板的所述主面，具有比所述封装框的宽度窄的宽度，
所述封装框和所述凸部接合，
所述凸块与所述第2基板电接合，
所述凸部的高度是所述第1基板和所述第2基板的间隔的0.4～0.7倍。
10.一种中空封装器件，其特征在于，具备：
第1基板；
环状的封装框，其形成于所述第1基板的主面；
凸块，其形成于所述第1基板的所述主面；
第2基板，其具有与所述第1基板的所述主面相对的主面；
环状的第1凸块，其形成于所述第2基板的所述主面，具有比所述封装框的宽度窄的宽度；以及
第2凸部，其形成于第2基板的所述主面，具有比所述凸块的宽度窄的宽度，
所述封装框和所述第1凸部接合，
所述凸块和所述第2凸部接合，
所述凸块与所述第2基板电接合。
11.根据权利要求10所述的中空封装器件，其特征在于，
所述第1凸部的高度是所述第1基板和所述第2基板的间隔的0.4～0.7倍。
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Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT201700103511A1 (it) * 2017-09-15 2019-03-15 St Microelectronics Srl Dispositivo microelettronico dotato di connessioni protette e relativo processo di fabbricazione
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JP7242220B2 (ja) * 2018-09-03 2023-03-20 キヤノン株式会社 接合ウェハ及びその製造方法、並びにスルーホール形成方法
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003188206A (ja) * 2001-12-20 2003-07-04 Mitsubishi Electric Corp 半導体装置用パッケージおよびその製造方法
JP2010206169A (ja) * 2009-02-27 2010-09-16 Ibiden Co Ltd プリント配線板の製造方法
JP2016197664A (ja) * 2015-04-03 2016-11-24 田中貴金属工業株式会社 パッケージの製造方法及び該方法により製造されるパッケージ

Family Cites Families (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3772740B2 (ja) 2001-12-21 2006-05-10 株式会社村田製作所 電子部品の製造方法
US7154206B2 (en) * 2002-07-31 2006-12-26 Kyocera Corporation Surface acoustic wave device and method for manufacturing same
JP2004207674A (ja) * 2002-10-30 2004-07-22 Kyocera Corp 電子部品装置の製造方法
JP4766831B2 (ja) * 2002-11-26 2011-09-07 株式会社村田製作所 電子部品の製造方法
US8853001B2 (en) * 2003-11-08 2014-10-07 Stats Chippac, Ltd. Semiconductor device and method of forming pad layout for flipchip semiconductor die
EP2428486B1 (en) * 2004-11-04 2021-04-14 Microchips Biotech, Inc. Compression and cold weld sealing methods and devices
JP4057017B2 (ja) 2005-01-31 2008-03-05 富士通株式会社 電子装置及びその製造方法
US7687906B2 (en) * 2006-03-31 2010-03-30 Brother Kogyo Kabushiki Kaisha Connecting structure, method for forming bump, and method for producing device-mounting substrate
WO2008108413A1 (ja) * 2007-03-05 2008-09-12 Kyocera Corporation 微小構造体装置および微小構造体装置の製造方法
JP5076166B2 (ja) * 2008-05-16 2012-11-21 セイコーエプソン株式会社 圧電デバイス及びその封止方法
JPWO2010021267A1 (ja) * 2008-08-21 2012-01-26 株式会社村田製作所 電子部品装置およびその製造方法
WO2010021268A1 (ja) * 2008-08-21 2010-02-25 株式会社村田製作所 電子部品装置およびその製造方法
US8692390B2 (en) * 2011-02-18 2014-04-08 Chipbond Technology Corporation Pyramid bump structure
JP5716627B2 (ja) * 2011-10-06 2015-05-13 オムロン株式会社 ウエハの接合方法及び接合部の構造
US9139423B2 (en) * 2012-01-19 2015-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Micro electro mechanical system structures
JP2014022699A (ja) 2012-07-24 2014-02-03 Nippon Telegr & Teleph Corp <Ntt> パッケージおよびその製造方法
JP5839326B2 (ja) * 2012-10-16 2016-01-06 国立大学法人東北大学 パッケージされたデバイス、パッケージ材の製造方法及びパッケージング方法
US8736045B1 (en) * 2012-11-02 2014-05-27 Raytheon Company Integrated bondline spacers for wafer level packaged circuit devices
DE112013002916T5 (de) * 2013-06-27 2015-03-05 Intel IP Corporation Hochleitende, hochfrequente Durchkontaktierung für elektronische Anlagen
US20150048509A1 (en) * 2013-08-16 2015-02-19 Globalfoundries Singapore Pte. Ltd. Cmos compatible wafer bonding layer and process
CN105084294A (zh) * 2014-04-21 2015-11-25 中芯国际集成电路制造(上海)有限公司 一种mems器件及其制备方法、电子装置
DE102014210852B4 (de) * 2014-06-06 2022-10-06 Robert Bosch Gmbh Bauteil mit zwei Halbleiter-Bauelementen, die über eine strukturierte Bond-Verbindungsschicht miteinander verbunden sind, und Verfahren zum Herstellen eines solchen Bauteils
DE102014210862B4 (de) * 2014-06-06 2022-10-06 Robert Bosch Gmbh Bauteil mit zwei Halbleiter-Bauelementen, zwischen denen mindestens zwei hermetisch dichte Kavernen ausgebildet sind, und Verfahren zum Herstellen einer entsprechenden Bondverbindung zwischen zwei Halbleiter-Bauelementen
KR20160084957A (ko) * 2015-01-06 2016-07-15 삼성디스플레이 주식회사 터치 스크린 패널 및 그 제조 방법
JP2016181555A (ja) * 2015-03-23 2016-10-13 日本電気株式会社 バンプ構造とバンプ接合構造およびバンプ製造方法
JP6350759B2 (ja) 2015-08-18 2018-07-04 三菱電機株式会社 半導体装置
WO2017132462A1 (en) * 2016-01-28 2017-08-03 Kyocera International, Inc. Semiconductor packaging structure and package having stress release structure
US20190031502A1 (en) * 2016-02-11 2019-01-31 Agency For Science, Technology And Research SEAL RING FOR AL-Ge BONDING
JP6862681B2 (ja) * 2016-05-23 2021-04-21 日本電気硝子株式会社 気密パッケージの製造方法及び気密パッケージ
KR102221892B1 (ko) 2016-10-24 2021-03-02 미쓰비시덴키 가부시키가이샤 반도체 장치

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003188206A (ja) * 2001-12-20 2003-07-04 Mitsubishi Electric Corp 半導体装置用パッケージおよびその製造方法
JP2010206169A (ja) * 2009-02-27 2010-09-16 Ibiden Co Ltd プリント配線板の製造方法
JP2016197664A (ja) * 2015-04-03 2016-11-24 田中貴金属工業株式会社 パッケージの製造方法及び該方法により製造されるパッケージ

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