CN102456584A - 在半导体小片和互连结构周围形成可穿透膜包封料的半导体器件和方法 - Google Patents

在半导体小片和互连结构周围形成可穿透膜包封料的半导体器件和方法 Download PDF

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Publication number
CN102456584A
CN102456584A CN2011103645669A CN201110364566A CN102456584A CN 102456584 A CN102456584 A CN 102456584A CN 2011103645669 A CN2011103645669 A CN 2011103645669A CN 201110364566 A CN201110364566 A CN 201110364566A CN 102456584 A CN102456584 A CN 102456584A
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interconnection structure
semiconductor chip
bed
pierceable membrane
projection
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CN102456584B (zh
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B·T·杜
R·A·帕盖拉
L·P·E·歘
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Changdian Integrated Circuit Shaoxing Co ltd
Stats Chippac Pte Ltd
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Stats Chippac Pte Ltd
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Abstract

本发明涉及在半导体小片和互连结构周围形成可穿透膜包封料的半导体器件和方法。半导体器件具有形成在载体上的多个凸块。在凸点之间将半导体小片安装到载体上。将具有基层、第一粘合剂层以及第二粘合剂层的可穿透膜包封料层置于半导体小片和凸块上。将可穿透膜包封料层按压到半导体小片和凸块上以将半导体小片和凸块嵌入第一粘合剂层和第二粘合剂层之内。分离第一粘合剂层和第二粘合剂层以去除基层和第一粘合剂层并且将第二粘合剂层留在半导体小片和凸块周围。使凸块从第二粘合剂层中露出。将载体去除。在半导体小片和第二粘合剂层上形成互连结构。在第二粘合剂层上形成与凸块电气相连的导电层。

Description

在半导体小片和互连结构周围形成可穿透膜包封料的半导体器件和方法
技术领域
本发明大体涉及半导体器件，并且更具体地涉及在半导体小片和互连结构周围形成可穿透膜包封料(penetrable film encapsulant)的半导体器件和方法。
背景技术
半导体器件在现代电子产品中很常见。半导体器件在电气部件的数量和密度方面不同。分立半导体器件通常包含一种类型的电气部件，例如发光二极管(LED)、小信号晶体管、电阻器、电容器、电感器以及功率金属氧化物半导体场效应晶体管(MOSFET)。集成半导体器件典型地包含数百至数百万的电气部件。集成半导体器件的实例包括微控制器、微处理器、电荷耦合器件(CCD)、太阳能电池以及数字微镜器件(DMD)。
半导体器件执行各种各样的功能，诸如信号处理、高速计算、传送和接收电磁信号、控制电子器件、将日光转变为电力以及为电视显示创建视像投射。在娱乐、通信、功率转换、网络、计算机以及消费品的领域中都用到半导体器件。还在军事应用、航空、汽车、工业控制器以及办公设备中用到半导体器件。
半导体器件采用半导体材料的电气特性。半导体材料的原子结构允许通过电场或基极电流的施加或通过掺杂工艺来操纵其导电率。掺杂将杂质引入半导体材料中以操纵和控制半导体器件的导电率。
半导体器件包含有源和无源的电气结构。包括双极型晶体管和场效应晶体管在内的有源结构控制电流的流动。通过改变掺杂的程度和 电场或基极电流的施加，晶体管或者促进或者限制电流的流动。包括电阻器、电容器以及电感器在内的无源结构创建对于执行各种电气功能所必要的、电压与电流之间的关系。无源结构与有源结构电气相连(electrically connected)以形成电路，所述电路使得半导体器件能够执行高速计算及其他有用的功能。
通常利用两个复杂的制造工艺，即前端制造和后端制造来制造半导体器件，所述前端制造和后端制造分别涉及大概数百个步骤。前端制造涉及多个小片(die)在半导体晶圆的表面上的形成。每个小片典型地是完全相同的并且包含通过使有源部件与无源部件电气相连而形成的电路。后端制造涉及从已完成的晶圆中分切出单个小片并且对小片进行封装以提供结构支撑和环境隔离。
半导体制造的一个目标在于生产更小的半导体器件。更小的器件典型地消耗更少的功率、具有更高的性能并且可以更高效地生产。另外，更小的半导体器件具有更小的占用面积(footprint)，这对于更小的最终产品而言是所期望的。可通过产生具有更小、密度更高的有源和无源部件的小片的前端工艺的改进来实现更小的小片尺寸。后端工艺可通过电气互连和封装材料的改进产生具有更小占用面积的半导体器件封装。
在扇出晶圆级芯片尺度封装(Fo-WLCSP)中，通常将半导体小片安装到临时载体上。典型地通过模具注塑(mold injection)将包封料沉积在半导体小片和载体上。载体被去除以露出半导体小片，并且在露出的半导体小片上形成内建互连结构。
已知半导体小片在包封期间，特别是在模具注塑期间，竖向和横向地偏移，这会引起内建互连结构的不对准。将半导体小片固定在载体上以减少小片偏移的一种技术涉及在载体上形成可浸润焊垫(wettable pad)并且用凸块(bump)将半导体小片固定到所述可浸润焊垫上。可浸润焊垫的形成典型地涉及光刻、蚀刻以及电镀，这些都是费时且昂贵的制造工艺。可浸润焊垫和凸块增加了半导体小片与内建互 连结构之间的互连阻抗。
通常通过包封料形成多个导电通孔或立柱以得到与层叠的半导体器件的z方向竖向电气互连。导电通孔典型地与包封料共面。导电通孔的最小露出表面面积降低了对于层叠的半导体器件的接合可靠性(joint reliability)。
发明内容
存在减少小片偏移以及提高对层叠的半导体器件的接合可靠性的需要。据此，在一个实施例中，本发明是一种制作半导体器件的方法，所述方法包括下述步骤：提供临时载体，在所述临时载体上形成多个第一凸块，在所述第一凸块之间将半导体小片安装到所述临时载体上，提供包括基层(base layer)、第一粘合剂层以及第二粘合剂层的可穿透膜包封料层，将所述可穿透膜包封料层按压到所述半导体小片和第一凸块上以将所述半导体小片和第一凸块嵌入所述第一粘合剂层和第二粘合剂层之内，将所述可穿透膜包封料层固化，分离所述第一粘合剂层和第二粘合剂层以去除所述基层和第一粘合剂层并且将所述第二粘合剂层留在所述半导体小片和第一凸块周围，去除所述临时载体，以及在所述半导体小片和第二粘合剂层上形成互连结构。
在另一实施例中，本发明是一种制作半导体器件的方法，所述方法包括下述步骤：提供载体，在所述载体上形成第一互连结构，将半导体小片安装到所述载体上，提供可穿透膜包封料层，将所述可穿透膜包封料层按压到所述半导体小片和第一互连结构上以将所述半导体小片和第一互连结构嵌入所述可穿透膜包封料层之内，去除所述可穿透膜包封料层的第一部分以露出所述第一互连结构而同时将所述可穿透膜包封料层的第二部分留在所述半导体小片和第一互连结构周围，去除所述载体，以及在所述半导体小片和所述可穿透膜包封料层的第二部分上形成第二互连结构。
在另一实施例中，本发明是一种制作半导体器件的方法，所述方 法包括下述步骤：提供可穿透膜包封料层，将所述可穿透膜包封料层按压到半导体小片和第一互连结构上以将所述半导体小片和第一互连结构嵌入所述可穿透膜包封料层之内，以及去除所述可穿透膜包封料层的第一部分以露出所述第一互连结构而同时将所述可穿透膜包封料层的第二部分留在所述半导体小片和第一互连结构周围。
在另一实施例中，本发明是一种半导体器件，所述半导体器件包括半导体小片和布置在所述半导体小片周围的第一互连结构。可穿透膜包封料层被按压到所述半导体小片和第一互连结构上以将所述半导体小片和第一互连结构嵌入所述可穿透膜包封料层之内。第二互连结构被形成在所述半导体小片和可穿透膜包封料层上。
附图说明
图1示出了有不同类型的封装安装到其表面上的PCB；
图2a-2c示出了安装到PCB上的代表性的半导体封装的更多细节；
图3a-3c示出了具有被划片街区(saw street)隔开的多个半导体小片的半导体晶圆；
图4a-41示出了在半导体小片和互连结构周围形成可穿透膜包封料层的工艺；
图5示出了具有形成在半导体小片和互连结构周围的可穿透膜包封料层的Fo-WLCSP；
图6示出了与半导体小片共面的可穿透膜包封料层；
图7示出了形成在可穿透膜包封料层上的RDL；
图8示出了分别具有形成在半导体小片和互连结构周围的可穿透膜包封料层的层叠的Fo-WLCSP；以及
图9示出了形成在半导体小片上的接触焊垫上的凸块。
具体实施方式
参考附图在以下说明中以一个或多个实施例描述本发明，在附图中相同的标号代表相同或相似的元件。尽管就实现本发明的目的的最佳方式描述了本发明，但本领域技术人员将理解的是，目的在于涵盖可被包括在本发明的主旨和范围之内的替换、修改以及等效内容，本发明的主旨和范围由所附权利要求及以下公开内容和附图所支持的所附权利要求的等效内容限定。
通常利用两个复杂的制造工艺：前端制造和后端制造，来制造半导体器件。前端制造涉及多个小片在半导体晶圆的表面上的形成。晶圆上的每个小片包含有源和无源电气部件，其电气相连以形成功能电路。诸如晶体管和二极管的有源电气部件具有控制电流的流动的能力。诸如电容器、电感器、电阻器以及变压器的无源电气部件创建对于执行电路功能所必要的、电压与电流之间的关系。
通过包括掺杂、沉积、光刻、蚀刻以及平坦化的一系列工艺步骤在半导体晶圆的表面上形成无源和有源部件。掺杂通过诸如离子注入或热扩散等技术将杂质引入半导体材料。掺杂工艺修改有源器件中的半导体材料的导电率，将半导体材料转变为绝缘体、导体或响应于电场或基极电流而动态地改变半导体材料的导电率。晶体管包含不同类型和程度的掺杂的区域，根据在施加电场或基极电流时使得晶体管能够促进或限制电流的流动的需要来布置所述不同类型和程度的掺杂。
由具有不同电气特性的材料的层形成有源和无源部件。可以通过由被沉积的材料的类型部分确定的各种沉积技术来形成所述层。例如，薄膜沉积可涉及化学气相沉积(CVD)、物理气相沉积(PVD)、电镀以及无电镀工艺。通常在每个层上形成图案以形成有源部件的部分、无源部件的部分或部件之间的电气连接。
可以利用光刻在各个层上形成图案，光刻涉及例如光致抗蚀剂的光敏材料在待被形成图案的层上的沉积。利用光将图案从光掩膜转移到光致抗蚀剂上。利用溶剂去除受到光照的光致抗蚀剂图案的部分，露出待被形成图案的下面的层的部分。去除光致抗蚀剂的剩余部分， 留下形成图案的层。可替换地，通过利用诸如无电镀和电镀等技术将材料直接沉积到由先前的沉积/蚀刻工艺形成的区域或空洞(void)中而在一些类型的材料上形成图案。
在已有图案上沉积材料薄膜可能放大下面的图案并且产生非齐平的表面。需要齐平的表面来生产更小并且更密集装配的有源和无源部件。平坦化可以被用于从晶圆的表面上去除材料并且产生齐平的表面。平坦化涉及用抛光垫对晶圆的表面抛光。在抛光期间对晶圆的表面添加研磨材料和腐蚀性化学品。化学品的研磨和腐蚀作用的综合机械作用去除任何不规则的表面构形，从而产生齐平的表面。
后端制造指将已完成的晶圆切割或分切为单个小片并且接着对小片进行封装以得到结构支撑和环境隔离。为了分切小片，沿着晶圆的被称为划片街区或划线(scribe)的非功能区域对晶圆进行刻划和切断。利用激光切割工具或锯条(saw blade)对晶圆进行分切。在分切之后，将单个小片安装到封装衬底上，该封装衬底包括用于与其他系统部件互连的管脚或接触焊垫。形成在半导体小片上的接触焊垫然后被连接至封装内的接触焊垫。可以用焊料凸块、柱形凸块、导电胶或引线键合(wirebond)来进行电气连接。在封装上沉积包封料或其他模塑材料以提供物理支撑和电气隔离。然后将完成的封装插入电气系统并且使半导体器件的功能对于其他系统部件可用。
图1示出了具有芯片载体衬底或印刷电路板(PCB)52的电子器件50，在该芯片载体衬底或印刷电路板(PCB)52的表面上安装有多个半导体封装。电子器件50可取决于应用而具有一种类型的半导体封装或多种类型的半导体封装。为了示意的目的在图1中示出了不同类型的半导体封装。
电子器件50可以是使用半导体封装来执行一个或多个电气功能的单机系统。可替换地，电子器件50可以是较大的系统的子部件。例如，电子器件50可以是蜂窝式电话、个人数字助理(PDA)、数字视频摄像机(DVC)或其他电子通信设备的部分。可替换地，电子器件50 可以是图形卡、网络接口卡或可被插入计算机的其他信号处理卡。半导体封装可以包括微处理器、存储器、专用集成电路(ASIC)、逻辑电路、模拟电路、RF电路、分立器件或其他半导体小片或电气部件。小型化和重量减轻对于这些产品被市场接受是必不可少的。必须减小半导体器件之间的距离以实现更高的密度。
在图1中，PCB 52为安装在PCB上的半导体封装的结构支撑和电气互连提供了通用衬底。利用蒸发、电镀、无电镀、丝网印刷或其他合适的金属沉积工艺在PCB 52的表面上或在PCB 52的各个层内形成导电信号迹线54。信号迹线54被用于半导体封装中的每一个、所安装的部件以及其他外部系统部件之间的电气通信。迹线54还为半导体封装中的每一个提供功率和地连接。
在一些实施例中，半导体器件具有两个封装级。第一级封装是用于将半导体小片机械地并且电气地附接到中间载体上的技术。第二级封装涉及将中间载体机械地并且电气地附接到PCB上。在其他实施例中，半导体器件可仅具有其中直接将小片机械地并且电气地安装到PCB上的第一级封装。
为了示意的目的，在PCB 52上示出了若干种类型的第一级封装，包括引线键合封装56和倒装芯片58。另外，包括球栅阵列(BGA)60、凸块芯片载体(BCC)62、双列直插式封装(DIP)64、矩栅阵列(LGA)66、多芯片模块(MCM)68、四边扁平无引脚封装(QFN)70以及四边扁平封装72在内的若干种类型的第二级封装被示出为安装在PCB 52上。根据系统要求，用第一级封装样式和第二级封装样式的任何组合构成的半导体封装的任何组合以及其他电子部件可被连接至PCB 52。在一些实施例中，电子器件50包括单个附接的半导体封装，而其他实施例需要多个互连的封装。通过在单个衬底上结合一个或多个半导体封装，制造商可以将预制的部件并入电子器件和系统中。由于半导体封装包括成熟的功能，因此可以利用较便宜的部件和流线型制造工艺来制造电子器件。结果得到的器件不太可能发生故障并且制造花费不那 么大，从而产生对于用户而言较低的成本。
图2a-2c示出了示例性半导体封装。图2a示出了安装在PCB 52上的DIP 64的更多细节。半导体小片74包括有源区域，该有源区域包含模拟或数字电路，所述模拟或数字电路被实现为形成在小片之内并且根据小片的电气设计电气互连的有源器件、无源器件、导电层以及介电层。例如，所述电路可以包括一个或多个晶体管、二极管、电感器、电容器、电阻器以及形成在半导体小片74的有源区域之内的其他电路元件。接触焊垫76是一层或多层导电材料，诸如铝(Al)、铜(Cu)、锡(Sn)、镍(Ni)、金(Au)或银(Ag)等，并且其与形成在半导体小片74内的电路元件电气相连。在DIP 64的组装期间，利用金-硅低共熔层或诸如热环氧化物或环氧树脂的粘合剂材料将半导体小片74安装到中间载体78上。封装体包括诸如聚合物或陶瓷的绝缘封装材料。导体引出线80和引线键合82提供半导体小片74与PCB 52之间的电气互连。在封装上沉积包封料84以便通过防止湿气和颗粒进入封装而污染小片74或引线键合82来实现环境防护。
图2b示出了安装在PCB 52上的BCC 62的更多细节。利用底部填充料(underfill)或环氧树脂粘合剂材料92将半导体小片88安装在载体90上。引线键合94在接触焊垫96与98之间提供第一级封装互连。在半导体小片88和引线键合94上沉积模塑化合物或包封料100以为器件提供物理支撑和电气隔离。利用诸如电镀或无电镀等合适的金属沉积工艺在PCB 52的表面上形成接触焊垫102以防止氧化。接触焊垫102与PCB 52中的一个或多个导电信号迹线54电气相连。在BCC62的接触焊垫98与PCB 52的接触焊垫102之间形成凸块104。
在图2c中，以倒装芯片型第一级封装将半导体小片58面朝下地安装到中间载体106上。半导体小片58的有源区域108包含模拟或数字电路，所述模拟或数字电路被实现为根据小片的电气设计形成的有源器件、无源器件、导电层以及介电层。例如，所述电路可以包括一个或多个晶体管、二极管、电感器、电容器、电阻器以及有源区域 108之内的其他电路元件。半导体小片58通过凸块110电气地并且机械地连接至载体106。
使用凸块112以BGA型第二级封装将BGA 60电气地并且机械地连接至PCB 52。半导体小片58通过凸块110、信号线114以及凸块112与PCB 52中的导电信号迹线54电气相连。在半导体小片58和载体106上沉积模塑化合物或包封料116以为器件提供物理支撑和电气隔离。倒装芯片半导体器件提供了从半导体小片58上的有源器件到PCB 52上的导电迹线的短导电路径以减小信号传播距离、降低电容并且改善整体电路性能。在另一实施例中，可以利用倒装芯片型第一级封装直接将半导体小片58机械地并且电气地连接至PCB 52而无需中间载体106。
图3a示出了具有诸如硅、锗、砷化镓、磷化铟或碳化硅等用于结构支撑的基衬底材料122的半导体晶圆120。多个半导体小片或部件124被形成在晶圆120上并且如上文所描述的那样被划片街区126隔开。
图3b示出了半导体晶圆120的一部分的横截面视图。每个半导体小片124具有背表面128和有源表面130，该有源表面包含模拟或数字电路，所述模拟或数字电路被实现为形成在小片之内并且根据小片的电气设计和功能电气互连的有源器件、无源器件、导电层以及介电层。例如，所述电路可包括一个或多个晶体管、二极管以及形成在有源表面130之内的其他电路元件以实现模拟电路或数字电路，诸如数字信号处理器(DSP)、ASIC、存储器或其他信号处理电路。半导体小片124还可包含诸如电感器、电容器以及电阻器的集成无源器件(IPD)以用于RF信号处理。在一个实施例中，半导体小片124是倒装芯片型半导体小片。
利用PVD、CVD、电镀、无电镀工艺或其他合适的金属沉积工艺在有源表面130上形成导电层132。导电层132可以是一层或多层Al、Cu、Sn、Ni、Au、Ag或其他合适的导电材料。导电层132操作为与 有源表面130上的电路电气相连的接触焊垫。
在图3c中，利用锯条或激光切割工具134通过划片街区126分切半导体晶圆120以将晶圆分离为单个半导体小片124。
图4a-41相对于图1和图2a-2c示出了在半导体小片和互连结构周围形成可穿透膜包封料层的工艺。图4a示出了衬底或载体140，其包含诸如硅、聚合物、氧化铍或适于结构支撑的其他低成本刚性材料的临时或牺牲性的基材料。界面层或双面胶带142作为临时的粘合剂键合膜或蚀刻终止层被形成在载体140上。
在图4b中，利用蒸发、电镀、无电镀、球滴(ball drop)或丝网印刷工艺在载体140和界面层142上沉积导电凸块材料。该凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料(solder)及其组合，并且采用可选的助熔剂(flux solution)。例如，凸块材料可以是低共熔的Sn/Pb、高铅焊料或无铅焊料。在一个实施例中，通过将材料加热至其熔点以上而使凸块材料回流以形成球体或凸块144。将凸块144布置在指定用于稍后安装的半导体小片的安装部位146周围。凸块144代表可被形成在载体140上的一种类型的z方向竖向互连结构。该互连结构也可使用柱形凸块、微型凸块或其他电气互连。
在图4c-4d中，利用取放操作(pick and place operation)将来自图3a-3c的半导体小片124安装到凸块144之间的部位146上，其中使有源表面130朝向载体140和界面层142。在一个实施例中，半导体小片124具有450微米(μm)的厚度。凸块144的高度大于450μm以延伸至半导体小片124的背表面128之上。图4e是形成在半导体小片124周围的凸块144的俯视图。可以在将半导体小片124安装到载体140上之后形成凸块144。
图4f示出了导电立柱148在半导体小片124周围形成在载体140上的可替换的实施例。可以通过在安装半导体小片124之前或之后在载体140上沉积光致抗蚀剂层并且然后利用光刻在光致抗蚀剂上形成图案以在立柱位置上形成通孔而形成导电立柱148。利用电镀、无电 镀工艺或其他合适的金属沉积工艺以Al、Cu、Sn、Ni、Au、Ag、Ti、钨(W)、多晶硅或其他合适的导电材料填充所述通孔。去除光致抗蚀剂，留下z方向的竖向导电立柱148。导电立柱148延伸至半导体小片124的背表面128之上。
图4g示出了包括基层152、紫外线(UV)B阶(B-stage)膜粘合剂层154以及热固性粘合剂膜层156的可穿透膜包封料层150。在一个实施例中，基层152包含聚酯，并且UV B阶膜粘合剂层154包含丙烯酸聚合物。热固性粘合剂膜层156具有大约20-45 ppm/K的低热膨胀系数(CTE)和大约1000-34000MPa的高模量，例如如在Denko AS-0001、AS-0016以及AS-0036粘合剂膜中发现的那样。将可穿透膜包封料层150加热至70℃以使粘合剂层154和156呈现柔软性、可延展性以及顺应性。
将可穿透膜包封料层150置于半导体小片124、凸块144以及载体140上。以力F将可穿透膜包封料层150按压到半导体小片124和凸块144上以使半导体小片和凸块穿入粘合剂层154和156中。在粘合剂层156非常接近或触及界面层142的顶表面之后去除力F。图4h示出了被嵌入粘合剂层154和156中的半导体小片124和凸块144。凸块144可以接触或可不接触基层152。可穿透膜包封料层150被固化以使粘合剂层156变硬并且牢牢固定住半导体小片124和凸块144。
在图4i中，通过沿箭头158的方向的机械剥离或机械顶离(lift-off)来去除基层152和UV B阶膜粘合剂层154。B阶膜粘合剂层154在UV辐射下分离，而粘合剂层156作为包封层留在半导体小片124和凸块144周围以用于结构支撑以及使半导体器件免受外部元件和污染物影响的环境防护。凸块144从粘合剂层156中露出以用于外部电气互连。也可以通过化学蚀刻、CMP、机械研磨、热烤、UV光、激光扫描或湿式剥模来去除基层152和B阶膜粘合剂层154。
在图4j中，通过化学蚀刻、机械剥离、CMP、机械研磨、热烤、UV光、激光扫描或湿式剥模来去除载体140和界面层142以露出有 源表面130和凸块144。
在图4k中，在半导体小片124的有源表面130和粘合剂层156上形成底侧内建互连结构160。内建互连结构160包括利用诸如溅射、电镀以及无电镀等图案形成和金属沉积工艺形成的导电层162。导电层162可以是一层或多层Al、Cu、Sn、Ni、Au、Ag或其他合适的导电材料。导电层162的一部分与凸块144电气相连。导电层162的另一部分与半导体小片124的接触焊垫132电气相连。导电层162的其他部分可根据半导体器件的设计和功能而共电(electrically common)或电气隔离。
内建互连结构160还包括形成在导电层162之间用于电气隔离的绝缘层或钝化层164。绝缘层164包含一层或多层二氧化硅(SiO2)、氮化硅(Si3N4)、氮氧化硅(SiON)、五氧化二钽(Ta2O5)、氧化铝(Al2O3)或具有相似绝缘特性和结构特性的其他材料。利用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化形成绝缘层164。通过蚀刻工艺去除绝缘层164的一部分以露出导电层162。
在图41中，利用蒸发、电镀、无电镀、球滴或丝网印刷工艺在内建互连结构160上沉积导电凸块材料并且使其与露出的导电层162电气相连。凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及其组合，并且采用可选的助熔剂。例如，凸块材料可以是低共熔的Sn/Pb、高铅焊料或无铅焊料。利用合适的附接或键合工艺将凸块材料键合到导电层162上。在一个实施例中，通过将材料加热至其熔点以上而使凸块材料回流以形成球体或凸块166。在一些应用中，使凸块166第二次回流以改善与导电层162的电接触。凸块也可被压缩键合至导电层162。凸块166代表可被形成在导电层162上的一种类型的互连结构。互连结构也可以使用键合引线、柱形凸块、微型凸块或其他电气互连。
利用锯条或激光切割工具168将半导体小片124分切为单个Fo-WLCSP 170。图5示出了分切之后的Fo-WLCSP 170。半导体小片 124与内建互连结构160以及凸块144和166电气相连。具有被按压到半导体小片124和凸块144上的粘合剂层154和156的可穿透膜包封料层150减少了横向和竖向的小片偏移。在去除基层152和UV B阶膜粘合剂层154之后，粘合剂层156作为包封层留在半导体小片124和凸块144周围以用于结构支撑以及使半导体器件免受外部元件和污染物影响的环境防护。通过将粘合剂层156作为包封层按压在半导体小片124和凸块144上，没有如在现有技术中所发现的、引起小片偏移的包封料注入。
类似于图5，图6示出了WLCSP 172的实施例，其中粘合剂层156与半导体小片124的背表面128共面。
类似于图5，图7示出了WLCSP 174的实施例，其中利用诸如溅射、电镀以及无电镀的图案形成和金属沉积工艺在粘合剂层156上形成导电层或重分布层(RDL)176。导电层176可以是一层或多层Al、Cu、Sn、Ni、Au、Ag或其他合适的导电材料。热固性粘合剂层156的固化工艺实现高温金属沉积。导电层176的一部分与凸块144电气相连。导电层176的其他部分可根据半导体器件的设计和功能而共电或电气隔离。
图8示出了通过凸块144、内建互连结构160以及RDL 176电气相连的多个层叠的Fo-WLCSP 170。在凸块144延伸至粘合剂层156之上的情况下，对于与相邻的Fo-WLCSP 170的竖向电气互连而言有更多的接触表面面积和更高的接合可靠性。
类似于图5，图9示出了WLCSP 180的实施例，其中在接触焊垫132上形成有凸块182。例如在图4b的处理步骤期间，在安装半导体小片124之前在界面层142上形成接触焊垫184。类似于图4c，将具有凸块182的半导体小片124安装到接触焊垫184上。
尽管已详细示出了本发明的一个或多个实施例，但技术人员将理解，可对这些实施例进行修改和调整而不背离如以下权利要求所阐述的本发明的范围。

Claims (25)

1.一种制作半导体器件的方法，所述方法包括：
提供临时载体；
在所述临时载体上形成多个第一凸块；
在所述第一凸块之间将半导体小片安装到所述临时载体上；
提供包括基层、第一粘合剂层以及第二粘合剂层的可穿透膜包封料层；
将所述可穿透膜包封料层按压到所述半导体小片和第一凸块上以将所述半导体小片和第一凸块嵌入所述第一粘合剂层和第二粘合剂层之内；
将所述可穿透膜包封料层固化；
分离所述第一粘合剂层和第二粘合剂层以去除所述基层和第一粘合剂层并且将所述第二粘合剂层留在所述半导体小片和第一凸块周围；
去除所述临时载体；以及
在所述半导体小片和第二粘合剂层上形成互连结构。
2.根据权利要求1所述的方法，其中，所述第一凸块延伸至所述第二粘合剂层之上。
3.根据权利要求1所述的方法，其还包括在所述互连结构上形成多个第二凸块。
4.根据权利要求1所述的方法，其中，所述第二粘合剂层与所述半导体小片共面。
5.根据权利要求1所述的方法，其还包括在所述第二粘合剂层上形成与所述第一凸块电气相连的导电层。
6.根据权利要求1所述的方法，其还包括：
层叠多个半导体器件；以及
通过所述第一凸块和互连结构使层叠的半导体器件电气相连。
7.一种制作半导体器件的方法，所述方法包括：
提供载体；
在所述载体上形成第一互连结构；
将半导体小片安装到所述载体上；
提供可穿透膜包封料层；
将所述可穿透膜包封料层按压到所述半导体小片和第一互连结构上以将所述半导体小片和第一互连结构嵌入所述可穿透膜包封料层之内；
去除所述可穿透膜包封料层的第一部分以露出所述第一互连结构而同时将所述可穿透膜包封料层的第二部分留在所述半导体小片和第一互连结构周围；
去除所述载体；以及
在所述半导体小片和所述可穿透膜包封料层的第二部分上形成第二互连结构。
8.根据权利要求7所述的方法，其中，所述可穿透膜包封料层包括基层、第一粘合剂层以及第二粘合剂层。
9.根据权利要求7所述的方法，其还包括将所述可穿透膜包封料层固化。
10.根据权利要求7所述的方法，其还包括在所述可穿透膜包封料层的第二部分上形成与所述第一互连结构电气相连的导电层。
11.根据权利要求7所述的方法，其中，所述第一互连结构包括凸块或导电立柱。
12.根据权利要求7所述的方法，其还包括：
层叠多个半导体器件；以及
通过所述第一互连结构和第二互连结构使层叠的半导体器件电气相连。
13.根据权利要求7所述的方法，其还包括在将所述半导体小片安装到所述载体上之前在所述半导体小片上的接触焊垫上形成凸块。
14.一种制作半导体器件的方法，所述方法包括：
提供可穿透膜包封料层；
将所述可穿透膜包封料层按压到半导体小片和第一互连结构上以将所述半导体小片和第一互连结构嵌入所述可穿透膜包封料层之内；以及
去除所述可穿透膜包封料层的第一部分以露出所述第一互连结构而同时将所述可穿透膜包封料层的第二部分留在所述半导体小片和第一互连结构周围。
15.根据权利要求14所述的方法，其还包括在所述半导体小片和所述可穿透膜包封料层的第二部分上形成第二互连结构。
16.根据权利要求14所述的方法，其中，所述可穿透膜包封料层包括基层、第一粘合剂层以及第二粘合剂层。
17.根据权利要求14所述的方法，其还包括将所述可穿透膜包封料层固化。
18.根据权利要求14所述的方法，其还包括在所述可穿透膜包封料层的第二部分上形成与所述第一互连结构电气相连的导电层。
19.根据权利要求14所述的方法，其中，所述第一互连结构包括凸块或导电立柱。
20.根据权利要求14所述的方法，其还包括：
层叠多个半导体器件；以及
通过所述第一互连结构使层叠的半导体器件电气相连。
21.一种半导体器件，所述半导体器件包括：
半导体小片；
第一互连结构，其被布置在所述半导体小片周围；
可穿透膜包封料层，其被按压到所述半导体小片和第一互连结构上以将所述半导体小片和第一互连结构嵌入所述可穿透膜包封料层之内；以及
第二互连结构，其被形成在所述半导体小片和可穿透膜包封料层上。
22.根据权利要求21所述的半导体器件，其中，所述第一互连结构从所述可穿透膜包封料层中露出。
23.根据权利要求21所述的半导体器件，其还包括导电层，所述导电层被形成在所述可穿透膜包封料层上并且与所述第一互连结构电气相连。
24.根据权利要求21所述的半导体器件，其中，所述第一互连结构包括凸块或导电立柱。
25.根据权利要求21所述的半导体器件，其还包括通过所述第一互连结构和第二互连结构电气相连的多个层叠的半导体器件。
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