TWI541913B - 半導體裝置以及在半導體晶粒和互連結構周圍形成可穿透膜封裝材料之方法 - Google Patents

半導體裝置以及在半導體晶粒和互連結構周圍形成可穿透膜封裝材料之方法 Download PDF

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TWI541913B
TWI541913B TW100136916A TW100136916A TWI541913B TW I541913 B TWI541913 B TW I541913B TW 100136916 A TW100136916 A TW 100136916A TW 100136916 A TW100136916 A TW 100136916A TW I541913 B TWI541913 B TW I541913B
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layer
interconnect structure
semiconductor die
encapsulating material
semiconductor
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TW100136916A
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TW201222687A (en
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杜雍台
瑞莎Ａ 派蓋菈
佩儀 周
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史達晶片有限公司
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Description

半導體裝置以及在半導體晶粒和互連結構周圍形成可穿透膜封裝材料之方法
本發明係大致有關於半導體裝置，並且更具體而言係有關於一種半導體裝置以及在一半導體晶粒和互連結構周圍形成一可穿透的膜封裝材料之方法。
半導體裝置係常見於現代的電子產品中。半導體裝置係在電氣構件的數目及密度上變化。離散的半導體裝置一般包含一類型的電氣構件，例如，發光二極體(LED)、小信號電晶體、電阻器、電容器、電感器、以及功率金屬氧化物半導體場效電晶體(MOSFET)。集積的半導體裝置通常包含數百到數百萬個電氣構件。集積的半導體裝置的例子係包含微控制器、微處理器、電荷耦合裝置(CCD)、太陽能電池、以及數位微鏡裝置(DMD)。
半導體裝置係執行廣範圍的功能，例如，信號處理、高速的計算、傳送及接收電磁信號、控制電子裝置、轉換太陽光成為電力、以及產生用於電視顯示器的視覺投影。半導體裝置係見於娛樂、通訊、電力轉換、網路、電腦以及消費者產品的領域中。半導體裝置亦見於軍事的應用、航空、汽車、工業用的控制器、以及辦公室設備中。
半導體裝置係利用半導體材料的電氣特性。半導體材料的原子結構係容許其導電度能夠藉由一電場或基極電流的施加或是透過摻雜的製程加以操縱。摻雜係將雜質帶入半導體材料中，以操縱及控制半導體裝置的導電度。
一半導體裝置係包含主動及被動的電性結構。包含雙載子及場效電晶體的主動結構係控制電流的流動。藉由改變摻雜的程度以及一電場或基極電流的施加，該電晶體不是提升、就是限制電流的流動。包含電阻器、電容器及電感器的被動結構係在電壓及電流之間產生執行各種電氣功能所必要的一種關係。該被動及主動結構係電連接以形成電路，此係使得該半導體裝置能夠執行高速的計算及其它有用的功能。
半導體裝置一般是利用兩個複雜的製程，亦即，前端製造及後端製造來加以製造，每個製造潛在涉及數百道步驟。前端製造係牽涉到複數個晶粒在一半導體晶圓的表面上的形成。每個晶粒通常是相同的並且包含藉由電連接主動及被動構件所形成的電路。後端製造係牽涉到從完成的晶圓單粒化(singulating)個別的晶粒並且封裝該晶粒以提供結構的支撐以及環境的隔離。
半導體製造的一目標是產出較小的半導體裝置。較小的裝置通常消耗較低的功率，具有較高的效能，並且可以更有效率地加以生產。此外，較小的半導體裝置具有一較小的覆蓋區，此係較小的終端產品所期望的。較小的晶粒尺寸可藉由在產生具有較小且較高密度的主動及被動構件之晶粒的前端製程中的改良來達成。後端製程可以藉由在電互連及封裝材料上的改良來產生具有較小覆蓋區的半導體裝置封裝。
在展開形式晶圓級晶片尺寸封裝(Fo-WLCSP)中，一半導體晶粒通常是安裝到一臨時的載體。一封裝材料(encapsulant)通常是藉由模具注入而沉積在該半導體晶粒及載體之上。該載體係被移除以露出該半導體晶粒，並且一積層的(build-up)互連結構係形成在該露出的半導體晶粒之上。
半導體晶粒已知在封裝期間，尤其是在模具注入期間會垂直及橫向地位移，此可能會造成該積層的互連結構的失準。一種將半導體晶粒固定到載體以減低晶粒位移的技術係牽涉到在該載體之上形成可濕性(wettable)墊，並且利用凸塊以將該半導體晶粒固定到該些可濕性墊。可濕性墊的形成通常牽涉到微影、蝕刻及電鍍，此係耗時且昂貴的製程。可濕性墊及凸塊係增加在半導體晶粒及積層的互連結構之間的互連電阻。
複數個導電的貫孔或柱通常穿過該封裝材料來加以形成，以用於z方向的垂直電互連到堆疊的半導體裝置。該些導電的貫孔通常是與該封裝材料共平面的。該導電的貫孔之最小露出的表面積係降低和堆疊的半導體裝置之接合的可靠度。
對於減低晶粒位移且改善堆疊的半導體裝置之接合可靠度係存在著需求。於是，在一實施例中，本發明係一種製造一半導體裝置之方法，其係包括以下步驟：提供一臨時載體，在該臨時載體之上形成複數個第一凸塊，在該些第一凸塊之間安裝一半導體晶粒至該臨時載體，提供一包含一基底層、第一黏著層以及第二黏著層之可穿透的膜封裝材料層，在該半導體晶粒及第一凸塊之上加壓該可穿透的膜封裝材料層以將該半導體晶粒及第一凸塊嵌入在該第一及第二黏著層之內，固化該可穿透的膜封裝材料層，分開該第一黏著層以及第二黏著層以移除該基底層以及第一黏著層並且留下在該半導體晶粒及第一凸塊周圍的該第二黏著層，移除該臨時載體，以及在該半導體晶粒以及第二黏著層之上形成一互連結構。
在另一實施例中，本發明係一種製造一半導體裝置之方法，其係包括以下步驟：提供一載體，在該載體之上形成一第一互連結構，安裝一半導體晶粒至該載體，提供一可穿透的膜封裝材料層，在該半導體晶粒以及第一互連結構之上加壓該可穿透的膜封裝材料層以將該半導體晶粒以及第一互連結構嵌入在該可穿透的膜封裝材料層之內，移除該可穿透的膜封裝材料層的一第一部分以露出該第一互連結構而留下該半導體晶粒以及第一互連結構周圍的該可穿透的膜封裝材料層的一第二部分，移除該載體，以及在該半導體晶粒以及該可穿透的膜封裝材料層的第二部分之上形成一第二互連結構。
在另一實施例中，本發明係一種製造一半導體裝置之方法，其係包括以下步驟：提供一可穿透的膜封裝材料層，在一半導體晶粒以及第一互連結構之上加壓該可穿透的膜封裝材料層以將該半導體晶粒以及第一互連結構嵌入在該可穿透的膜封裝材料層之內，以及移除該可穿透的膜封裝材料層的一第一部分以露出該第一互連結構而留下該半導體晶粒以及第一互連結構周圍的該可穿透的膜封裝材料層的一第二部分。
在另一實施例中，本發明係一半導體裝置，其係包括一半導體晶粒以及設置在該半導體晶粒周圍的第一互連結構。一可穿透的膜封裝材料層係在該半導體晶粒以及第一互連結構之上被加壓，以將該半導體晶粒以及第一互連結構嵌入在該可穿透的膜封裝材料層之內。一第二互連結構係形成在該半導體晶粒以及可穿透的膜封裝材料層之上。
本發明係在以下參考該些圖式的說明中，以一或多個實施例來加以描述，其中相同的元件符號係代表相同或類似的元件。儘管本發明係以用於達成本發明之目的之最佳模式來加以描述，但熟習此項技術者將會體認到的是，其係欲涵蓋可內含在藉由所附的申請專利範圍及其由以下的揭露內容及圖式所支持的等同項所界定的本發明的精神與範疇內的替換物、修改以及等同物。
半導體裝置一般是利用兩個複雜的製程：前端製造及後端製造來加以製造。前端製造係牽涉到複數個晶粒在一半導體晶圓的表面上的形成。在該晶圓上的每個晶粒係包含電連接以形成功能電路的主動及被動電氣構件。例如是電晶體及二極體的主動電氣構件係具有控制電流的流動之能力。例如是電容器、電感器、電阻器及變壓器的被動電氣構件係產生執行電路功能所必要的電壓及電流之間的一種關係。
被動及主動構件係藉由一系列的製程步驟而形成在半導體晶圓的表面之上，該些製程步驟包含摻雜、沉積、微影、蝕刻及平坦化。摻雜係藉由例如是離子植入或熱擴散的技術以將雜質帶入半導體材料中。該摻雜製程係修改主動元件中的半導體材料的導電度，其係轉換該半導體材料成為絕緣體、導體、或是響應於一電場或基極電流來動態地改變該半導體材料的導電度。電晶體係包含具有不同類型及程度的摻雜的區域，該些區域係以使得該電晶體在電場或基極電流的施加時能夠提升或限制電流的流動所必要的來加以配置。
主動及被動構件係藉由具有不同電氣特性的材料層來加以形成。該些層可藉由各種沉積技術來形成，該技術部分是由被沉積的材料類型來決定的。例如，薄膜沉積可能牽涉到化學氣相沉積(CVD)、物理氣相沉積(PVD)、電解的電鍍以及無電的電鍍製程。每個層一般是被圖案化，以形成主動構件、被動構件或是構件間的電連接的部分。
該些層可利用微影而被圖案化，微影係牽涉到光敏材料(例如，光阻)在待被圖案化的層之上的沉積。一圖案係利用光從一光罩轉印至光阻。該光阻圖案遭受到光的部分係利用一溶劑來移除，以露出下面待被圖案化的層的部分。該光阻的剩餘部分係被移除，留下一圖案化的層。或者是，某些類型的材料係藉由利用例如是無電的電鍍及電解的電鍍的技術來直接將該材料沉積到該些區域或是沉積到由一先前的沉積/蝕刻製程所形成的空孔中而被圖案化。
在一現有的圖案之上沉積一材料薄膜可能會擴大下面的圖案並且產生一非均勻平坦的表面。一均勻平坦的表面是產生較小且更緊密聚集的主動及被動構件所需的。平坦化可被利用來從晶圓的表面移除材料並且產生一均勻平坦的表面。平坦化係牽涉到利用一拋光墊來拋光晶圓的表面。一研磨劑材料及腐蝕性化學品係在拋光期間被加到晶圓的表面。該研磨劑的機械性作用以及該化學品的腐蝕性作用的組合係移除任何不規則的表面構形，產生一均勻平坦的表面。
後端製造係指切割或單粒化完成的晶圓成為個別的晶粒並且接著為了結構的支撐及環境的隔離來封裝該晶粒。為了單粒化晶粒，晶圓係沿著該晶圓的非功能區域(稱為切割道或劃線)來被劃線且截斷。該晶圓係利用一雷射切割工具或鋸刀而被單粒化。在單粒化之後，該個別的晶粒係被安裝到一封裝基板，該封裝基板係包含用於和其它系統構件互連的接腳或接觸墊。形成在半導體晶粒之上的接觸墊係接著連接至該封裝內的接觸墊。該些電連接可以利用銲料凸塊、柱形凸塊、導電膏、或是引線接合來做成。一封裝材料(encapsulant)或是其它模製材料係沉積在該封裝之上，以提供實體支撐及電氣隔離。該完成的封裝係接著被插入一電氣系統中，並且使得該半導體裝置的功能為可供其它系統構件利用的。
圖1係描繪具有複數個安裝於其表面上之半導體封裝的晶片載體基板或印刷電路板(PCB)52之電子裝置50。視應用而定，電子裝置50可具有一種類型之半導體封裝或多種類型之半導體封裝。不同類型之半導體封裝係為了說明之目的而展示於圖1中。
電子裝置50可以是一使用該些半導體封裝以執行一或多種電功能之獨立的系統。或者，電子裝置50可以是一較大系統之子構件。舉例而言，電子裝置50可以是行動電話、個人數位助理(PDA)、數位視訊攝影機(DVC)、或是其它電子通訊裝置的一部份。或者是，電子裝置50可以是一可插入電腦中之顯示卡、網路介面卡或其它信號處理卡。該半導體封裝可包括微處理器、記憶體、特殊應用積體電路(ASIC)、邏輯電路、類比電路、RF電路、離散裝置或其它半導體晶粒或電氣構件。小型化及重量減輕是這些產品能夠被市場接受所不可少的。在半導體裝置間的距離必須縮短以達到更高的密度。
在圖1中，PCB 52係提供一般的基板以供安裝在該PCB上之半導體封裝的結構支撐及電氣互連。導電的信號線路54係利用蒸鍍、電解的電鍍、無電的電鍍、網版印刷、或其它適合的金屬沉積製程而被形成在PCB 52的一表面之上或是在層內。信號線路54係提供在半導體封裝、安裝的構件、以及其它外部的系統構件的每一個之間的電通訊。線路54亦提供電源及接地連接給每個半導體封裝。
在某些實施例中，一半導體裝置具有兩個封裝層級。第一層級的封裝是一種用於將半導體晶粒機械及電氣地附接至一中間載體的技術。第二層級的封裝係牽涉到將該中間載體機械及電氣地附接至PCB。在其它實施例中，一半導體裝置可以只有該第一層級的封裝，其中晶粒是直接機械及電氣地安裝到PCB上。
為了說明之目的，包含引線接合封裝56及覆晶58之數種類型的第一層級的封裝係被展示在PCB 52上。此外，包含球狀柵格陣列(BGA)60、凸塊晶片載體(BCC)62、雙排型封裝(DIP)64、平台柵格陣列(LGA)66、多晶片模組(MCM)68、四邊扁平無引腳封裝(QFN)70及四邊扁平封裝72之數種類型的第二層級的封裝係被展示安裝在PCB 52上。視系統需求而定，以第一及第二層級的封裝類型的任意組合來組態的半導體封裝的任何組合及其它電子構件可連接至PCB 52。在某些實施例中，電子裝置50包含單一附接的半導體封裝，而其它實施例需要多個互連的封裝。藉由在單一基板之上組合一或多個半導體封裝，製造商可將預製的構件納入電子裝置及系統中。由於半導體封裝包括複雜的功能，因此可使用較便宜構件及流線化製程來製造電子裝置。所產生的裝置不太可能發生故障且製造費用較低，從而降低消費者成本。
圖2a-2c係展示範例的半導體封裝。圖2a係描繪安裝在PCB 52上的DIP 64之進一步的細節。半導體晶粒74係包括一含有類比或數位電路的主動區域，該些類比或數位電路係被實施為形成在晶粒內之主動元件、被動元件、導電層及介電層並且根據該晶粒的電設計而電互連。例如，該電路可包含形成在半導體晶粒74的主動區域內之一或多個電晶體、二極體、電感器、電容器、電阻器、以及其它電路元件。接觸墊76是一或多層的導電材料，例如鋁(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)或銀(Ag)，並且電連接至形成在半導體晶粒74內之電路元件。在DIP 64的組裝期間，半導體晶粒74係利用一金矽共晶層或例如是熱環氧樹脂的黏著材料而被安裝到一中間載體78。封裝主體係包含一種例如是聚合物或陶瓷的絕緣封裝材料。導線80及引線接合82係在半導體晶粒74及PCB 52之間提供電互連。封裝材料84係為了環境保護而沉積在該封裝之上以防止濕氣及微粒進入該封裝且污染晶粒74或引線接合82。
圖2b係描繪安裝在PCB 52上之BCC 62的進一步細節。半導體晶粒88係利用一種底膠填充(underfill)或是環氧樹脂黏著材料92而被安裝在載體90之上。引線接合94係在接觸墊96及98之間提供第一層級的封裝互連。模製化合物或封裝材料100係沉積在半導體晶粒88及引線接合94之上以提供實體支撐及電氣隔離給該裝置。接觸墊102係利用一例如是電解的電鍍或無電的電鍍之合適的金屬沉積製程而被形成在PCB 52的一表面之上以避免氧化。接觸墊102係電連接至PCB 52中的一或多個導電信號線路54。凸塊104係形成在BCC 62的接觸墊98以及PCB 52的接觸墊102之間。
在圖2c中，半導體晶粒58係以覆晶型第一層級的封裝方式面向下安裝到中間載體106。半導體晶粒58的主動區域108係包含類比或數位電路，該些類比或數位電路係被實施為根據該晶粒的電設計所形成的主動元件、被動元件、導電層及介電層。例如，該電路可包含一或多個電晶體、二極體、電感器、電容器、電阻器以及主動區域108內之其它電路元件。半導體晶粒58係透過凸塊110電氣及機械地連接至載體106。
BGA 60係以BGA型第二層級的封裝方式利用凸塊112電氣及機械地連接至PCB 52。半導體晶粒58係透過凸塊110、信號線114及凸塊112電連接至PCB 52中的導電信號線路54。一種模製化合物或封裝材料116係沉積在半導體晶粒58及載體106之上以提供實體支撐及電氣隔離給該裝置。該覆晶半導體裝置係提供從半導體晶粒58上的主動元件到PCB 52上的導電跡線之短的導電路徑，以便縮短信號傳遞距離、降低電容以及改善整體電路效能。在另一實施例中，半導體晶粒58可在無中間載體106的情況下，利用覆晶型第一層級的封裝直接機械及電連接至PCB 52。
圖3a係展示一具有一種例如是矽、鍺、砷化鎵、磷化銦或矽碳化物的主體基板材料122以供結構支撐的半導體晶圓120。如上所述，複數個半導體晶粒或構件124係形成在晶圓120上且藉由切割道126分開。
圖3b係展示半導體晶圓120的一部份的橫截面圖。每個半導體晶粒124係具有一背表面128以及一包含類比或數位電路的主動表面130，該類比或數位電路被實施為形成在該晶粒內且根據該晶粒的電設計及功能電互連的主動元件、被動元件、導電層以及介電層。例如，該電路可包含一或多個電晶體、二極體以及其它形成在主動表面130內之電路元件以實施類比電路或數位電路，例如數位信號處理器(DSP)、ASIC、記憶體或是其它信號處理電路。半導體晶粒124亦可包含整合被動裝置(IPD)，例如電感器、電容器及電阻器，以供RF信號處理使用。在一實施例中，半導體晶粒124是一覆晶類型的半導體晶粒。
一導電層132係利用PVD、CVD、電解的電鍍、無電的電鍍製程、或是其它合適的金屬沉積製程而形成在主動表面130之上。導電層132可以是一或多層的Al、Cu、Sn、Ni、Au、Ag、或是其它合適的導電材料。導電層132係運作為接觸墊，該些接觸墊係電連接至主動表面130上的電路。
在圖3c中，半導體晶圓120係利用鋸刀或雷射切割工具134透過切割道126而被單粒化，以將該晶圓分開成為個別的半導體晶粒124。
圖4a-4l係相關於圖1及2a-2c來描繪一種在一半導體晶粒以及互連結構周圍形成一可穿透的膜封裝材料層的製程。圖4a係展示一基板或載體140，其係包含臨時或犧牲基底材料，例如，矽、聚合物、鈹氧化物或其它適當的低成本剛性材料，以用於結構的支撐。一介面層或雙面帶142係形成在載體140之上以作為一臨時黏著的黏合膜或蝕刻停止層。
在圖4b中，一導電的凸塊材料係利用一蒸鍍、電解的電鍍、無電的電鍍、球式滴落(ball drop)或網版印刷製程而沉積在載體140及介面層142之上。該凸塊材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料、及其組合，其具有一選配的助熔(flux)溶劑。例如，該凸塊材料可以是共晶Sn/Pb、高鉛的焊料或是無鉛的焊料。在一實施例中，該凸塊材料係藉由加熱該材料超過其熔點來進行回焊以形成球或凸塊144。凸塊144係被設置在指定用於稍後安裝的半導體晶粒的安裝位置146的周圍。凸塊144係代表一種類型的z方向垂直的互連結構，其可以形成在載體140之上。該互連結構亦可以使用柱形凸塊、微凸塊或是其它的電互連。
在圖4c-4d中，半導體晶粒124係從圖3a-3c利用拾放動作並且以主動表面130朝向載體140及介面層142而被安裝到凸塊144之間的位置146。在一實施例中，半導體晶粒124係具有450微米(μm)的厚度。凸塊144係具有大於450μm的高度以延伸超出半導體晶粒124的背表面128。圖4e是形成在半導體晶粒124周圍的凸塊144的俯視圖。凸塊144可以在安裝半導體晶粒124到載體140之後才形成。
圖4f係展示一利用導電柱148形成在載體140之上且在半導體晶粒124周圍的替代實施例。導電柱148可以在安裝半導體晶粒124之前或是之後，藉由沉積一光阻層在載體140之上並且接著利用微影來圖案化該光阻以在該柱位置中形成貫孔來加以形成。該些貫孔係利用電解的電鍍、無電的電鍍製程、或是其它適當的金屬沉積製程而被填入Al、Cu、Sn、Ni、Au、Ag、Ti、鎢(W)、多晶矽、或是其它適當的導電材料。該光阻係被移除，而留下z方向垂直的導電柱148。導電柱148係延伸超出半導體晶粒124的背表面128。
圖4g係展示一可穿透的膜封裝材料層150，其係包含基底層152、紫外線(UV)B-階段膜黏著層154、以及熱凝黏著膜層156。在一實施例中，基底層152係包含聚酯，並且UV B-階段膜黏著層154係包含丙烯酸聚合物。該熱凝黏著膜層156係具有大約20-45ppm/K之低的熱膨脹係數(CTE)以及大約1000-34000MPa之高的模數(modulus)，例如可見於Denko的AS-0001、AS-0016以及AS-0036黏著膜。該可穿透的膜封裝材料層150係被加熱到70℃以使得黏著層154及156為軟的、有延展性的且為柔性的。
該可穿透的膜封裝材料層150係被設置在半導體晶粒124、凸塊144及載體140之上。該可穿透的膜封裝材料層150係以一力F而被壓到半導體晶粒124及凸塊144之上，以使得該半導體晶粒及凸塊穿透到黏著層154及156中。在黏著層156來到接近或接觸介面層142的一頂表面之後，該力F係被移去。圖4h係展示半導體晶粒124及凸塊144被嵌入到黏著層154及156之中。凸塊144可接觸、或是可不接觸到基底層152。該可穿透的膜封裝材料層150係被固化以硬化黏著層156並且穩固地保持住半導體晶粒124及凸塊144。
在圖4i中，基底層152及UV B-階段膜黏著層154係藉由在箭頭158的方向上的機械式剝離或機械式剝除而被移除。該B-階段膜黏著層154係在UV照射下分離，而黏著層156係留在半導體晶粒124及凸塊144的周圍，以作為一用於該半導體裝置的結構支撐以及免於接觸到外部的元素及污染物的環境保護之封裝層。凸塊144係從黏著層156露出以用於外部的電互連。基底層152及B-階段膜黏著層154亦可藉由化學品蝕刻、CMP、機械式研磨、熱烘烤、UV光、雷射掃描、或是濕式剝除而被移除。
在圖4j中，載體140及介面層142係藉由化學品蝕刻、機械式剝離、CMP、機械式研磨、熱烘烤、UV光、雷射掃描、或是濕式剝除而被移除，以露出主動表面130及凸塊144。
在圖4k中，一底側積層的互連結構160係形成在半導體晶粒124的主動表面130以及黏著層156之上。該積層的互連結構160係包含一導電層162，該導電層162係利用一例如是濺鍍、電解的電鍍以及無電的電鍍之圖案化及金屬沉積製程來加以形成。導電層162可以是一或多個層的Al、Cu、Sn、Ni、Au、Ag、或是其它適當的導電材料。導電層162的一部分係電連接至凸塊144。導電層162的另一部分係電連接至半導體晶粒124的接觸墊132。導電層162的其它部分可以根據該半導體裝置的設計及功能而為電氣共用的或是電氣隔離的。
該積層的互連結構160進一步包含一形成在導電層162之間的絕緣或保護層164，以用於電氣隔離。該絕緣層164係包含一或多個層的二氧化矽(SiO2)、矽氮化物(Si3N4)、氮氧化矽(SiON)、五氧化二鉭(Ta2O5)、鋁氧化物(Al2O3)、或是其它具有類似的絕緣及結構性質的材料。該絕緣層164係利用PVD、CVD、印刷、旋轉塗覆、噴霧塗覆、燒結或熱氧化來加以形成。絕緣層164的一部分係藉由一蝕刻製程而被移除以露出導電層162。
在圖41中，一導電的凸塊材料係利用一蒸鍍、電解的電鍍、無電的電鍍、球式滴落或網版印刷製程而沉積在積層的互連結構160之上並且電連接至該露出的導電層162。該凸塊材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料、及其組合，其具有一選配的助熔溶劑。例如，該凸塊材料可以是共晶Sn/Pb、高鉛的焊料或是無鉛的焊料。該凸塊材料係利用一適當的連結或接合製程而被接合到導電層162。在一實施例中，該凸塊材料係藉由加熱該材料超過其熔點來進行回焊以形成球或凸塊166。在某些應用中，凸塊166係二次進行回焊以改善至導電層162的電接觸。該些凸塊亦可以壓縮接合到導電層162。凸塊166係代表一種類型的可形成在導電層162之上的互連結構。該互連結構亦可以使用接合線、柱形凸塊、微凸塊或是其它的電互連。
半導體晶粒124係利用鋸刀或雷射切割工具168而被單粒化為個別的Fo-WLCSP 170。圖5係展示在單粒化之後的Fo-WLCSP 170。半導體晶粒124係電連接至積層的互連結構160以及凸塊144及166。該具有黏著層154及156之可穿透的膜封裝材料層150被加壓到半導體晶粒124及凸塊144之上，此係降低橫向及垂直的晶粒位移。在移除基底層152及UV B-階段膜黏著層154之後，黏著層156係留在半導體晶粒周圍124及凸塊144的周圍，以作為一用於該半導體裝置的結構支撐以及免於接觸到外部的元素及污染物的環境保護之封裝層。藉由將黏著層156加壓到半導體晶粒124以及凸塊144之上以作為該封裝層，因此沒有如同在習知技術中所見的造成晶粒位移的封裝材料之注入。
圖6係展示類似於圖5的WLCSP 172的一實施例，其中黏著層156係與半導體晶粒124的背表面128共平面。
圖7係展示類似於圖5的WLCSP 174的一實施例，其中一導電層或重新分配層(RDL)176係利用一例如是濺鍍、電解的電鍍以及無電的電鍍之圖案化及金屬沉積製程而形成在黏著層156之上。導電層176可以是一或多個層的Al、Cu、Sn、Ni、Au、Ag、或是其它適當的導電材料。熱凝黏著層156的固化製程係使得高溫金屬沉積成為可能的。導電層176的一部分係電連接至凸塊144。導電層176的其它部分可以根據該半導體裝置的設計及功能而為電氣共用的或是電氣隔離的。
圖8係展示複數個堆疊的Fo-WLCSP 170，其係藉由凸塊144、積層的互連結構160以及RDL 176來電連接。在凸塊144延伸超出黏著層156的情形下，至相鄰的Fo-WLCSP 170的垂直電互連會有更大的接觸表面積及更高的接合可靠度。
圖9係展示類似於圖5的WLCSP 180的一實施例，其中凸塊182係形成在接觸墊132之上。接觸墊184係在安裝半導體晶粒124之前的例如是在圖4b的製程步驟期間形成在介面層142之上。類似於圖4c，具有凸塊182的半導體晶粒124係被安裝到接觸墊184。
儘管本發明的一或多個實施例已經詳細地描述，本領域技術人員將會體認到可在不脫離本發明如以下申請專利範圍中闡述的範疇下，對那些實施例進行修改及改編。
50．．．電子裝置
52．．．晶片載體基板(印刷電路板)
54．．．信號線路
60．．．球狀柵格陣列(BGA)
62．．．凸塊晶片載體(BCC)
64．．．雙排型封裝(DIP)
66．．．平台柵格陣列(LGA)
68．．．多晶片模組(MCM)
70．．．四邊扁平無引腳封裝(QFN)
72．．．四邊扁平封裝
74．．．半導體晶粒
76．．．接觸墊
78．．．中間載體
80．．．導線
82．．．引線接合
84．．．封裝材料
88．．．半導體晶粒
90．．．載體
92．．．底膠填充材料(環氧樹脂黏著材料)
94．．．引線接合
96、98．．．接觸墊
100．．．模製化合物(封裝材料)
102．．．接觸墊
104．．．凸塊
106．．．中間載體
108．．．主動區域
110、112．．．凸塊
114．．．信號線
116．．．模製化合物(封裝材料)
120．．．半導體晶圓
122．．．主體基板材料
124．．．半導體晶粒(構件)
126．．．切割道
128．．．背表面
130．．．主動表面
132．．．導電層
134．．．鋸刀(雷射切割工具)
140．．．基板(載體)
142．．．介面層(雙面帶)
144．．．凸塊
146．．．安裝位置
148．．．導電柱
150．．．可穿透的膜封裝材料層
152．．．基底層
154．．．紫外線(UV)B-階段膜黏著層
156．．．熱凝黏著膜層
158．．．箭頭
160．．．積層的互連結構
162．．．導電層
164．．．絕緣(保護)層
166．．．球(凸塊)
168．．．鋸刀(雷射切割工具)
170．．．Fo-WLCSP
172．．．WLCSP
174．．．WLCSP
176．．．導電層(重新分配層)
180．．．WLCSP
182．．．凸塊
184．．．接觸墊
圖1係描繪一具有不同類型的封裝安裝到其表面的PCB；
圖2a-2c係描繪安裝到該PCB之代表性的半導體封裝的進一步細節；
圖3a-3c係描繪一具有複數個藉由切割道分開的半導體晶粒之半導體晶圓；
圖4a-4l係描繪一種在一半導體晶粒及互連結構周圍形成一可穿透的膜封裝材料層之製程；
圖5係描繪具有形成在該半導體晶粒及互連結構周圍之可穿透的膜封裝材料層之Fo-WLCSP；
圖6係描繪與半導體晶粒共平面的可穿透的膜封裝材料層；
圖7係描繪一形成在該可穿透的膜封裝材料層之上的RDL；
圖8係描繪堆疊的Fo-WLCSP，每個Fo-WLCSP係具有形成在該半導體晶粒以及互連結構周圍之可穿透的膜封裝材料層；以及
圖9係描繪形成在半導體晶粒上的接觸墊之上的凸塊。
124．．．半導體晶粒(構件)
128．．．背表面
130．．．主動表面
132．．．導電層
144．．．凸塊
156．．．熱凝黏著膜層
160．．．積層的互連結構
162．．．導電層
164．．．絕緣(保護)層
166．．．球(凸塊)
170．．．Fo-WLCSP

Claims (15)

  1. 一種製造一半導體裝置之方法，其係包括：提供一半導體晶粒；形成一第一互聯結構鄰近於該半導體晶粒；在該半導體晶粒以及第一互連結構之上加壓一可穿透的膜封裝材料層，以將該半導體晶粒以及第一互連結構嵌入在該可穿透的膜封裝材料層之內；移除該可穿透的膜封裝材料層的一第一部分以露出該第一互連結構，而留下該半導體晶粒以及第一互連結構周圍的該可穿透的膜封裝材料層的一第二部分；以及在該半導體晶粒以及該可穿透的膜封裝材料層的第二部分之上形成一第二互連結構。
  2. 如申請專利範圍第1項之方法，其中該可穿透的膜封裝材料層係包含一基底層、第一黏著層以及第二黏著層。
  3. 如申請專利範圍第1項之方法，其進一步包含固化該可穿透的膜封裝材料層。
  4. 如申請專利範圍第1項之方法，其進一步包含在電連接至該第一互連結構的該可穿透的膜封裝材料層的該第二部分之上形成一導電層。
  5. 如申請專利範圍第1項之方法，其中該第一互連結構係包含凸塊或導電柱。
  6. 一種製造一半導體裝置之方法，其係包括：提供一可穿透的膜封裝材料層；在一半導體晶粒以及第一互連結構之上加壓該可穿透 的膜封裝材料層，以將該半導體晶粒以及第一互連結構嵌入在該可穿透的膜封裝材料層之內；以及移除該可穿透的膜封裝材料層的一第一部分以露出該第一互連結構，而留下該半導體晶粒以及第一互連結構周圍的該可穿透的膜封裝材料層的一第二部分。
  7. 如申請專利範圍第6項之方法，其進一步包含在該半導體晶粒以及該可穿透的膜封裝材料層的第二部分之上形成一第二互連結構。
  8. 如申請專利範圍第6項之方法，其中該可穿透的膜封裝材料層係包含一基底層、第一黏著層以及第二黏著層。
  9. 如申請專利範圍第6項之方法，其進一步包含固化該可穿透的膜封裝材料層。
  10. 如申請專利範圍第6項之方法，其中該第一互連結構係包含凸塊或導電柱。
  11. 如申請專利範圍第6項之方法，其進一步包含形成一導電層於該可穿透的膜封裝材料層之上而電性地連接至該第一互連結構。
  12. 一種半導體裝置，其係包括：一半導體晶粒；一設置在該半導體晶粒周圍的第一互連結構；一可穿透的膜封裝材料層，其係在該半導體晶粒以及第一互連結構之上被加壓，以將該半導體晶粒以及第一互連結構嵌入在該可穿透的膜封裝材料層之內；以及一第二互連結構，其係形成在該半導體晶粒以及可穿 透的膜封裝材料層之上。
  13. 如申請專利範圍第12項之半導體裝置，其中該第一互連結構係從該可穿透的膜封裝材料層露出。
  14. 如申請專利範圍第12項之半導體裝置，其進一步包含一導電層，該導電層係形成在電連接至該第一互連結構的該可穿透的膜封裝材料層之上。
  15. 如申請專利範圍第12項之半導體裝置，其中該第一互連結構係包含凸塊或導電柱。
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KR20110124993A (ko) * 2010-05-12 2011-11-18 삼성전자주식회사 반도체 칩 및 이를 포함하는 반도체 패키지 및 반도체 칩의 제조 방법
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US8633598B1 (en) * 2011-09-20 2014-01-21 Amkor Technology, Inc. Underfill contacting stacking balls package fabrication method and structure
US10622310B2 (en) 2012-09-26 2020-04-14 Ping-Jung Yang Method for fabricating glass substrate package
US9287204B2 (en) * 2012-12-20 2016-03-15 Stats Chippac, Ltd. Semiconductor device and method of bonding semiconductor die to substrate in reconstituted wafer form
US10269619B2 (en) 2013-03-15 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level chip scale packaging intermediate structure apparatus and method
CN104051399B (zh) 2013-03-15 2018-06-08 台湾积体电路制造股份有限公司 晶圆级芯片尺寸封装中间结构装置和方法
US9419156B2 (en) 2013-08-30 2016-08-16 Taiwan Semiconductor Manufacturing Co., Ltd. Package and method for integration of heterogeneous integrated circuits
JP2015076503A (ja) * 2013-10-09 2015-04-20 日東電工株式会社 半導体装置の製造方法
US9129981B2 (en) * 2013-11-26 2015-09-08 Freescale Semiconductor Inc. Methods for the production of microelectronic packages having radiofrequency stand-off layers
US9362161B2 (en) 2014-03-20 2016-06-07 Stats Chippac, Ltd. Semiconductor device and method of forming 3D dual side die embedded build-up semiconductor package
CN104064557B (zh) * 2014-06-25 2017-03-29 中国科学院微电子研究所 一种芯片背面裸露的重构晶圆结构及制造方法
CN104103633A (zh) * 2014-06-25 2014-10-15 中国科学院微电子研究所 一种封装高度可控的重构晶圆结构及制造方法
CN104241216A (zh) * 2014-06-25 2014-12-24 中国科学院微电子研究所 一种封装高度可控的扇出型封装结构及制造方法
CN104241217A (zh) * 2014-06-25 2014-12-24 中国科学院微电子研究所 一种芯片背面裸露的扇出型封装结构及制造方法
CN104064531A (zh) * 2014-06-25 2014-09-24 中国科学院微电子研究所 一种焊球控制封装高度的器件封装结构及制造方法
US9390993B2 (en) * 2014-08-15 2016-07-12 Broadcom Corporation Semiconductor border protection sealant
CN104241219B (zh) 2014-08-26 2019-06-21 日月光半导体制造股份有限公司 元件嵌入式封装结构和其制造方法
TWI599007B (zh) * 2014-09-03 2017-09-11 矽品精密工業股份有限公司 電子單體及其製法
TWI548043B (zh) * 2014-11-17 2016-09-01 矽品精密工業股份有限公司 封裝結構及其製法
CN104658933A (zh) * 2014-12-30 2015-05-27 华天科技（西安）有限公司 一种运用贴膜工艺的pop封装结构及其制备方法
CN105810599A (zh) * 2014-12-30 2016-07-27 深南电路有限公司 埋入指纹识别芯片的基板及其加工方法
TWI601252B (zh) * 2015-05-22 2017-10-01 南茂科技股份有限公司 封裝結構的製作方法以及使用其所製得之封裝結構
US9728498B2 (en) * 2015-06-30 2017-08-08 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure
CN105185717A (zh) * 2015-08-12 2015-12-23 中芯长电半导体（江阴）有限公司 晶圆级芯片封装方法
EP3449502B1 (en) 2016-04-26 2021-06-30 Linear Technology LLC Mechanically-compliant and electrically and thermally conductive leadframes for component-on-package circuits
CN106098644A (zh) * 2016-08-11 2016-11-09 华天科技（西安）有限公司 一种daf膜与垫块结合的芯片封装结构及其制造方法
IT201800002903A1 (it) * 2018-02-21 2019-08-21 St Microelectronics Srl Procedimento per fabbricare dispositivi a semiconduttore e dispositivo a semiconduttore corrispondente
US10497635B2 (en) 2018-03-27 2019-12-03 Linear Technology Holding Llc Stacked circuit package with molded base having laser drilled openings for upper package
CN109166807A (zh) * 2018-07-24 2019-01-08 江阴芯智联电子科技有限公司 新型扇出型封装结构的制造方法
US11410977B2 (en) 2018-11-13 2022-08-09 Analog Devices International Unlimited Company Electronic module for high power applications
CN112582281B (zh) * 2019-09-29 2023-08-25 矽磐微电子(重庆)有限公司 半导体封装方法及半导体封装结构
US12021052B2 (en) * 2020-01-29 2024-06-25 Stmicroelectronics S.R.L. Method of manufacturing semiconductor products, semiconductor product, device and testing method
US11844178B2 (en) 2020-06-02 2023-12-12 Analog Devices International Unlimited Company Electronic component

Family Cites Families (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200302685A (en) 2002-01-23 2003-08-01 Matsushita Electric Ind Co Ltd Circuit component built-in module and method of manufacturing the same
SG137651A1 (en) * 2003-03-14 2007-12-28 Micron Technology Inc Microelectronic devices and methods for packaging microelectronic devices
JP4776188B2 (ja) 2004-08-03 2011-09-21 古河電気工業株式会社 半導体装置製造方法およびウエハ加工用テープ
US7187068B2 (en) * 2004-08-11 2007-03-06 Intel Corporation Methods and apparatuses for providing stacked-die devices
US20060275952A1 (en) 2005-06-07 2006-12-07 General Electric Company Method for making electronic devices
US20070141751A1 (en) * 2005-12-16 2007-06-21 Mistry Addi B Stackable molded packages and methods of making the same
US7550680B2 (en) * 2006-06-14 2009-06-23 Stats Chippac Ltd. Package-on-package system
DE102006037538B4 (de) * 2006-08-10 2016-03-10 Infineon Technologies Ag Elektronisches Bauteil, elektronischer Bauteilstapel und Verfahren zu deren Herstellung sowie Verwendung einer Kügelchenplatziermaschine zur Durchführung eines Verfahrens zum Herstellen eines elektronischen Bauteils bzw. Bauteilstapels
WO2008035658A1 (fr) 2006-09-22 2008-03-27 Hitachi Chemical Company, Ltd. Procédé de fabrication de guide de lumière
JP5068990B2 (ja) * 2006-12-26 2012-11-07 新光電気工業株式会社 電子部品内蔵基板
TWI335070B (en) * 2007-03-23 2010-12-21 Advanced Semiconductor Eng Semiconductor package and the method of making the same
US8039309B2 (en) * 2007-05-10 2011-10-18 Texas Instruments Incorporated Systems and methods for post-circuitization assembly
US7944034B2 (en) * 2007-06-22 2011-05-17 Texas Instruments Incorporated Array molded package-on-package having redistribution lines
US7619901B2 (en) * 2007-06-25 2009-11-17 Epic Technologies, Inc. Integrated structures and fabrication methods thereof implementing a cell phone or other electronic system
JP5012896B2 (ja) * 2007-06-26 2012-08-29 株式会社村田製作所 部品内蔵基板の製造方法
US8829663B2 (en) * 2007-07-02 2014-09-09 Infineon Technologies Ag Stackable semiconductor package with encapsulant and electrically conductive feed-through
US7923846B2 (en) * 2007-11-16 2011-04-12 Stats Chippac Ltd. Integrated circuit package-in-package system with wire-in-film encapsulant
US8390117B2 (en) * 2007-12-11 2013-03-05 Panasonic Corporation Semiconductor device and method of manufacturing the same
US8120186B2 (en) 2008-02-15 2012-02-21 Qimonda Ag Integrated circuit and method
US8138590B2 (en) 2008-06-20 2012-03-20 Stats Chippac Ltd. Integrated circuit package system with wire-in-film encapsulation
TWI473553B (zh) * 2008-07-03 2015-02-11 Advanced Semiconductor Eng 晶片封裝結構
JP4602450B2 (ja) * 2008-12-02 2010-12-22 日東電工株式会社 半導体装置製造用フィルム及びその製造方法
US7993941B2 (en) * 2008-12-05 2011-08-09 Stats Chippac, Ltd. Semiconductor package and method of forming Z-direction conductive posts embedded in structurally protective encapsulant
US7642128B1 (en) * 2008-12-12 2010-01-05 Stats Chippac, Ltd. Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
JP5330065B2 (ja) * 2009-04-13 2013-10-30 新光電気工業株式会社 電子装置及びその製造方法
US7923304B2 (en) 2009-09-10 2011-04-12 Stats Chippac Ltd. Integrated circuit packaging system with conductive pillars and method of manufacture thereof
JP5425584B2 (ja) * 2009-10-15 2014-02-26 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US8592973B2 (en) * 2009-10-16 2013-11-26 Stats Chippac Ltd. Integrated circuit packaging system with package-on-package stacking and method of manufacture thereof
US8404518B2 (en) 2009-12-13 2013-03-26 Stats Chippac Ltd. Integrated circuit packaging system with package stacking and method of manufacture thereof
US8536462B1 (en) * 2010-01-22 2013-09-17 Amkor Technology, Inc. Flex circuit package and method
US8299595B2 (en) * 2010-03-18 2012-10-30 Stats Chippac Ltd. Integrated circuit package system with package stacking and method of manufacture thereof
US8105872B2 (en) 2010-06-02 2012-01-31 Stats Chippac, Ltd. Semiconductor device and method of forming prefabricated EMI shielding frame with cavities containing penetrable material over semiconductor die
TWI451539B (zh) * 2010-08-05 2014-09-01 Advanced Semiconductor Eng 半導體封裝件及其製造方法
US8097490B1 (en) * 2010-08-27 2012-01-17 Stats Chippac, Ltd. Semiconductor device and method of forming stepped interconnect layer for stacked semiconductor die
US8378477B2 (en) * 2010-09-14 2013-02-19 Stats Chippac Ltd. Integrated circuit packaging system with film encapsulation and method of manufacture thereof
US8409923B2 (en) * 2011-06-15 2013-04-02 Stats Chippac Ltd. Integrated circuit packaging system with underfill and method of manufacture thereof
US8546932B1 (en) * 2012-08-15 2013-10-01 Apple Inc. Thin substrate PoP structure
US9030010B2 (en) * 2012-09-20 2015-05-12 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging devices and methods
US9165876B2 (en) * 2013-03-11 2015-10-20 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package structure and methods for forming the same

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CN102456584A (zh) 2012-05-16
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