CN102569097A - 形成通过封装剂之上的绝缘层的开口供互连结构的增强粘合性的半导体器件和方法 - Google Patents

形成通过封装剂之上的绝缘层的开口供互连结构的增强粘合性的半导体器件和方法 Download PDF

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CN102569097A
CN102569097A CN201110429755XA CN201110429755A CN102569097A CN 102569097 A CN102569097 A CN 102569097A CN 201110429755X A CN201110429755X A CN 201110429755XA CN 201110429755 A CN201110429755 A CN 201110429755A CN 102569097 A CN102569097 A CN 102569097A
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insulating barrier
encapsulants
conductive layer
semiconductor chip
semiconductor
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CN102569097B (zh
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林耀剑
陈康
方建敏
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Stats Chippac Pte Ltd
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Stats Chippac Pte Ltd
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Abstract

半导体器件具有安装到载体的半导体小片。封装剂沉积在半导体小片和载体之上。去除载体。在半导体小片的占用面积外部的互连部位中的封装剂的一部分之上形成第一绝缘层。开口形成为通过互连部位中的第一绝缘层，以便露出封装剂。开口能够是环形的或是互连部位周围以及互连部位的中心区域中的通孔，以便露出封装剂。在第一绝缘层之上形成第一导电层，以便跟随第一绝缘层的轮廓。在第一导电层和外露封装剂之上形成第二导电层。在第二导电层之上形成第二绝缘层。在互连部位中的第二导电层之上形成凸块。

Description

形成通过封装剂之上的绝缘层的开口供互连结构的增强粘合性的半导体器件和方法
技术领域
一般来说，本发明涉及半导体器件，并且更具体来说，涉及形成通过封装剂之上的绝缘层的开口供互连结构的增强粘合性的半导体器件和方法。
背景技术
半导体器件常见于现代电子产品中。半导体器件在电子组件的数量和密度方面有所不同。分立半导体器件一般包含一种类型的电组件，例如发光二极管(LED)、小信号晶体管、电阻器、电容器、电感器和功率金属氧化物半导体场效应晶体管(MOSFET)。集成半导体器件通常包含数百至数百万电组件。集成半导体器件的示例包括微控制器、微处理器、电荷耦合器件(CCD)、太阳能电池和数字微镜器件(DMD)。
半导体器件执行大量功能，例如信号处理、高速计算、传送和接收电磁信号、控制电子装置、将太阳光变换成电力以及创建用于电视显示的可视投影。半导体器件见于娱乐、通信、功率转换、网络、计算机和消费者产品的领域。半导体器件还见于军事应用、航空、汽车、工业控制器和办公设备。
半导体器件利用半导体材料的电性质。半导体材料的原子结构允许其电导率通过施加电场或基极电流或者经由掺杂过程来操纵。掺杂将杂质引入半导体材料，以便操纵和控制半导体器件的导电率。
半导体器件包含有源和无源电结构。包括双极和场效应晶体管的有源结构控制电流的流动。通过改变掺杂水平和电场或基极电流的施加，晶体管促进或限制电流的流动。包括电阻器、电容器和电感器的无源结构创建执行各种电功能所需的电压与电流之间的关系。无源和有源结构经电连接以形成电路，该电路使半导体器件能够执行高速计算和其它有用功能。
半导体器件一般使用各潜在地涉及数百个步骤的两个复杂制造过程来制造，即前端制造和后端制造。前端制造涉及在半导体晶圆的表面上形成多个小片。各小片通常是相同的，并且包含通过电连接有源和无源组件所形成的电路。后端制造涉及从成品晶圆来切分(singulate)单独小片，并且封装小片以便提供结构支承和环境隔离。
半导体制造的一个目标是产生更小的半导体器件。更小的器件通常消耗更少功率，具有更高性能，并且能够更有效地生产。另外，更小的半导体器件具有更小占用面积，这对于较小最终产品是合乎需要的。较小小片尺寸可通过前端过程的改进来实现，从而产生具有更小、更高密度的有源和无源组件的小片。通过电互连和封装材料的改进，后端过程可产生具有较小占用面积的半导体器件封装。
在展开形式晶圆级芯片规模封装(Fo-WLCSP)中，半导体小片具有有源表面，有源表面包含作为小片中形成并且按照小片的电气设计和功能电互连的有源器件、无源器件、导电层和介电层所实现的模拟或数字电路。封装剂沉积在半导体小片之上。第一钝化层在封装剂之上形成。再分布层(RDL)在第一钝化层之上形成。第二钝化层在RDL和第一钝化层之上形成。第二钝化层的一部分通过蚀刻过程去除，以便露出RDL。在第二钝化层的被去除部分中的RDL之上形成凸块。
第一钝化层与封装剂之间的粘合性在许多Fo-WLCSP中趋向于较弱。第一钝化层与封装剂之间的弱粘合性在可靠性测试、如跌落测试期间极为明显。该器件可能被后可靠性检验(post-reliabilityinspection)否决，或者器件在现场可能出故障。
发明内容
存在降低半导体器件上的凸块结构的故障的需要。相应地，在一个实施例中，本发明是一种制作半导体器件的方法，包括下列步骤：提供载体，将半导体小片安装到载体，将封装剂沉积在半导体小片和载体之上，去除载体，在半导体小片的占用面积外部的互连部位中的封装剂的一部分之上形成第一绝缘层，去除互连部位中的第一绝缘层的一部分以露出封装剂，在第一绝缘层和外露封装剂之上形成第一导电层，在第一导电层之上形成第二绝缘层，以及在互连部位中的第一导电层之上形成凸块。
在另一个实施例中，本发明是一种制作半导体器件的方法，包括下列步骤：提供载体，将半导体小片安装到载体，将封装剂沉积在半导体小片和载体之上，去除载体，在半导体小片的占用面积外部的互连部位中的封装剂的一部分之上形成第一绝缘层，形成通过互连部位中的第一绝缘层的开口以露出封装剂，以及在第一绝缘层和外露封装剂之上形成第一导电层。
在另一个实施例中，本发明是一种制作半导体器件的方法，包括下列步骤：提供半导体小片，将封装剂沉积在半导体小片之上和周围，在半导体小片的占用面积外部的互连部位中的封装剂的一部分之上形成第一绝缘层，形成通过互连部位中的第一绝缘层的开口以露出封装剂，以及在第一绝缘层和外露封装剂之上形成第一导电层。
在另一个实施例中，本发明是一种半导体器件，包括半导体小片以及沉积在半导体小片之上和周围的封装剂。在半导体小片的占用面积外部的互连部位中的封装剂的一部分之上形成第一绝缘层。开口形成为通过互连部位中的第一绝缘层，以便露出封装剂。在第一绝缘层和外露封装剂之上形成第一导电层。
附图说明
图1示出在半导体晶圆之上形成的常规凸块结构；
图2a-2c示出具有安装到其表面的不同类型的封装的PCB；
图3a-3c示出安装到PCB的典型半导体封装的其它细节；
图4a-4k示出形成通过封装剂之上的绝缘层的开口供互连结构的增强粘合性的过程；以及
图5a-5e示出形成通过封装剂之上的绝缘层的开口供互连结构的增强粘合性的另一个过程。
具体实施方式
在以下描述中参照附图、通过一个或多个实施例来描述本发明，附图中，相似标号表示相同或相似元件。虽然按照用于实现本发明的目标的最佳模式来描述本发明，但是本领域的技术人员会理解，预计涵盖可包含在所附权利要求书所定义的本发明及以下公开和附图所支持的其等效方案的精神和范围之内的备选、修改和等效方案。
半导体器件一般使用两个复杂制造过程来制造：前端制造和后端制造。前端制造涉及在半导体晶圆的表面上形成多个小片。晶圆上的各小片包含有源和无源电组件，它们经电连接以形成功能电路。诸如晶体管和二极管之类的有源电组件具有控制电流的流动的能力。诸如电容器、电感器、电阻器和变压器之类的无源电组件创建执行电路功能所需的电压与电流之间的关系。
通过包括掺杂、沉积、光刻、蚀刻和平面化的一系列过程步骤，在半导体晶圆的表面之上形成无源和有源组件。掺杂通过诸如离子注入或热扩散之类的技术，将杂质引入半导体材料。掺杂过程修改有源器件中的半导体材料的电导率，从而将半导体材料变换为绝缘体、导电体，或者响应电场或基极电流而动态改变半导体材料导电率。晶体管包含根据需要所设置的可变类型和程度的掺杂的区域，以便在施加电场或基极电流时使晶体管能够促进或限制电流的流动。
有源和无源组件通过具有不同电性质的材料层来形成。能够通过部分由所沉积材料的类型所确定的各种沉积技术来形成层。例如，薄膜沉积可涉及化学气相沉积(CVD)、物理气相沉积(PVD)、电镀和非电解镀过程。一般对各层形成图案以形成有源组件、无源组件或者组件之间的电连接的部分。
能够使用光刻来对层形成图案，这涉及在将要形成图案的层之上沉积光敏材料、如光致抗蚀剂。使用光线将图案从光掩模转印到光致抗蚀剂。使用溶剂去除经受光线的光致抗蚀剂图案的部分，从而露出待形成图案的基础层的部分。去除光致抗蚀剂的其余部分，从而留下形成图案的层。备选地，通过使用诸如非电解镀和电镀之类的技术将材料直接沉积到前一个沉积/蚀刻过程所形成的区域或空隙(void)中，来对一些类型的材料形成图案。
将材料薄膜沉积在现有图案之上能够扩大基本图案并且创建非均匀平坦表面。需要均匀平坦表面以产生更小并且更密集封装的有源和无源组件。平面化能够用于从晶圆的表面去除材料，并且产生均匀平坦表面。平面化涉及采用抛光垫来抛光晶圆的表面。在抛光期间将研磨材料和腐蚀性化学品添加到晶圆的表面。研磨剂的机械作用和化学品的腐蚀作用的结合去除任何不规则拓扑，从而产生均匀平坦表面。
后端制造表示将成品晶圆切割或切分为单独小片，并且然后封装小片供结构支承和环境隔离。为了对小片进行切分，沿称作锯道(sawstreet)或锯痕(scribe)的晶圆的非功能区域来将晶圆划线和分离。使用激光切割工具或锯条来对晶圆进行切分。在切分之后，单独小片被安装到包括引脚或接触片供与其它系统组件互连的封装衬底。在半导体小片之上形成的接触片则连接到封装中的接触片。电连接能够采用焊料凸块、螺柱凸块(stud bump)、导电膏或丝焊来制作。封装剂或其它成型材料沉积在封装之上，以便提供物理支承和电绝缘。然后，将成品封装插入电气系统，并且使半导体器件的功能性为其它系统组件可用。
图1示出具有芯片承载衬底或印刷电路板(PCB)52的电子装置50，其中多个半导体封装安装在其表面上。电子装置50可根据应用而具有一种类型的半导体封装或者多种类型的半导体封装。为了便于说明，在图1中示出不同类型的半导体封装。
电子装置50可以是使用半导体封装来执行一个或多个电功能的独立系统。备选地，电子装置50可以是较大系统的子组件。例如，电子装置50可以是蜂窝电话、个人数字助理(PDA)、数字摄像机(DVC)或者其它电子通信装置的一部分。备选地，电子装置50能够是图形卡、网络接口卡或者能够插入计算机中的其它信号处理卡。半导体封装能够包括微处理器、存储器、专用集成电路(ASIC)、逻辑电路、模拟电路、RF电路、分立装置或者其它半导体小片或电组件。小型化和重量降低对这些产品被市场接受是必不可少的。半导体器件之间的距离必须减小，以便实现更高密度。
图1中，PCB 52提供用于PCB上安装的半导体封装的结构支承和电互连的一般衬底。使用蒸发、电镀、非电解镀、丝网印刷或者其它适当金属沉积过程，在PCB 52的表面之上或PCB52的层之中形成导电信号迹线54。信号迹线54提供半导体封装、所安装组件和其它外部系统组件的每个之间的电通信。迹线54还向半导体封装的每个提供电力和地连接。
在一些实施例中，半导体器件具有两个封装级。第一级封装是一种用于将半导体小片机械和电附连到中间载体的技术。第二级封装涉及将中间载体机械和电附连到PCB。在其它实施例中，半导体器件可以仅具有第一级封装，其中将小片直接机械和电安装到PCB。
为了便于说明，在PCB 52上示出包括丝焊封装56和倒装芯片58的若干类型的第一级封装。另外，包括球栅阵列(BGA)60、凸块芯片载体(BCC)62、双列直插封装(DIP)64、平面栅格阵列(LGA)66、多芯片模块(MCM)68、四边扁平无引线封装(QFN)70和四边扁平封装72的若干类型的第二级封装示为安装在PCB 52上。取决于系统要求，采用第一和第二级封装样式的任何组合所配置的半导体封装以及其它电子组件的任何组合能够连接到PCB 52。在一些实施例中，电子装置50包括单个附连半导体封装，而其它实施例要求多个互连封装。通过在单个衬底之上组合一个或多个半导体封装，制造商能够将预制组件加入电子装置和系统中。由于半导体封装包括复杂功能性，所以电子装置能够使用更低价组件和流水线制造过程来制造。所产生的装置不太可能出故障并且制造价格不太高，从而对消费者带来更低成本。
图2a-2c示出示范半导体封装。图2a示出安装在PCB 52上的DIP 64的其它细节。半导体小片74包括有源区域，有源区域包含作为小片中形成并且按照小片的电气设计电互连的有源器件、无源器件、导电层和介电层所实现的模拟或数字电路。例如，电路可包括一个或多个晶体管、二极管、电感器、电容器、电阻器以及在半导体小片74的有源区域中形成的其它电路元件。接触片76是一层或多层导电材料，例如铝(Al)、铜(Cu)、锡(Sn)、镍(Ni)、金(Au)或银(Ag)，并且电连接到半导体小片74中形成的电路元件。在DIP 64的组装期间，使用金-硅共晶层或者诸如热环氧树脂或环氧树脂之类的粘合材料，将半导体小片74安装到中间载体78。封装主体包括绝缘封装材料，例如聚合物或陶瓷。导体引线80和丝焊82提供半导体小片74与PCB52之间的电互连。封装剂84沉积在封装之上，用于通过防止水分和微粒进入封装以及污染小片74或丝焊82而进行环境保护。
图2b示出安装在PCB 52上的BCC 62的其它细节。使用底部填充剂(underfill)或环氧树脂粘合材料92将半导体小片88安装在载体90之上。丝焊94提供接触片96与98之间的第一级封装互连。模塑料或封装剂100沉积在半导体小片88和丝焊94之上，以便为装置提供物理支承和电绝缘。使用诸如电镀或非电解镀之类的适当金属沉积过程在PCB 52的表面之上形成接触片102，以便防止氧化。接触片102电连接到PCB 52中的一个或多个导电信号迹线54。凸块104在BCC 62的接触片98与PCB 52的接触片102之间形成。
图2c中，采用倒装芯片样式第一级封装将半导体小片58朝下安装到中间载体106。半导体小片58的有源区域108包含作为按照小片的电气设计所形成的有源器件、无源器件、导电层和介电层所实现的模拟或数字电路。例如，电路可包括一个或多个晶体管、二极管、电感器、电容器、电阻器以及有源区域108中的其它电路元件。半导体小片58通过凸块110电和机械连接到载体106。
BGA 60采用BGA样式第二级封装、使用凸块112电和机械连接到PCB 52。半导体小片58通过凸块110、信号线114和凸块112电连接到PCB 52中的导电信号迹线54。模塑料或封装剂116沉积在半导体小片58和载体106之上，以便为装置提供物理支承和电绝缘。倒装芯片半导体器件提供从半导体小片58上的有源器件到PCB 52上的导电轨(conduction track)的短导电通路，以便降低信号传播距离、降低电容并且提高总电路性能。在另一个实施例中，半导体小片58能够使用倒装芯片样式第一级封装直接地机械和电连接到PCB 52，而无需中间载体106。
图3a示出具有诸如硅、锗、砷化镓、磷化铟或碳化硅之类的基本衬底材料122的半导体晶圆120，供结构支承。多个半导体小片或组件124在晶圆120上形成，通过锯道126分隔，如上所述。
图3b示出半导体晶圆120的一部分的截面图。各半导体小片124具有背面128和有源表面130，其中包含作为小片中形成并且按照小片的电气设计和功能电互连的有源器件、无源器件、导电层和介电层所实现的模拟或数字电路。例如，电路可包括一个或多个晶体管、二极管以及有源表面130中形成的其它电路元件，以便实现模拟电路或数字电路，例如数字信号处理器(DSP)、ASIC、存储器或者其它信号处理电路。半导体小片124还可包含用于RF信号处理的集成无源器件(IPD)，例如电感器、电容器和电阻器。在一个实施例中，半导体小片124是倒装芯片类型半导体小片。
使用PVD、CVD、电镀、非电解镀过程或者其它适当金属沉积过程，在有源表面130之上形成导电层132。导电层132能够是一层或多层Al、Cu、Sn、Ni、Au、Ag或者其它适当的导电材料。导电层132作为电连接到有源表面130上的电路的接触片进行操作。凸块134在接触片132上形成。
使用PVD、CVD、丝网印刷、旋涂、喷涂、烧结或热氧化，在有源表面130和导电层132之上形成绝缘或介电层136。绝缘层136包含一层或多层二氧化硅(SiO2)、氮化硅(Si3N4)、氧氮化硅(SiON)、五氧化二钽(Ta2O5)、氧化铝(Al2O3)或者具有相似绝缘和结构性质的其它材料。通过蚀刻过程去除绝缘层136的一部分，以便露出接触片132。
图3c中，使用锯条或激光切割工具138，通过锯道126将半导体晶圆120切分为单独半导体小片124。
图4a-4k相对于图1和图2a-2c示出形成通过封装剂之上的绝缘层的开口供互连结构的增强粘合性的过程。图4a示出包含诸如硅、聚合物、氧化铍或者其它适当低成本刚性材料之类的暂时或牺牲基本材料的衬底或载体140，供结构支承。在载体140之上形成界面层或双面胶(double-sided tape)142作为暂时粘合接合膜或蚀刻停止层。
以绝缘层136朝载体定向、使用取放操作把来自图3a-3c的半导体小片124定位在载体140之上并且安装到载体140。图4b示出安装到载体140的半导体小片124，其中绝缘层136和接触片132与界面层142邻接。
图4c中，使用焊膏印刷、压缩成型、转印成型、液态封装剂成型、真空层压、旋涂或者其它适当涂敷器(applicator)将封装剂或模塑料144沉积在半导体小片124和界面层142之上。封装剂144能够是聚合物合成材料，例如具有填充剂的环氧树脂、具有填充剂的环氧丙烯酸酯或者具有适当填充剂的聚合物。封装剂144是非导电的，并且在环境上保护半导体器件免受外部元素和污染物的影响。
图4d中，通过化学蚀刻、机械剥离、CMP、机械研磨、热烘焙、激光扫描或者湿式剥落，去除载体140和界面层142，以便露出接触片132。使用PVD、CVD、丝网印刷、旋涂、喷涂、烧结或热氧化，在半导体小片124和封装剂144之上形成绝缘或钝化层146。绝缘层146包含一层或多层SiO2、Si3N4、SiON、Ta2O5、Al2O3或者具有相似绝缘和结构性质的其它材料。通过蚀刻过程去除绝缘层146的一部分，以便形成开口或通孔148，并且露出接触片132和封装剂144。
图4e示出绝缘层146和开口148的平面图。具体来说，绝缘层146中的开口148在互连部位或凸块形成区域150中具有环形，以便露出半导体小片124的占用面积外部的封装剂144。在一个实施例中，环形开口148的宽度为20-100微米(μm)。
图4f示出作为四个隔离圆或通孔以90度递增在互连部位或凸块形成区域153周围所形成的绝缘层146和开口152的另一个实施例的平面图。开口152具有与图4e相似的截面图，并且露出半导体小片124的占用面积外部的封装剂144。开口152能够分布在互连部位153的边缘附近，例如40μm间距。
图4g示出作为多个隔离圆或通孔在互连部位或凸块形成区域155周边所形成的绝缘层146和开口154的另一个实施例的平面图。开口154具有与图4e相似的截面图，并且露出半导体小片124的占用面积外部的封装剂144。开口154能够分布在互连部位155的边缘附近，例如40μm间距。
图4h中，使用诸如PVD、CVD、溅射、电镀和非电解镀之类的形成图案以及金属沉积过程，将导电层156共形地涂敷在绝缘层146、封装剂144和外露接触片132之上。导电层156能够是一层或多层Al、Cu、Sn、Ni、Au、Ag或者其它适当的导电材料。导电层156跟随绝缘层146的轮廓，包括进入封装剂144上的环形开口148中。更具体来说，导电层156直接在环形开口148中的封装剂144上形成。同样，导电层156直接在图4f和图4g的开口152和154中的封装剂144上形成。导电层156能够是包含Ti/Cu、TiW/Cu、Ta/Cu、Cr/Cu、Ni、NiV、Au或Al的籽晶层或粘合层。
图4i中，使用诸如PVD、CVD、溅射、电镀和非电解镀之类的形成图案以及金属沉积过程，在导电层156之上形成导电层或RDL158。导电层158能够是一层或多层Al、Cu、Sn、Ni、Au、Ag或者其它适当的导电材料。导电层158的部分取决于半导体小片124的设计和功能而能够是电公共(electrically common)或电绝缘的。
图4j中，使用PVD、CVD、丝网印刷、旋涂、喷涂、烧结或热氧化，在绝缘层146和导电层158之上形成绝缘或钝化层160。绝缘层160包含一层或多层SiO2、Si3N4、SiON、Ta2O5、Al2O3或者具有相似绝缘和结构性质的其它材料。去除绝缘层160的一部分，以便露出互连部位或凸块形成区域150之上的导电层158。
图4k中，使用蒸发、电镀、非电解镀、落球(ball drop)或丝网印刷过程，在互连部位150和外露导电层158之上沉积导电凸块材料。凸块材料能够是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及其组合，其中具有可选助焊剂溶液。例如，凸块材料能够是共晶Sn/Pb、高铅焊料或者无铅焊料。使用适当附连或接合过程将凸块材料接合到导电层158。在一个实施例中，通过将材料加热到其熔点之上，使凸块材料回流以形成球珠或球形凸块164。在一些应用中，使凸块164第二次回流，以便改进到导电层158的电接触。凸块还能够压缩接合到导电层158。凸块164表示能够在导电层158之上形成的一种类型的互连结构。互连结构还能够使用螺柱凸块、微凸块或者其它电互连。
在Fo-WLCSP 166中，直接在半导体小片124的占用面积外部的环形开口148中的封装剂144上形成的导电层156(和RDL 158)的部分提供用于锚定凸块164的增强粘合性和可靠性。同样，导电层156(和RDL 158)能够直接在开口152和154中的封装剂144上形成，供增强的粘合性和可靠性。导电层156(和RDL 158)的一部分直接沉积在半导体小片124的占用面积外部的绝缘层146上，用于封装剂144的应力消除和缓冲，以及平衡半导体小片上的应力。
在另一个实施例中，继续针对一直到图4c所述的结构，使用PVD、CVD、丝网印刷、旋涂、喷涂、烧结或热氧化，在半导体小片124和封装剂144之上形成绝缘或钝化层168，如图5a所示。绝缘层168包含一层或多层SiO2、Si3N4、SiON、Ta2O5、Al2O3或者具有相似绝缘和结构性质的其它材料。通过蚀刻过程去除绝缘层168的一部分，以便形成开口或通孔170，并且露出接触片132和封装剂144。
图5b示出作为均匀分布于互连部位或凸块形成区域172的多个隔离圆或通孔所形成的绝缘层168和开口170的平面图。开口154能够分布在互连部位172的边缘附近、如40μm间距以及内部(中心)区域中。开口170露出半导体小片124的占用面积外部的封装剂144。
图5c中，使用诸如PVD、CVD、溅射、电镀和非电解镀之类的形成图案以及金属沉积过程，将导电层174共形地涂敷在绝缘层146、封装剂144和外露接触片132之上。导电层174能够是一层或多层Al、Cu、Sn、Ni、Au、Ag或者其它适当的导电材料。导电层174跟随绝缘层146的轮廓，包括进入封装剂144上的开口170中。更具体来说，导电层174直接在开口170中的封装剂144上形成。导电层170能够是包含Ti/Cu、TiW/Cu、Ta/Cu、Cr/Cu、Ni、NiV、Au或Al的籽晶层或粘合层。
使用诸如PVD、CVD、溅射、电镀和非电解镀之类的形成图案以及金属沉积过程，在导电层174之上形成导电层或RDL 176。导电层176能够是一层或多层Al、Cu、Sn、Ni、Au、Ag或者其它适当的导电材料。导电层176的部分取决于半导体小片124的设计和功能而能够是电公共或电绝缘的。
图5d中，使用PVD、CVD、丝网印刷、旋涂、喷涂、烧结或热氧化，在绝缘层146和导电层176之上形成绝缘或钝化层178。绝缘层178包含一层或多层SiO2、Si3N4、SiON、Ta2O5、Al2O3或者具有相似绝缘和结构性质的其它材料。去除绝缘层178的一部分，以便露出互连部位或凸块形成区域172之上的导电层176。
图5e中，使用蒸发、电镀、非电解镀、落球或丝网印刷过程，在互连部位172和外露导电层176之上沉积导电凸块材料。凸块材料能够是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及其组合，其中具有可选助焊剂溶液。例如，凸块材料能够是共晶Sn/Pb、高铅焊料或者无铅焊料。使用适当附连或接合过程将凸块材料接合到导电层176。在一个实施例中，通过将材料加热到其熔点之上，使凸块材料回流以形成球珠或球形凸块180。在一些应用中，使凸块180第二次回流，以便改进到导电层176的电接触。凸块还能够压缩接合到导电层176。凸块180表示能够在导电层176之上形成的一种类型的互连结构。互连结构还能够使用螺柱凸块、微凸块或者其它电互连。
在Fo-WLCSP 182中，直接在半导体小片124的占用面积外部的开口170中的封装剂144上形成的导电层174(和RDL 176)的部分提供用于锚定凸块180的增强粘合性和可靠性。导电层174(和RDL 176)的一部分直接沉积在半导体小片124的占用面积外部的绝缘层146上，用于封装剂144的应力消除和缓冲，以及平衡半导体小片上的应力。
虽然详细说明了本发明的一个或多个实施例，但是熟练的技术人员会理解，可进行对那些实施例的修改和适配，而没有背离以下权利要求书中提出的本发明的范围。

Claims (10)

1.一种制作半导体器件的方法，包括：
提供载体；
将半导体小片安装到所述载体；
将封装剂沉积在所述半导体小片和载体之上；
去除所述载体；
在所述半导体小片的占用面积外部的互连部位中的所述封装剂的一部分之上形成第一绝缘层；
去除所述互连部位中的所述第一绝缘层的一部分，以便露出所述封装剂；
在所述第一绝缘层和外露封装剂之上形成第一导电层；
在所述第一导电层之上形成第二绝缘层；以及
在所述互连部位中的所述第一导电层之上形成凸块。
2.如权利要求1所述的方法，其中，去除所述第一绝缘层的所述一部分而留下所述第一绝缘层中的环形开口，以便露出所述封装剂。
3.如权利要求1所述的方法，其中，去除所述第一绝缘层的所述一部分而留下所述第一绝缘层中在所述互连部位周围以90度递增的多个开口，以便露出所述封装剂。
4.如权利要求1所述的方法，其中，去除所述第一绝缘层的所述一部分而留下所述第一绝缘层中在所述互连部位周边的多个开口，以便露出所述封装剂。
5.一种制作半导体器件的方法，包括：
提供半导体小片；
将封装剂沉积在所述半导体小片之上和周围；
在所述半导体小片的占用面积外部的互连部位中的所述封装剂的一部分之上形成第一绝缘层；
形成通过所述互连部位中的所述第一绝缘层的开口，以便露出所述封装剂；以及
在所述第一绝缘层和外露封装剂之上形成第一导电层。
6.如权利要求5所述的方法，其中，所述第一绝缘层中的所述开口为环形。
7.如权利要求5所述的方法，其中，所述第一绝缘层中的所述开口包括所述互连部位的周边的所述第一绝缘层中的多个通孔，以便露出所述封装剂。
8.一种半导体器件，包括：
半导体小片；
沉积在所述半导体小片之上和周围的封装剂；
在所述半导体小片的占用面积外部的互连部位中的所述封装剂的一部分之上形成的第一绝缘层，其中开口形成为通过所述互连部位中的所述第一绝缘层，以便露出所述封装剂；以及
在所述第一绝缘层和外露封装剂之上形成第一导电层。
9.如权利要求8所述的半导体器件，其中，所述第一绝缘层中的所述开口为环形。
10.如权利要求8所述的半导体器件，其中，所述第一绝缘层中的所述开口包括所述互连部位的周边的所述第一绝缘层中的多个通孔，以便露出所述封装剂。
CN201110429755.XA 2010-12-10 2011-12-09 形成通过封装剂之上的绝缘层的开口供互连结构的增强粘合性的半导体器件和方法 Active CN102569097B (zh)

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