CN102543779B - 形成与半导体小片垂直分隔的互连层中的电感器的半导体器件和方法 - Google Patents

形成与半导体小片垂直分隔的互连层中的电感器的半导体器件和方法 Download PDF

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CN102543779B
CN102543779B CN201110429754.5A CN201110429754A CN102543779B CN 102543779 B CN102543779 B CN 102543779B CN 201110429754 A CN201110429754 A CN 201110429754A CN 102543779 B CN102543779 B CN 102543779B
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semiconductor chip
conductive layer
insulating barrier
layer
encapsulation agent
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CN102543779A (zh
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林耀剑
陈康
方建敏
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Stats Chippac Pte Ltd
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Stats Chippac Pte Ltd
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Abstract

半导体器件具有在载体之上形成的粘合层。半导体小片具有在半导体小片的有源表面之上形成的凸块。将半导体小片安装到载体，其中凸块部分设置在粘合层中，以便形成半导体小片与粘合层之间的间隙。将封装剂沉积在半导体小片之上以及半导体小片与粘合层之间的间隙中。去除载体和粘合层，以便从封装剂露出凸块。绝缘层在封装剂之上形成。按照缠绕配置在绝缘层之上形成导电层以呈现电感性质，并且所述导电层电连接到凸块。导电层部分设置在半导体小片的占用面积中。导电层具有由间隙和绝缘层所确定的与半导体小片的分隔。

Description

形成与半导体小片垂直分隔的互连层中的电感器的半导体器件和方法
技术领域
一般来说，本发明涉及半导体器件，并且更具体来说，涉及形成具有与半导体小片垂直分隔的互连层中的电感器的半导体器件和方法。
背景技术
半导体器件常见于现代电子产品中。半导体器件在电子组件的数量和密度方面有所不同。分立半导体器件一般包含一种类型的电组件，例如发光二极管(LED)、小信号晶体管、电阻器、电容器、电感器和功率金属氧化物半导体场效应晶体管(MOSFET)。集成半导体器件通常包含数百至数百万电组件。集成半导体器件的示例包括微控制器、微处理器、电荷耦合器件(CCD)、太阳能电池和数字微镜器件(DMD)。
半导体器件执行大量功能，例如信号处理、高速计算、传送和接收电磁信号、控制电子装置、将太阳光变换成电力以及创建用于电视显示的可视投影。半导体器件见于娱乐、通信、功率转换、网络、计算机和消费者产品的领域。半导体器件还见于军事应用、航空、汽车、工业控制器和办公设备。
半导体器件利用半导体材料的电性质。半导体材料的原子结构允许其电导率通过施加电场或基极电流或者经由掺杂过程来操纵。掺杂将杂质引入半导体材料，以便操纵和控制半导体器件的导电率。
半导体器件包含有源和无源电结构。包括双极和场效应晶体管的有源结构控制电流的流动。通过改变掺杂水平和电场或基极电流的施加，晶体管促进或限制电流的流动。包括电阻器、电容器和电感器的无源结构创建执行各种电功能所需的电压与电流之间的关系。无源和有源结构经电连接以形成电路，该电路使半导体器件能够执行高速计算和其它有用功能。
半导体器件一般使用各潜在地涉及数百个步骤的两个复杂制造过程来制造，即前端制造和后端制造。前端制造涉及在半导体晶圆的表面上形成多个小片。各小片通常是相同的，并且包含通过电连接有源和无源组件所形成的电路。后端制造涉及从成品晶圆来切分(singulate)单独小片，并且封装小片以便提供结构支承和环境隔离。
半导体制造的一个目标是产生更小的半导体器件。更小的器件通常消耗更少功率，具有更高性能，并且能够更有效地生产。另外，更小的半导体器件具有更小占用面积，这对于较小最终产品是合乎需要的。较小小片尺寸可通过前端过程的改进来实现，从而产生具有更小、更高密度的有源和无源组件的小片。通过电互连和封装材料的改进，后端过程可产生具有较小占用面积的半导体器件封装。
半导体制造的另一个目标是产生更高性能的半导体器件。装置性能的增加能够通过形成能够工作在更高速度的有源组件来实现。在诸如射频(RF)无线通信之类的高频应用中，集成无源器件(IPD)往往包含在半导体器件中。IPD的示例包括电阻器、电容器和电感器。一种典型RF系统要求一个或多个半导体封装中的多个IPD来执行必要的电功能。
电感器能够在半导体小片中形成。但是，集成小片电感器往往部分由于涡流损耗而遭受低Q因子。集成电感器消耗相当大的小片面积，并且降低设计灵活性。
发明内容
需要半导体器件中的高Q因子电感器。相应地，在一个实施例中，本发明是一种制作半导体器件的方法，包括下列步骤：提供载体；在载体之上形成粘合层；提供具有在半导体小片的有源表面之上形成的多个凸块的半导体小片；将半导体小片安装到载体，其中凸块部分设置在粘合层中以形成半导体小片与粘合层之间的间隙；将封装剂沉积在半导体小片之上以及半导体小片与粘合层之间的间隙之中；去除载体和粘合层，以便从封装剂露出凸块；在封装剂之上形成绝缘层；以及按照缠绕配置在绝缘层之上形成第一导电层以呈现电感性质并且该第一导电层电连接到凸块。第一导电层具有由间隙中的封装剂和绝缘层所确定的与半导体小片的分隔。
在另一个实施例中，本发明是一种制作半导体器件的方法，包括下列步骤：提供载体；提供半导体小片；在半导体小片的表面之上形成第一绝缘层；以第一绝缘层为先导而将半导体小片安装到载体；将封装剂沉积在半导体小片之上；去除载体；在半导体小片之上形成第二绝缘层；以及按照缠绕配置在第二绝缘层之上形成第一导电层以呈现电感性质。第一导电层具有由第一和第二绝缘层所确定的与半导体小片的分隔。
在另一个实施例中，本发明是一种制作半导体器件的方法，包括下列步骤：提供半导体小片；在半导体小片的第一表面上形成第一绝缘层；将封装剂沉积在半导体小片中与第一表面相对的第二表面之上；在半导体小片的第一表面之上形成第二绝缘层；以及按照缠绕配置在第二绝缘层之上形成第一导电层以呈现电感性质。第一导电层具有与半导体小片的分隔。
在另一个实施例中，本发明是一种半导体器件，包括半导体小片以及在半导体小片的第一表面之上形成的第一绝缘层。封装剂沉积在半导体小片中与第一表面相对的第二表面之上。在半导体小片的第一表面之上形成第二绝缘层。按照缠绕配置在第二绝缘层之上形成第一导电层以呈现电感性质。第一导电层具有与半导体小片的分隔。
附图说明
图1示出具有安装到其表面的不同类型的封装的PCB；
图2a-2c示出安装到PCB的半导体封装的其它细节；
图3a-3c示出具有通过锯道所分离的多个半导体小片的半导体晶圆；
图4a-4k示出形成具有与半导体小片的垂直分隔的互连层中的电感器的过程；
图5a-5f示出形成具有与半导体小片的垂直分隔的互连层中的电感器的第二实施例；
图6a-6g示出形成具有与半导体小片的垂直分隔的互连层中的电感器的第三实施例；以及
图7a-7e示出形成具有与半导体小片的垂直分隔的互连层中的电感器的第四实施例。
具体实施方式
在以下描述中参照附图、通过一个或多个实施例来描述本发明，附图中，相似标号表示相同或相似元件。虽然按照用于实现本发明的目标的最佳模式来描述本发明，但是本领域的技术人员会理解，预计涵盖可包含在所附权利要求书所定义的本发明及以下公开和附图所支持的其等效方案的精神和范围之内的备选、修改和等效方案。
半导体器件一般使用两个复杂制造过程来制造：前端制造和后端制造。前端制造涉及在半导体晶圆的表面上形成多个小片。晶圆上的各小片包含有源和无源电组件，它们经电连接以形成功能电路。诸如晶体管和二极管之类的有源电组件具有控制电流的流动的能力。诸如电容器、电感器、电阻器和变压器之类的无源电组件创建执行电路功能所需的电压与电流之间的关系。
通过包括掺杂、沉积、光刻、蚀刻和平面化的一系列过程步骤，在半导体晶圆的表面之上形成无源和有源组件。掺杂通过诸如离子注入或热扩散之类的技术，将杂质引入半导体材料。掺杂过程修改有源器件中的半导体材料的电导率，从而将半导体材料变换为绝缘体、导电体，或者响应电场或基极电流而动态改变半导体材料导电率。晶体管包含根据需要所设置的可变类型和程度的掺杂的区域，以便在施加电场或基极电流时使晶体管能够促进或限制电流的流动。
有源和无源组件通过具有不同电性质的材料层来形成。能够通过部分由所沉积材料的类型所确定的各种沉积技术来形成层。例如，薄膜沉积可涉及化学气相沉积(CVD)、物理气相沉积(PVD)、电镀和非电解镀过程。一般对各层形成图案以形成有源组件、无源组件或者组件之间的电连接的部分。
能够使用光刻来对层形成图案，这涉及在将要形成图案的层之上沉积光敏材料、如光致抗蚀剂。使用光线将图案从光掩模转印到光致抗蚀剂。使用溶剂去除经受光线的光致抗蚀剂图案的部分，从而露出待形成图案的基础层的部分。去除光致抗蚀剂的其余部分，从而留下形成图案的层。备选地，通过使用诸如非电解镀和电镀之类的技术将材料直接沉积到前一个沉积/蚀刻过程所形成的区域或空隙(void)中，来对一些类型的材料形成图案。
将材料薄膜沉积在现有图案之上能够扩大基本图案并且创建非均匀平坦表面。需要均匀平坦表面以产生更小并且更密集封装的有源和无源组件。平面化能够用于从晶圆的表面去除材料，并且产生均匀平坦表面。平面化涉及采用抛光垫来抛光晶圆的表面。在抛光期间将研磨材料和腐蚀性化学品添加到晶圆的表面。研磨剂的机械作用和化学品的腐蚀作用的结合去除任何不规则拓扑，从而产生均匀平坦表面。
后端制造表示将成品晶圆切割或切分为单独小片，并且然后封装小片供结构支承和环境隔离。为了对小片进行切分，沿称作锯道(sawstreet)或锯痕(scribe)的晶圆的非功能区域来将晶圆划线和分离。使用激光切割工具或锯条来对晶圆进行切分。在切分之后，单独小片被安装到包括引脚或接触片供与其它系统组件互连的封装衬底。在半导体小片之上形成的接触片则连接到封装中的接触片。电连接能够采用焊料凸块、螺柱凸块(studbump)、导电膏或丝焊来制作。封装剂或其它成型材料沉积在封装之上，以便提供物理支承和电绝缘。然后，将成品封装插入电气系统，并且使半导体器件的功能性为其它系统组件可用。
图1示出具有芯片承载衬底或印刷电路板(PCB)52的电子装置50，其中多个半导体封装安装在其表面上。电子装置50可根据应用而具有一种类型的半导体封装或者多种类型的半导体封装。为了便于说明，在图1中示出不同类型的半导体封装。
电子装置50可以是使用半导体封装来执行一个或多个电功能的独立系统。备选地，电子装置50可以是较大系统的子组件。例如，电子装置50可以是蜂窝电话、个人数字助理(PDA)、数字摄像机(DVC)或者其它电子通信装置的一部分。备选地，电子装置50能够是图形卡、网络接口卡或者能够插入计算机中的其它信号处理卡。半导体封装能够包括微处理器、存储器、专用集成电路(ASIC)、逻辑电路、模拟电路、RF电路、分立装置或者其它半导体小片或电组件。小型化和重量降低对这些产品被市场接受是必不可少的。半导体器件之间的距离必须减小，以便实现更高密度。
图1中，PCB52提供用于PCB上安装的半导体封装的结构支承和电互连的一般衬底。使用蒸发、电镀、非电解镀、丝网印刷或者其它适当金属沉积过程，在PCB52的表面之上或PCB52的层之中形成导电信号迹线54。信号迹线54提供半导体封装、所安装组件和其它外部系统组件的每个之间的电通信。迹线54还向半导体封装的每个提供电力和地连接。
在一些实施例中，半导体器件具有两个封装级。第一级封装是一种用于将半导体小片机械和电附连到中间载体的技术。第二级封装涉及将中间载体机械和电附连到PCB。在其它实施例中，半导体器件可以仅具有第一级封装，其中将小片直接机械和电安装到PCB。
为了便于说明，在PCB52上示出包括丝焊封装56和倒装芯片58的若干类型的第一级封装。另外，包括球栅阵列(BGA)60、凸块芯片载体(BCC)62、双列直插封装(DIP)64、平面栅格阵列(LGA)66、多芯片模块(MCM)68、四边扁平无引线封装(QFN)70和四边扁平封装72的若干类型的第二级封装示为安装在PCB52上。取决于系统要求，采用第一和第二级封装样式的任何组合所配置的半导体封装以及其它电子组件的任何组合能够连接到PCB52。在一些实施例中，电子装置50包括单个附连半导体封装，而其它实施例要求多个互连封装。通过在单个衬底之上组合一个或多个半导体封装，制造商能够将预制组件加入电子装置和系统中。由于半导体封装包括复杂功能性，所以电子装置能够使用更低价组件和流水线制造过程来制造。所产生的装置不太可能出故障并且制造价格不太高，从而对消费者带来更低成本。
图2a-2c示出示范半导体封装。图2a示出安装在PCB52上的DIP64的其它细节。半导体小片74包括有源区域，有源区域包含作为小片中形成并且按照小片的电气设计电互连的有源器件、无源器件、导电层和介电层所实现的模拟或数字电路。例如，电路可包括一个或多个晶体管、二极管、电感器、电容器、电阻器以及在半导体小片74的有源区域中形成的其它电路元件。接触片76是一层或多层导电材料，例如铝(Al)、铜(Cu)、锡(Sn)、镍(Ni)、金(Au)或银(Ag)，并且电连接到半导体小片74中形成的电路元件。在DIP64的组装期间，使用金-硅共晶层或者诸如热环氧树脂或环氧树脂之类的粘合材料，将半导体小片74安装到中间载体78。封装主体包括绝缘封装材料，例如聚合物或陶瓷。导体引线80和丝焊82提供半导体小片74与PCB52之间的电互连。封装剂84沉积在封装之上，用于通过防止水分和微粒进入封装以及污染小片74或丝焊82而进行环境保护。
图2b示出安装在PCB52上的BCC62的其它细节。使用底部填充剂(underfill)或环氧树脂粘合材料92将半导体小片88安装在载体90之上。丝焊94提供接触片96与98之间的第一级封装互连。模塑料或封装剂100沉积在半导体小片88和丝焊94之上，以便为装置提供物理支承和电绝缘。使用诸如电镀或非电解镀之类的适当金属沉积过程在PCB52的表面之上形成接触片102，以便防止氧化。接触片102电连接到PCB52中的一个或多个导电信号迹线54。凸块104在BCC62的接触片98与PCB52的接触片102之间形成。
图2c中，采用倒装芯片样式第一级封装将半导体小片58朝下安装到中间载体106。半导体小片58的有源区域108包含作为按照小片的电气设计所形成的有源器件、无源器件、导电层和介电层所实现的模拟或数字电路。例如，电路可包括一个或多个晶体管、二极管、电感器、电容器、电阻器以及有源区域108中的其它电路元件。半导体小片58通过凸块110电和机械连接到载体106。
BGA60采用BGA样式第二级封装、使用凸块112电和机械连接到PCB52。半导体小片58通过凸块110、信号线114和凸块112电连接到PCB52中的导电信号迹线54。模塑料或封装剂116沉积在半导体小片58和载体106之上，以便为装置提供物理支承和电绝缘。倒装芯片半导体器件提供从半导体小片58上的有源器件到PCB52上的导电轨(conductiontrack)的短导电通路，以便降低信号传播距离、降低电容并且提高总电路性能。在另一个实施例中，半导体小片58能够使用倒装芯片样式第一级封装直接地机械和电连接到PCB52，而无需中间载体106。
图3a示出具有诸如硅、锗、砷化镓、磷化铟或碳化硅之类的基本衬底材料122的半导体晶圆120，供结构支承。多个半导体小片或组件124在晶圆120上形成，通过锯道126分隔，如上所述。
图3b示出半导体晶圆120的一部分的截面图。各半导体小片124具有背面128和有源表面130，其中包含作为小片中形成并且按照小片的电气设计和功能电互连的有源器件、无源器件、导电层和介电层所实现的模拟或数字电路。例如，电路可包括一个或多个晶体管、二极管以及有源表面130中形成的其它电路元件，以便实现模拟电路或数字电路，例如数字信号处理器(DSP)、ASIC、存储器或者其它信号处理电路。半导体小片124还可包含用于RF信号处理的集成无源器件(IPD)，例如电感器、电容器和电阻器。在一个实施例中，半导体小片124是倒装芯片类型半导体小片。
使用PVD、CVD、电镀、非电解镀过程或者其它适当金属沉积过程，在有源表面130之上形成导电层132。导电层132能够是一层或多层Al、Cu、Sn、Ni、Au、Ag或者其它适当的导电材料。导电层132作为电连接到有源表面130上的电路的接触片进行操作。凸块134在接触片132上形成。
图3c中，使用锯条或激光切割工具136，通过锯道126将半导体晶圆120切分为单独半导体小片124。
图4a-4k相对于图1和图2a-2c来示出形成具有与半导体小片的垂直分隔的互连层中的电感器的过程。图4a示出包含诸如硅、聚合物、氧化铍或者其它适当低成本刚性材料之类的暂时或牺牲基本材料的衬底或载体140，供结构支承。在载体140之上形成界面层或双面胶(double-sidedtape)142作为暂时粘合接合膜或蚀刻停止层。在界面层142之上形成可渗透粘合层144。在一个实施例中，可渗透粘合层144是B阶材料。
图4b中，使用取放操作把来自图3a-3c的半导体小片124定位在载体140之上并且安装到载体140。凸块134部分嵌入粘合层144中，以便留下半导体小片124与粘合层144之间的间隙145，如图4c所示。在一个实施例中，半导体小片124包含导电层146(稍后用作电感器桥)以及作为有源表面130的一部分的模拟和数字电路148，如图3b所示。
使用PVD、CVD、丝网印刷、旋涂、喷涂、烧结或热氧化，在半导体小片124的有源表面130和导电层146之上形成绝缘或介电层150。绝缘层150包含一层或多层二氧化硅(SiO2)、氮化硅(Si3N4)、氧氮化硅(SiON)、五氧化二钽(Ta2O5)、氧化铝(Al2O3)、聚酰亚胺、苯并环丁烯(BCB)、聚苯并恶唑(PBO)或者其它适当介电材料。
图4d中，使用焊膏印刷、压缩成型、转印成型、液态封装剂成型、真空层压、旋涂或者其它适当涂敷器(applicator)将封装剂或模塑料152沉积在半导体小片124和粘合层144之上。封装剂152延伸在半导体小片124与粘合层144之间。在一个实施例中，使用模底部填充(moldunderfill，MUF)过程在压力下将封装剂152从分配针头(dispensingneedle)注入凸块134周围、在半导体小片124与粘合层144之间的间隙145中。真空辅助能够吸取封装剂152以帮助均匀分布。封装剂152能够是聚合物合成材料，例如具有填充剂的环氧树脂、具有填充剂的环氧丙烯酸酯或者具有适当填充剂的聚合物。封装剂152是非导电的，并且在环境方面保护半导体器件免受外部元素和污染物的影响。由于半导体小片124与粘合层144之间的间隙145，半导体小片124之下的封装剂152的厚度为15-90微米(μm)。
图4e示出可选背面研磨操作，其中封装剂152的表面154的一部分由研磨机156去除，以便平面化封装剂并且露出半导体小片124的背面128供静电放电(ESD)控制。
图4f中，通过化学蚀刻、机械剥离、CMP、机械研磨、热烘焙、激光扫描或者湿式剥落，去除载体140、界面层142和粘合层144，以便从封装剂152露出凸块134。
图4g中，使用PVD、CVD、丝网印刷、旋涂、喷涂、烧结或热氧化，在封装剂152中与表面154相对的表面160之上形成绝缘或介电层158。绝缘层158包含一层或多层SiO2、Si3N4、SiON、Ta2O5、Al2O3、聚酰亚胺、BCB、PBO或者其它适当介电材料。绝缘层158的厚度为5-50μm。去除绝缘层158的一部分，以便露出凸块134。
图4h中，使用诸如PVD、CVD、溅射、电镀和非电解镀之类的形成图案以及金属沉积过程，将导电层162共形地涂敷在绝缘层158和外露凸块134之上。导电层162能够是一层或多层Al、Cu、Sn、Ni、Au、Ag或者其它适当的导电材料。导电层162能够是跟随绝缘层158的轮廓的籽晶层，包括进入绝缘层的已去除部分之中以及外露凸块134周围。在另一个实施例中，导电层162是具有粘合层、阻挡层和籽晶或浸润层的多金属叠层。粘合层在绝缘层158和凸块134之上形成，并且能够是钛(Ti)、氮化钛(TiN)、钛钨(TiW)、Al或铬(Cr)。阻挡层在粘合层之上形成，并且能够是Ni、NiV、铂(Pt)、钯(Pd)、TiW或铬铜(CrCu)。阻挡层阻止Cu扩散到小片的有源区域中。籽晶层在阻挡层之上形成，并且能够是Cu、Ni、NiV、Au或Al。
在导电层162之上形成绝缘或光致抗蚀剂层164。通过蚀刻过程去除绝缘层164的一部分，以便对导电层166a-166h形成图案。通过电镀、非电解镀或者其它适当金属沉积过程，在绝缘层164的已去除部分中沉积导电材料。剩余绝缘层164以及绝缘层下面的导电层162通过蚀刻过程去除，从而留下作为一层或多层Al、Cu、Sn、Ni、Au、Ag或者其它适当导电材料的导电层166a-166h，如图4i所示。导电层166a-166h取决于半导体小片124的设计和功能而能够是电公共或电绝缘的。
导电层166的单独段在平面图中能够缠绕或盘绕，以便产生或呈现电感性质。例如，导电层166d、166e、166f和166g构成缠绕或螺旋电感器翼(inductorwing)，如图4j所示。在部分或完全处于半导体小片124的占用面积之内的互连层中设置电感器翼166d-166g。电感器翼166d-166g通过导电层162、凸块134和接触片132电连接到导电层146，导电层146作为电感器桥进行操作，以便将电感器翼电连接到模拟和数字电路148。由于半导体小片124之下的封装剂152的厚度(15-90μm)和绝缘层158的厚度(5-50μm)，电感器翼166d-166g与半导体小片124分隔20-140μm。在一个实施例中，电感器翼166d-166g与半导体小片124分隔100μm。电感器翼166d-166g与半导体小片124之间的间隙降低涡流损耗，并且增加Q因子。
图4k中，使用PVD、CVD、丝网印刷、旋涂、喷涂、烧结或热氧化，在绝缘层158和导电层166之上形成绝缘或钝化层168。绝缘层168包含一层或多层SiO2、Si3N4、SiON、Ta2O5、Al2O3或者具有相似绝缘和结构性质的其它材料。去除绝缘层168的一部分，以便露出导电层166a、166c和166h。
使用蒸发、电镀、非电解镀、落球或丝网印刷过程，在外露导电层166a、166c和166h之上沉积导电凸块材料。凸块材料能够是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及其组合，其中具有可选助焊剂溶液。例如，凸块材料能够是共晶Sn/Pb、高铅焊料或者无铅焊料。使用适当附连或接合过程将凸块材料接合到导电层166。在一个实施例中，通过将材料加热到其熔点之上，使凸块材料回流以形成球珠或球形凸块170。在一些应用中，使凸块170第二次回流，以便改进到导电层166的电接触。凸块还能够压缩接合到导电层166。凸块170表示能够在导电层166之上形成的一种类型的互连结构。互连结构还能够使用螺柱凸块、微凸块或者其它电互连。
图5a-5f示出具有包含诸如硅、聚合物、氧化铍或者其它适当低成本刚性材料之类的暂时或牺牲基本材料的衬底或载体172供结构支承的另一个实施例。图5a中，在载体172之上形成界面层或双面胶(double-sidedtape)173作为暂时粘合接合膜或蚀刻停止层。
采取晶圆形式来提供多个半导体小片174，与图3a相似。各半导体小片174具有背面178和有源表面180，其中包含作为小片中形成并且按照小片的电气设计和功能电互连的有源器件、无源器件、导电层和介电层所实现的模拟或数字电路。例如，电路可包括一个或多个晶体管、二极管以及有源表面180中形成的其它电路元件，以便实现模拟电路或数字电路，例如DSP、ASIC、存储器或者其它信号处理电路。半导体小片174还可包含用于RF信号处理的IPD，例如电感器、电容器和电阻器。
使用PVD、CVD、电镀、非电解镀过程或者其它适当金属沉积过程，在有源表面180之上形成导电层182。导电层182能够是一层或多层Al、Cu、Sn、Ni、Au、Ag或者其它适当的导电材料。导电层182稍后用作到作为有源表面180的一部分的模拟和数字电路188的电感器桥。
使用PVD、CVD、丝网印刷、旋涂、喷涂、烧结或热氧化，在半导体小片124的有源表面180和导电层182之上形成绝缘或介电层190。绝缘层190包含一层或多层SiO2、Si3N4、SiON、Ta2O5、Al2O3、聚酰亚胺、BCB、PBO或者其它适当介电材料。
使用PVD、CVD、电镀、非电解镀过程或者其它适当金属沉积过程，在绝缘层190之上形成导电层192。导电层192能够是一层或多层Al、Cu、Sn、Ni、Au、Ag或者其它适当的导电材料。导电层192电连接到导电层182以及模拟和数字电路188。
通过镀铜、焊球附连或丝焊在192和190上形成导电栓塞196。在采取晶圆形式时进行分割之前，参见图3a-3b，使用PVD、CVD、丝网印刷、旋涂、喷涂、层压、成型(molding)、烧结或热氧化，在绝缘层190和导电层192之上形成绝缘或介电层194并且露出导电栓塞196。绝缘层194包含一层或多层SiO2、Si3N4、SiON、Ta2O5、Al2O3、聚酰亚胺、BCB、PBO或者其它适当介电材料。在一个实施例中，绝缘层194具有15-90μm的厚度，并且包含高电阻率材料，例如具有填充剂的聚合物材料。
备选地，在采取晶圆形式时进行分割之前，使用激光打孔、机械打孔或深反应离子蚀刻(DRIE)，来形成通过绝缘层194的多个通孔。通孔向下延伸到导电层192。使用电镀、非电解镀过程或者其它适当金属沉积过程，采用Al、Cu、Sn、Ni、Au、Ag、Ti、W、多晶硅或者其它适当导电材料来填充通孔，以便形成z方向垂直互连导电栓塞196。导电栓塞196电连接到导电层192。导电层192为导电栓塞196提供对准容限(tolerance)。
在分割半导体晶圆之后，与图3c相似，使用取放操作将半导体小片174定位在载体172和界面层173之上并且安装到载体172和界面层173。绝缘层194提供半导体小片174与界面层173之间的15-90μm的间距或分隔198，如图5b所示。
图5c中，使用焊膏印刷、压缩成型、转印成型、液态封装剂成型、真空层压、旋涂或者其它适当涂敷器将封装剂或模塑料200沉积在半导体小片174和界面层173之上。封装剂200能够是聚合物合成材料，例如具有填充剂的环氧树脂、具有填充剂的环氧丙烯酸酯或者具有适当填充剂的聚合物。封装剂200是非导电的，并且在环境方面保护半导体器件免受外部元素和污染物的影响。
能够在可选背面研磨操作中去除封装剂200的表面202的一部分，与图4e相似，以便平面化封装剂并且露出半导体小片174的背面178供ESD控制。
图5d中，通过化学蚀刻、机械剥离、CMP、机械研磨、热烘焙、激光扫描或者湿式剥落，去除载体172和界面层173，以便露出导电栓塞196。
使用PVD、CVD、丝网印刷、旋涂、喷涂、烧结或热氧化，在封装剂200中与表面202相对的表面205之上形成绝缘或介电层204。绝缘层204包含一层或多层SiO2、Si3N4、SiON、Ta2O5、Al2O3、聚酰亚胺、BCB、PBO或者其它适当介电材料。绝缘层204的厚度为5-50μm。去除绝缘层204的一部分，以便露出导电栓塞196。
图5e中，通过电镀、非电解镀或者其它适当金属沉积过程，在绝缘层204之上形成作为段206a-206h的导电层206。导电层206a-206h包含一层或多层Al、Cu、Sn、Ni、Au、Ag或者其它适当的导电材料。导电层206a-206h取决于半导体小片174的设计和功能而能够是电公共或电绝缘的。
导电层206的单独段在平面图中能够缠绕或盘绕，以便产生或呈现电感性质。例如，导电层206d、206e、206f和206g构成缠绕或螺旋电感器翼，与图4j相似。在部分或完全处于半导体小片174的占用面积之内的互连层中设置电感器翼206d-206g。电感器翼206d-206g通过导电栓塞196和导电层192电连接到导电层182，导电层182作为电感器桥进行操作，以便将电感器翼电连接到模拟和数字电路188。由于绝缘层194的厚度(15-90μm)和绝缘层204的厚度(5-50μm)，电感器翼206d-206g与半导体小片174分隔20-140μm。在一个实施例中，电感器翼206d-206g与半导体小片174分隔100μm。电感器翼206d-206g与半导体小片174之间的分隔降低涡流损耗，并且增加Q因子。
图5f中，使用PVD、CVD、丝网印刷、旋涂、喷涂、烧结或热氧化，在绝缘层204和导电层206之上形成绝缘或钝化层208。绝缘层208包含一层或多层SiO2、Si3N4、SiON、Ta2O5、Al2O3或者具有相似绝缘和结构性质的其它材料。去除绝缘层208的一部分，以便露出导电层206a、206c和206h。
使用蒸发、电镀、非电解镀、落球或丝网印刷过程，在外露导电层206a、206c和206h之上沉积导电凸块材料。凸块材料能够是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及其组合，其中具有可选助焊剂溶液。例如，凸块材料能够是共晶Sn/Pb、高铅焊料或者无铅焊料。使用适当附连或接合过程将凸块材料接合到导电层206。在一个实施例中，通过将材料加热到其熔点之上，使凸块材料回流以形成球珠或球形凸块210。在一些应用中，使凸块210第二次回流，以便改进到导电层206的电接触。凸块还能够压缩接合到导电层206。凸块210表示能够在导电层206之上形成的一种类型的互连结构。互连结构还能够使用螺柱凸块、微凸块或者其它电互连。
图6a-6g示出具有包含诸如硅、聚合物、氧化铍或者其它适当低成本刚性材料之类的暂时或牺牲基本材料的衬底或载体212供结构支承的另一个实施例。图6a中，在载体212之上形成界面层或双面胶213作为暂时粘合接合膜或蚀刻停止层。
采取晶圆形式来提供多个半导体小片214，与图3a相似。各半导体小片214具有背面218和有源表面220，其中包含作为小片中形成并且按照小片的电气设计和功能电互连的有源器件、无源器件、导电层和介电层所实现的模拟或数字电路。例如，电路可包括一个或多个晶体管、二极管以及有源表面220中形成的其它电路元件，以便实现模拟电路或数字电路，例如DSP、ASIC、存储器或者其它信号处理电路。半导体小片214还可包含用于RF信号处理的IPD，例如电感器、电容器和电阻器。
使用PVD、CVD、电镀、非电解镀过程或者其它适当金属沉积过程，在有源表面220之上形成导电层222。导电层222能够是一层或多层Al、Cu、Sn、Ni、Au、Ag或者其它适当的导电材料。导电层222稍后用作到作为有源表面220的一部分的模拟和数字电路228的电感器桥。
使用PVD、CVD、丝网印刷、旋涂、喷涂、烧结或热氧化，在半导体小片214的有源表面220和导电层222之上形成绝缘或介电层230。绝缘层230包含一层或多层SiO2、Si3N4、SiON、Ta2O5、Al2O3、聚酰亚胺、BCB、PBO或者其它适当介电材料。
使用PVD、CVD、电镀、非电解镀过程或者其它适当金属沉积过程，在绝缘层230之上形成导电层232。导电层232能够是一层或多层Al、Cu、Sn、Ni、Au、Ag或者其它适当的导电材料。导电层232电连接到导电层222。
在采取晶圆形式时进行分割之前，参见图3a-3b，在绝缘层230和导电层232之上形成牺牲层234。牺牲层234包含一层或多层干膜和背面研磨带、液态光致抗蚀剂或保护膏。在一个实施例中，绝缘层234的厚度为15-90μm。
在分割半导体晶圆之后，与图3c相似，使用取放操作将半导体小片214定位在载体212和界面层213之上并且安装到载体212和界面层213。牺牲层234提供半导体小片214与界面层213之间的15-90μm的间距或分隔238，如图6b所示。
图6c中，使用焊膏印刷、压缩成型、转印成型、液态封装剂成型、真空层压、旋涂或者其它适当涂敷器将封装剂或模塑料240沉积在半导体小片214和界面层213之上。封装剂240能够是聚合物合成材料，例如具有填充剂的环氧树脂、具有填充剂的环氧丙烯酸酯或者具有适当填充剂的聚合物。封装剂240是非导电的，并且在环境方面保护半导体器件免受外部元素和污染物的影响。
能够在可选背面研磨操作中去除封装剂240的表面242的一部分，与图4e相似，以便平面化封装剂并且露出半导体小片214的背面218供ESD控制。
图6d中，通过化学蚀刻、机械剥离、CMP、机械研磨、热烘焙、激光扫描或者湿式剥落，去除载体212、界面层213和牺牲层234，从而在半导体小片214之下留下空腔246。
图6e中，使用PVD、CVD、丝网印刷、旋涂、喷涂、烧结或热氧化，在封装剂240中与表面242相对的表面254之上形成绝缘或介电层252，并且形成到空腔246中。绝缘层252包含一层或多层SiO2、Si3N4、SiON、Ta2O5、Al2O3、聚酰亚胺、BCB、PBO或者其它适当介电材料。在一个实施例中，沉积作为单层或双层介电材料的绝缘层252。绝缘层252的厚度为5-50μm。去除绝缘层252的一部分，以便露出导电层232。
图6f中，通过电镀、非电解镀或者其它适当金属沉积过程，在绝缘层252之上形成作为段256a-256h的导电层256。导电层256a-256h包含一层或多层Al、Cu、Sn、Ni、Au、Ag或者其它适当的导电材料。例如，导电层256可包括Ti/Cu或TiW/Cu的籽晶层，其中选择性镀铜之后接着籽晶层湿式蚀刻。导电层256b和256f延伸到绝缘层252的已去除部分中，以便接触导电层232。导电层256a-256h取决于半导体小片214的设计和功能而能够是电公共或电绝缘的。
导电层256的单独段在平面图中能够缠绕或盘绕，以便产生或呈现电感性质。例如，导电层256d、256e、256f和256g构成缠绕或螺旋电感器翼，与图4j相似。在部分或完全处于半导体小片214的占用面积之内的互连层中设置电感器翼256d-256g。电感器翼256d-256g通过导电层232电连接到导电层222，导电层222作为电感器桥进行操作，以便将电感器翼电连接到模拟和数字电路228。由于绝缘层252的厚度，电感器翼256d-256g与半导体小片214分隔25-160μm。在一个实施例中，电感器翼256d-256g与半导体小片214分隔120μm。电感器翼256d-256g与半导体小片214之间的分隔降低涡流损耗，并且增加Q因子。
图6g中，使用PVD、CVD、丝网印刷、旋涂、喷涂、烧结或热氧化，在绝缘层252和导电层256之上形成绝缘或钝化层258。绝缘层258包含一层或多层SiO2、Si3N4、SiON、Ta2O5、Al2O3或者具有相似绝缘和结构性质的其它材料。去除绝缘层258的一部分，以便露出导电层256a、256c和256h。
使用蒸发、电镀、非电解镀、落球或丝网印刷过程，在外露导电层256a、256c和256h之上沉积导电凸块材料。凸块材料能够是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及其组合，其中具有可选助焊剂溶液。例如，凸块材料能够是共晶Sn/Pb、高铅焊料或者无铅焊料。使用适当附连或接合过程将凸块材料接合到导电层256。在一个实施例中，通过将材料加热到其熔点之上，使凸块材料回流以形成球珠或球形凸块260。在一些应用中，使凸块260第二次回流，以便改进到导电层256的电接触。凸块还能够压缩接合到导电层256。凸块260表示能够在导电层256之上形成的一种类型的互连结构。互连结构还能够使用螺柱凸块、微凸块或者其它电互连。
图7a-7e延续图6d来示出另一个实施例，其中空腔246通过剥落牺牲保护层234来露出半导体小片214。在采取晶圆形式时，使用蒸发、电镀、非电解镀、落球或丝网印刷过程，在空腔246中的外露导电层232之上沉积导电凸块材料，如图7a所示。凸块材料能够是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及其组合，其中具有可选助焊剂溶液。例如，凸块材料能够是共晶Sn/Pb、高铅焊料或者无铅焊料。使用适当附连或接合过程将凸块材料接合到导电层232。在一个实施例中，通过将材料加热到其熔点之上，使凸块材料回流以形成球珠或球形凸块270。在一些应用中，使凸块270第二次回流，以便改进到导电层232的电接触。凸块还能够压缩接合到导电层232。凸块270表示能够在导电层232之上形成的一种类型的互连结构。互连结构还能够使用螺柱凸块、微凸块或者其它电互连。
图7b示出一个实施例，其中在采取晶圆形式时，背面研磨带262和保护衬垫264在凸块270和绝缘层230之上形成。在一个实施例中，带262能够是耐热树脂。背面研磨带262和保护衬垫264在背面研磨与分割操作期间提供结构支承，如图3c和图4e所示。
图7c中，使用PVD、CVD、丝网印刷、喷涂、旋涂、烧结或热氧化，在封装剂240中与表面242相对的表面274之上形成绝缘或介电层272，并且形成到凸块270之上的空腔246中。绝缘层272包含一层或多层SiO2、Si3N4、SiON、Ta2O5、Al2O3、聚酰亚胺、BCB、PBO或者其它适当介电材料。在一个实施例中，沉积作为单层或双层介电材料的绝缘层272。绝缘层272的厚度为5-50μm。去除绝缘层272的一部分，以便露出凸块270。
图7d中，通过电镀、非电解镀或者其它适当金属沉积过程，在绝缘层272之上形成作为段276a-276h的导电层276。导电层276a-276h包含一层或多层Al、Cu、Sn、Ni、Au、Ag或者其它适当的导电材料。例如，导电层276可包括Ti/Cu或TiW/Cu的籽晶层，其中选择性镀铜之后接着籽晶层湿式蚀刻。导电层276b和276f延伸到绝缘层272的已去除部分中，以便接触凸块270。导电层276a-276h取决于半导体小片214的设计和功能而能够是电公共或电绝缘的。
导电层276的单独段在平面图中能够缠绕或盘绕，以便产生或呈现电感性质。例如，导电层276d、276e、276f和276g构成缠绕或螺旋电感器翼，与图4j相似。在部分或完全处于半导体小片214的占用面积之内的互连层中设置电感器翼276d-276g。电感器翼276d-276g通过凸块270和导电层232电连接到导电层222，导电层222作为电感器桥进行操作，以便将电感器翼电连接到模拟和数字电路228。由于绝缘层272的厚度，电感器翼276d-276g与半导体小片214分隔25-160μm。在一个实施例中，电感器翼276d-276g与半导体小片214分隔120μm。电感器翼276d-276g与半导体小片214之间的分隔降低涡流损耗，并且增加Q因子。
图7e中，使用PVD、CVD、丝网印刷、旋涂、喷涂、烧结或热氧化，在绝缘层272和导电层276之上形成绝缘或钝化层278。绝缘层278包含一层或多层SiO2、Si3N4、SiON、Ta2O5、Al2O3或者具有相似绝缘和结构性质的其它材料。去除绝缘层278的一部分，以便露出导电层276a、276c和276h。
使用蒸发、电镀、非电解镀、落球或丝网印刷过程，在外露导电层276a、276c和276h之上沉积导电凸块材料。凸块材料能够是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及其组合，其中具有可选助焊剂溶液。例如，凸块材料能够是共晶Sn/Pb、高铅焊料或者无铅焊料。使用适当附连或接合过程将凸块材料接合到导电层276。在一个实施例中，通过将材料加热到其熔点之上，使凸块材料回流以形成球珠或球形凸块280。在一些应用中，使凸块280第二次回流，以便改进到导电层276的电接触。凸块还能够压缩接合到导电层276。凸块280表示能够在导电层276之上形成的一种类型的互连结构。互连结构还能够使用螺柱凸块、微凸块或者其它电互连。
虽然详细说明了本发明的一个或多个实施例，但是熟练的技术人员会理解，可进行对那些实施例的修改和适配，而没有背离以下权利要求书中提出的本发明的范围。

Claims (15)

1.一种制作半导体器件的方法，包括：
提供载体；
提供半导体小片，所述半导体小片包括在所述半导体小片的表面之上形成的多个凸块；
将所述半导体小片安装到所述载体；
将封装剂沉积在所述半导体小片之上，包括在所述半导体小片的表面与所述载体之间；
去除所述载体；
在所述封装剂之上形成绝缘层；
去除所述绝缘层的一部分，以便露出所述凸块；以及
以缠绕配置在所述绝缘层之上形成第一导电层以呈现电感性质，其中所述第一导电层通过所述封装剂和所述绝缘层来与所述半导体小片分隔。
2.如权利要求1所述的方法，还包括：
形成第二导电层，所述第二导电层跟随所述绝缘层和凸块的轮廓。
3.如权利要求1所述的方法，其中，所述第一导电层与所述半导体小片分隔20-140微米。
4.一种制作半导体器件的方法，包括：
提供半导体小片；
在所述半导体小片的第一表面之上形成第一绝缘层；
在形成所述第一绝缘层之后，将封装剂沉积在所述半导体小片中与所述第一表面相对的第二表面之上；
在沉积所述封装剂之后，在所述半导体小片的所述第一表面之上形成第二绝缘层；以及
按照缠绕配置在所述第二绝缘层之上形成第一导电层以呈现电感性质，其中所述第一导电层通过所述第二绝缘层来与所述半导体小片分隔。
5.如权利要求4所述的方法，还包括：
在所述半导体小片的所述第一表面上形成电路；以及
在所述半导体小片的所述第一表面之上形成第二导电层，从而电连接所述第一导电层和所述电路。
6.如权利要求4所述的方法，还包括：将所述第一导电层部分设置在所述半导体小片的占用面积中。
7.如权利要求4所述的方法，还包括：在形成所述第二绝缘层之前去除所述第一绝缘层。
8.一种半导体器件，包括：
半导体小片；
在所述半导体小片的第一表面之上形成的第一绝缘层；
在所述半导体小片中与所述第一表面相对的第二表面之上沉积的封装剂；
在所述半导体小片的所述第一表面之上形成且形成到所述封装剂的空腔内的第二绝缘层；以及
按照缠绕配置在所述第二绝缘层之上形成以呈现电感性质的导电层，其中所述导电层与所述半导体小片分隔。
9.如权利要求8所述的半导体器件，其中，所述导电层与所述半导体小片分隔20-140微米。
10.如权利要求8所述的半导体器件，还包括：
通过所述第二绝缘层所形成的导电通孔。
11.如权利要求8所述的半导体器件，其中，所述导电层部分设置在所述半导体小片的占用面积中。
12.如权利要求8所述的半导体器件，还包括：设置在所述半导体小片与所述导电层之间的互连结构。
13.如权利要求1所述的方法，还包括：将所述第一导电层的一部分部分设置在所述半导体小片的占用面积中。
14.如权利要求4所述的方法，还包括：将导电栓塞形成在所述第一绝缘层中。
15.如权利要求4所述的方法，还包括：将互连结构形成在所述第一导电层之上。
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