TWI538124B - 形成在互連層之內與半導體晶粒垂直分離的電感器之半導體裝置和方法 - Google Patents

形成在互連層之內與半導體晶粒垂直分離的電感器之半導體裝置和方法 Download PDF

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TWI538124B
TWI538124B TW100144143A TW100144143A TWI538124B TW I538124 B TWI538124 B TW I538124B TW 100144143 A TW100144143 A TW 100144143A TW 100144143 A TW100144143 A TW 100144143A TW I538124 B TWI538124 B TW I538124B
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semiconductor die
layer
insulating layer
semiconductor
conductor
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TW100144143A
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TW201246476A (en
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林耀劍
陳康
方建敏
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史達晶片有限公司
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Description

形成在互連層之內與半導體晶粒垂直分離的電感器之半導體裝置和方法
本發明概略關於一種半導體裝置，並且尤其是有關一種形成在互連層內而與半導體晶粒垂直分離之電感器的半導體裝置及方法。
半導體裝置常見於當今的電子產品。半導體裝置在電氣元件的數量及密度上多所變化。離散半導體裝置通常含有某種類型的電氣元件，即如發光二極體(LED)、小型信號產生器、電阻器、電容器、電感器以及功率金屬氧化物半導體場效電晶體(MOSFET)。積體半導體裝置通常含有數百至數百萬個這種電氣元件。積體半導體裝置的範例包含微控制器、微處理器、電荷耦合裝置(CCD)、太陽能電池以及數位微映鏡裝置(DMD)。
半導體裝置可執行廣泛各種功能，像是信號處理、高速計算、電磁信號傳送與接收、電子裝置控制、陽光至電力之轉換處理，以及電視顯示器的視覺投影產生作業。半導體裝置可見於娛樂、通訊、電力轉換、網路、電腦及消費性產品的領域。半導體裝置亦可見於軍事應用項目、航空、車輛、工業用控制器以及辦公室設備。
半導體裝置是運用半導體材料的電氣性質。半導體材料的原子結構可供藉由施加電場或基極電流，或是透過摻雜處理，以操縱其導電性。摻雜處理可將雜質引入至該半導體材料內以供操縱並控制該半導體裝置的導體性。
半導體裝置可含有主動性和被動性的電氣結構。主動結構，包含二極體和場效電晶體，可控制電流的行流。藉由改變摻雜以及電場或基極電流施加的位準，該電晶體可促成或阻制電流的流動。而包含電阻器、電容器和電感器在內的被動結構則可產生為執行各種電氣功能所必要的電壓與電流間關係。這些被動與主動結構係經電氣連接以構成電路而可供該半導體裝置能夠執行高速計算以及其他的可用功能。
一般說來，半導體裝置是利用兩項複雜製程所製造，亦即前端製造與後端製造，而各者都可能牽涉到數以百計的步驟。前端製造牽涉到在半導體晶圓的表面上形成複數個晶粒。各個晶粒通常為等同，並且含有藉由以電氣方式連接多個主動及被動元件所構成的電路。後端製造則涉及到從所完工的晶圓單切出個別晶粒，並且進行晶粒封裝以提供結構支撐與環境隔離。
半導體製造的其一目標為產生更微小的半導體裝置。小型化裝置通常耗用較少電力、擁有較高效能並且能夠更加提升生產效率。此外，較微小的半導體裝置具有較小形跡，這對於微型終端產品而言確為所企求者。小型晶粒可藉由改善前端製程所達成，而獲致具備更小、更高密度之主動及被動元件的晶粒。後端製程則可藉由改善電氣互連及封裝材料以獲致具有較小形跡的半導體裝置封裝。
半導體製造的另一目標是在於生產具備更高效能的半導體裝置。可藉由構成能夠按照較高速度運作的主動元件來達到裝置效能的提升。在高頻應用項目裡，經常會將像是射頻(RF)無線通訊的積體被動裝置(IPD)納入在該半導體裝置之內。IPD的範例包含電阻器、電容器及電感器。典型的RF系統在一或更多個半導體封裝內需要多個IPD以利執行必要的電氣功能。
電感器則可形成於半導體晶粒內。然而積體晶粒電感器通常遭受到低Q因數的困擾，部分原因是渦流損失所導致。積體電感器會耗佔顯著的晶粒面積並且降低設計彈性。
在半導體裝置裡存在一種對於高Q因數電感器的需要。從而，在一具體實施例裡，本發明為一種製作半導體裝置的方法，其中包含下列步驟，即提供一載體；在該載體上構成一黏著層；提供一半導體晶粒，此者具有複數個經構成於該半導體晶粒之作用表面上的凸起；將該半導體晶粒架置於具有該等經部份地設置在該黏著層內之凸起的載體以於該半導體晶粒與該黏著層之間構成一間隔；將密封劑沉積在該半導體晶粒上以及該半導體晶粒與該黏著層間的間隔內；移除該載體及該黏著層以從該密封劑曝出該等凸起；在該密封劑上構成一絕緣層；以及在該絕緣層上按纏繞組態方式構成一第一導體層以展現電感性質並且電氣連接至該等凸起。該第一導體層具有距於該半導體晶粒而按如該間隔與該絕緣層內之密封劑所決定的分離。
在另一具體實施例裡，本發明為一種製作半導體裝置的方法，其中包含下列步驟，即提供一載體；提供一半導體晶粒；在該半導體晶粒之表面上構成一第一絕緣層；對該第一絕緣層施以鉛化；將該半導體晶粒架置於該載體；在該半導體晶粒上沉積一密封劑；移除該載體；在該半導體晶粒上構成一第二絕緣層；以及在該第二絕緣層上按纏繞組態方式構成一第一導體層以展現電感性質。該第一導體層具有距於該半導體晶粒而按如該等第一及第二絕緣層所決定的分離。
在另一具體實施例裡，本發明為一種製作半導體裝置的方法，其中包含下列步驟，即提供一半導體晶粒；在該半導體晶粒之第一表面上構成一第一絕緣層；在該半導體晶粒中相對於該第一表面之第二表面上沉積一密封劑；在該半導體晶粒之第一表面上構成一第二絕緣層；以及在該第二絕緣層上按纏繞組態方式構成一第一導體層以展現電感性質。該第一導體層具有距於該半導體晶粒的分離。
在另一具體實施例裡，本發明為一種半導體裝置，其中含有一半導體晶粒以及經構成於該半導體晶粒之第一表面上的第一絕緣層。一密封劑係經沉積於該半導體晶粒中相對於該第一表面的第二表面上。一第二絕緣層係經構成於該半導體晶粒之第一表面上。而在該第二絕緣層上則按纏繞組態方式構成一第一導體層以展現電感性質。該第一導體層具有距於該半導體晶粒的分離。
在後文說明中係按一或更多具體實施例並參照於各項圖式以敘述本發明，其中類似編號代表相同或相仿構件。本發明雖係按照為以達到本發明目的之最佳模式所描述，然熟諳本項技藝之人士將可瞭解所欲者係為以涵蓋可經納入在如後載申請專利範圍所定義之本發明精神與範疇內的替代、修改和等同項目，以及其等按照後文揭示說明與圖式所支持的等同項目。
半導體裝置通常是利用兩項複雜的製造程序所製成：前端製造及後端製造。前端製造牽涉到在半導體晶圓的表面上形成複數個晶粒。該晶圓上的各個晶粒含有主動及被動電氣元件，而該等元件係經電氣連接以構成功能性電路。像是電晶體及二極體之主動電氣元件擁有控制電流行流的能力。而像是電容器、電感器、電阻器及轉換器之被動電氣元件則可產生為執行電路功能所必要的電壓與電流間關係。
被動及主動元件是藉由包含摻雜、沉積、光微影、蝕刻及平坦化處理在內的一系列製程步驟所形成在該半導體晶圓的表面上。摻雜處理可藉由像是離子植入或熱性擴散的技術以將雜質引入至半導體材料之內。摻雜製程可修改主動裝置內之半導體材料的導電性、將半導體材料轉換成絕緣體，或者是回應於電場或基極電流以按動態方式改變半導體材料導體性。電晶體包含具備各式摻雜類型與程度而視需要所排置的範圍，藉以當施加該電場或基極電流時讓電晶體能夠促成或阻禁電流的行流。
主動及被動元件是由具備不同電氣性質的材料覆層所構成。該等覆層是藉由沉積技術所形成，而這些技術則是部份地基於所予沉積之材料的類型所決定。例如，薄膜沉積作業可能牽涉到化學氣相沉積(CVD)、物理氣相沉積(PVD)、電解塗鍍處理以及無電塗鍍製程。各個覆層通常係經樣式化以供構成主動元件、被動元件的局部，或者是該等元件之間的電氣連接。
可利用光微影技術以樣式化該等覆層，而這種技術牽涉到在所予樣式化之覆層上進行即如光阻物之光敏材料的沉積作業。利用光線即可將該樣式自光遮罩轉傳至該光阻物。該光阻物樣式中受照於光線的局部可利用溶劑加以移除，從而曝出所予樣式化之底置覆層的局部。然後移除該光阻物的其餘部分而留下樣式化覆層。或另者，有些類型的材料則是利用像是無電或電解塗鍍技術以藉由將材料直接沉積至由先前沉積/蝕刻製程所形成的區域或空處內所樣式化。
將薄膜材料沉積在既有樣式上可能會造成底置樣式誇大並且產生不均勻的平坦表面。為產生較小且較密集包集之主動及被動元件，均勻的平坦表面確屬必要。可利用平坦化作業以自晶圓的表面去除材料，同時產生均勻的平坦表面。平坦化作業牽涉到以拋光板進行晶圓表面拋光處理。在拋光過程中可將摩擦材料及侵蝕性化學藥劑添增至晶圓的表面處。合併的摩擦機械性動作及化學藥劑侵蝕作用可去除任何不規則拓樸性，從而獲致均勻的平坦表面。
後端製造是指將經拋光完工的晶圓切割或單切成個別晶粒，然後封裝該晶粒以予結構支撐和環境隔離。為進行晶粒單切，可沿該晶圓上稱為鋸切線道或刻劃線的非功能性範圍將晶圓予以劃割且斷折。可利用雷射切割機具或鋸切刀片對晶圓進行單切。在單切作業之後，即可將個別晶粒架置在一封裝基板上，此者含有腳針或接觸板以供互連於其他的系統元件。然後再將在該半導體晶粒上所形成的接觸板連接至該封裝內的接觸板。該等電氣連接可藉由焊料凸起、釘頭凸起、導體膏劑或接線連附所進行。可將密封劑或其他的鑄造材料沉積在該封裝上以提供實體支撐與電氣隔離。然後將該所完工封裝插入至一電氣系統內，而且其他的系統元件即能獲用該半導體裝置的功能性。
圖1說明一電子裝置50，其中具有晶片載體基板或印刷電路板(PCB)52，而該者含有複數個經架置於其表面上的半導體封裝。該電子裝置50可按照應用項目而定擁有單一類型的半導體封裝或是多種類型的半導體封裝。圖1中係為說明之目的而顯示不同類型的半導體封裝。
該電子裝置50可為運用該等半導體封裝以執行一或更多電氣功能的單立式系統。或另者，該電子裝置50可為一更大系統的子元件。例如，該電子裝置50可為行動電話、個人數位助理(PDA)、數位視訊相機(DVC)或其他電子通訊裝置的其中一部份。或另者，該電子裝置50可為圖形卡、網路介面卡，或是其他可供插設於電腦之內的信號處理機卡。該半導體封裝可包含微處理器、記憶體、應用特定積體電路(ASIC)、邏輯電路、類比電路、RF電路、離散裝置，或是其他的半導體晶粒或電氣元件。對於這些產品來說，若欲為市場所接受，則微小化和重量減輕確為重點。故而必須縮減半導體裝置之間的距離以利獲致更高密度。
在圖1中，PCB 52可供作為經架置於該PCB上之半導體封裝的結構支撐與電氣互連之通用基板。導體性信號跡線54係利用汽化作業、電解塗鍍、無電塗鍍、網版印刷或是其他的適當金屬沉積製程構成於該PCB 52的表面上或覆層內。信號跡線54提供該等半導體封裝、所架置元件與其他外部系統元件各者之間的電氣通訊。該等跡線54亦提供連至該等半導體封裝各者的電力和接地連接。
在一些具體實施例裡，半導體裝置具有兩種封裝層級。第一層級的封裝處理是一種將該半導體晶粒按照機械性和電氣性之方式接附至中介載體的技術。而第二層級的封裝處理則牽涉到將該中介載體以機械性和電氣性方式接附至PCB。在其他的具體實施例裡，半導體裝置可僅具有該第一層級封裝處理，其中晶粒是以機械性和電氣性的方式直接地架置於PCB。
為示範說明，在PCB 52上顯示有多種類型的第一層級封裝，包含線路連附封裝56及覆晶58。除此之外，在PCB 52上顯示有多種類型的第二層級封裝，包含焊球柵格陣列(BGA) 60、凸起晶片載體(BCC) 62、雙線內封裝64(DIP) 64、基面柵格陣列(LGA) 66、多晶片模組(MCM) 68、四側扁平無鉛封裝(QFN) 70以及四側扁平封裝72。根據系統需求而定，任何經組態設定具任何第一與第二層級封裝式樣之組合的半導體封裝組合，以及其他電子元件，皆可連接至PCB 52。在一些具體實施例裡，該電子裝置50含有單一個接附半導體封裝，而其他的具體實施例則運用多個互連封裝。藉由在單一基板上合併一或更多半導體封裝，製造廠商可將預製元件併入在電子裝置及系統之內。由於半導體封裝含有複雜的功能性，因此能夠利用較價廉元件及流線化製程來製造電子裝置。所獲裝置較不易於失效並且製造成本較低，故而消費者的價格成本較低。
圖2a-2c顯示示範性半導體封裝。圖2a說明經架置於PCB 52上之DIP 64的進一步細節。該半導體晶粒74含有一作用範圍，其內含有按如依據該晶粒之電氣設計而構成於該晶粒內且為電氣互連的主動裝置、被動裝置、導體層及介電層所實作之類比或數位電路。例如，該電路可含有一或更多經構成於該半導體晶粒74之作用範圍內的電晶體、二極體、電感器、電容器、電阻器以及其他的電路構件。接觸板76為一或更多像是鋁(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)或銀(Ag)的導體材料層，並且電氣連接至該半導體晶粒74之內所形成的一或更多電路構件。在組裝DIP 64的過程中，該半導體晶粒74係利用金-矽共晶層或者像是熱性環氧樹脂或環氧樹脂的黏著材料以架置於中介載體78。該封裝本體含有像是聚合物或陶瓷的絕緣封裝材料。該等導體引腳80及接線連附82提供該半導體晶粒74與PCB 52之間的電氣互連。該密封劑84係經沉積於該封裝上以藉由防止溼氣及粒子進入封裝內並污染晶粒74或接線連附82來提供環境保護。
圖2b說明經架置於PCB 52上之BCC 62的進一步細節。半導體晶粒88是利用底部填充或環氧樹脂黏著材料92以架置於載體90上。該等接線連附94提供該等接觸板96與98之間的第一層級封裝互連。鑄造化合物或密封劑100係經沉積在該半導體晶粒88及該等接線連附94上，藉以提供對於該裝置的實體支撐與電氣隔離。該等接觸板102是利用像是電解塗鍍或無電塗鍍的適當金屬沉積製程而構成於PCB 52的表面上藉以避免氧化。該等接觸板102係經電氣連接至PCB 52內的一或更多導體信號跡線54。在BCC 62的接觸板98與PCB 52的接觸板102之間構成有多個凸起104。
在圖2c中，半導體晶粒58是藉由覆晶式樣第一層級封裝以向下面朝該中介載體106的方式所架置。該半導體晶粒58的作用範圍108含有類比或數位電路，此等電路係按根據該晶粒之電氣設計而形成的主動裝置、被動裝置、導體層和介電層所實作。例如，該電路在該作用範圍108內可含有一或更多電晶體、二極體、電感器、電容器、電阻器以及其他的電路構件。該半導體晶粒58係透過凸起110電氣且機械性地連接至該載體106。
BGA 60是利用凸起112以BGA式樣第二層級封裝所電氣且機械性地連接至PCB 52。該半導體晶粒58透過該等凸起110、信號線114和凸起112以電氣性地連接至PCB 52內的導體信號跡線54。鑄造化合物或密封劑116係經沉積在該半導體晶粒58及該載體106上，藉以提供對於該裝置的實體支撐與電氣隔離。該覆晶半導體裝置可提供一條從該半導體晶粒58上之主動裝置至該PCB 52上之傳導軌線的微短導電路徑，藉以縮短信號傳播距離、降低電容值並且改善整體的電路效能。在另一具體實施例裡，該半導體晶粒58則是利用覆晶式樣第一層級封裝以機械性地且電氣性地直接連接至該PCB 52而無需中介載體106。
圖3a顯示擁有即如矽、鍺、砷化鎵、磷化銦或碳化矽之基底基板材料122的半導體晶圓120以供結構性支撐。複數個半導體晶粒或元件124係經形成於晶圓120上，並如前述般依鋸切線道126所分離。
圖3b顯示該半導體晶圓120之一局部的截面視圖。各個半導體晶粒124具有一背側表面128以及一作用表面130，此作用表面含有按如依據該晶粒之電氣設計與功能而構成於該晶粒內且為電氣互連的主動裝置、被動裝置、導體層及介電層所實作之類比或數位電路。例如，該電路可含有一或更多構成於該作用表面130內的電晶體、二極體和其他電路構件，藉以實作像是數位信號處理器(DSP)、ASIC、記憶體或是其他信號處理電路的類比電路或數位電路。該半導體晶粒124亦可含有即如電感器、電容器和電阻器的積體被動裝置(IPD)以供進行RF信號處理。在一具體實施例裡，該半導體晶粒124為覆晶類型的半導體晶粒。
導電層132是利用PVD、CVD、電解塗鍍及無電塗鍍製程或是其他適當的金屬沉積製程以構成於該作用表面130上。該導體層132可為Al、Cu、Sn、Ni、Au、Ag或是其他適當導電材料的覆層。該導體層132可運作如經電氣連接至該作用表面130上之電路的接觸板。而該等接觸板132上則形成有多個凸起134。
在圖3c中，該半導體晶圓120是利用鋸切刀片或雷射切割機具136經由鋸切線道126單切成個別的半導體晶粒124。
關聯於圖1及2a-2c，圖4a-4k顯示構成在互連層內而具有與該半導體晶粒垂直分離之電感器的程序。圖4a顯示一基板或載體140，其中含有像是矽、聚合物、氧化鈹的臨時性或可犧牲基底材料，或是其他適當的低成本、硬固性材料，以供結構性支撐。在該載體140上構成有介面層或雙側式條帶142以作為臨時性的黏著連附膜層或蝕刻停阻層。該介面層142上則形成一可穿透黏著層144。在一具體實施例裡，該可穿透黏著層144為B階段材料。
在圖4b裡，圖3a-3c的半導體晶粒124是利用撿拾及放置操作以安放且架置在該載體140上。凸起134係經部份地嵌入於該黏著層144內，藉以在該半導體晶粒124與該黏著層144之間留下間隔145，即如圖4c所示。在一具體實施例裡，該半導體晶粒124含有導電層146(稍後作為電感器橋接之用)以及類比和數位電路148作為該作用表面130的一部份，即如圖3b中所示。
絕緣或介電層150係利用PVD、CVD、網版印刷、旋轉塗鍍、噴灑塗鍍、燒結或熱性氧化作業以構成於該半導體晶粒124的作用表面130及導體層146上。該絕緣層150含有多個二氧化矽(SiO2)、氮化矽(Si3N4)、氮氧化矽(SiON)、五氧化二鉭(Ta2O5)、氧化鋁(Al2O3)、聚醯亞胺、苯並環丁烯(BCB)、聚苯并噁唑(PBO)或是其他適當介電材料的覆層。
在圖4d中，密封劑或鑄造化合物152是利用膏劑印刷、沖壓鑄造、傳動鑄造、液體密封劑鑄造、真空疊覆、旋轉塗鍍或是其他適當的塗佈器以沉積在該半導體晶粒124及該黏著層144上。該密封劑152是在該半導體晶粒124與該黏著層144之間延伸。在一具體實施例裡，該密封劑152是利用鑄模底部填充(MUF)製程在凸起134附近於壓力下自配送針管射入至該半導體晶粒124與該黏著層144之間的間隔145內。真空輔助器可吸汲該密封劑152以有助於均勻的塗佈結果。該密封劑152可為聚合物合成材料，即如具有填充物的環氧樹脂、具有填充物的環氧丙烯酸酯或是具有適當填充物的聚合物。該密封劑152為非導體性，並且環境保護該半導體裝置不致受到外部構件及污染物所影響。由於該半導體晶粒124與該黏著層間的間隔145之故，因此該密封劑152在該半導體晶粒124下方的厚度為15-90微米(μm)。
圖4e顯示選擇性背側研磨作業，其中可由研磨器156移除該密封劑152之表面154的一部份，藉此平坦化該密封劑並且曝出該半導體晶粒124的背側表面128以供進行靜電放電(ESD)控制。
在圖4f裡，可藉由化學蝕刻、機械剝除、CMP、機械研磨、熱性烘烤、雷射掃瞄或濕性剝離以移除該等載體140、介面層142與黏著層144，藉以從該密封劑152曝出該等凸起134。
在圖4g裡，絕緣或介電層158是利用PVD、CVD、網版印刷、旋轉塗鍍、噴灑塗鍍、燒結或熱性氧化作業以構成於該密封劑152中相反於該表面154的表面160上。該絕緣層158含有一或更多SiO2、Si3N4、SiON、Ta2O5、Al2O3、聚醯亞胺、BCB、PBO或是其他適當介電材料的覆層。該絕緣層158的厚度為5-50μm。該絕緣層158之一局部係經去除以曝出該等凸起134。
在圖4h中，導電層162是利用樣式化和金屬沉積製程，像是PVD、CVD、濺鍍、電解塗鍍與無電塗鍍處理，共形地施佈於該絕緣層158及所曝出凸起134上。該導體層162可為Al、Cu、Sn、Ni、Au、Ag或是其他適當導電材料的覆層。該導體層162可為依照該絕緣層158之廓型的種源層，並且納入在該絕緣層的所移除局部內而位於該等所曝出凸起134附近。在另一具體實施例裡，該導體層162為具有黏著層、阻障層以及種源或濕性層的多金屬堆疊。該黏著層係經構成於該絕緣層158和該等凸起134上，並且可為鈦(Ti)、氮化鈦(TiN)、鎢化鈦(TiW)、鋁(Al)或鉻(Cr)。該阻障層係經構成於該黏著層上，並且可為Ni、NiV、鉑(Pt)、鈀(Pd)、TiW或銅化鉻(CrCu)。該阻障層禁阻Cu擴散進入到該晶粒的作用區域內。該種源層係經構成於該阻障層上，並且可為Cu、Ni、NiV、Au或Al。
在該導體層162上構成有一絕緣或光阻層164。該絕緣層164的一局部係藉蝕刻製程所移除以樣式化該等導體層166a-166h。而在該絕緣層164的所移除局部上可藉由電解塗鍍、無電塗鍍或是其他適當金屬沉積製程以沉積導電材料。其餘的絕緣層164以及位在該絕緣層下方的導體層162是藉由蝕刻製程所移除，而留下該等導體層166a-166h以作為一或更多Al、Cu、Sn、Ni、Au、Ag或者其他適當導電材料的覆層，即如圖4i中所示。該等導體層166a-166h可根據該半導體晶粒124的設計與功能而為電氣共通或電氣隔離。
該導體層166的個別區段在平面視圖上可為纏繞或捲圈形式，藉以產生或展現電感性質。例如該等導體層166d、166e、166f及166g可組成纏繞或螺旋式電感器支翼，即如圖4j所示。該等電感器支翼166d-166g係經設置在一互連層裡，此者係部份地或全然地位於該半導體晶粒124之形跡的內部。該等電感器支翼166d-166g是經由導體層162、凸起134以及接觸板132所電氣連接至該導體層146，而此導體層運作如電感器橋接以利將該等電感器支翼電氣連接至該類比及數位電路148。由於位在該半導體晶粒124下方的密封劑152厚度(15-90μm)及該絕緣層158的厚度(5-50μm)之故，因此該等電感器支翼166d-166g是以20-140μm與該半導體晶粒124分離。在一具體實施例裡，該等電感器支翼166d-166g是以100μm與該半導體晶粒124分離。該等電感器支翼166d-166g與該半導體晶粒124之間的間隔可降低渦流損失並且提高Q因數。
在圖4k裡，絕緣或鈍化層168是利用PVD、CVD、網版印刷、旋轉塗鍍、噴灑塗鍍、燒結或熱性氧化作業以構成於該絕緣層158及該導體層166之上。該絕緣層168含有一或更多SiO2、Si3N4、SiON、Ta2O5、Al2O3或是其他具有類似絕緣及結構性質之材料，的覆層。該絕緣層168的一部份係經移除以曝出該等導體層166a、166c及166h。
在該等所曝出導體層166a、166c及166h上可利用汽化作業、電解塗鍍、無電塗鍍、焊球滴落或是網版印刷製程以沉積一導電凸起材料。該凸起材料可為Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料以及該等的組合，並具有選擇性的通流溶液。例如，該凸起材料可為共晶Sn/Pb、高鉛焊料，或是無鉛焊料。該凸起材料係利用適當的接附或連附製程以連附於該導體層166。在一具體實施例裡，該凸起材料是藉由將該材料加熱至高於其熔點所回流，藉以構成球形焊球或凸起170。在一些應用項目中，該等凸起170係經二次回流以供改善對該導體層166的電氣接觸。該等凸起亦可為壓縮連附於該導體層166。該等凸起170是代表一種能夠在該導體層166上形成的互連結構類型。該互連結構亦可運用釘頭凸起、微型凸起或者其他的電氣互連。
圖5a-5f顯示該基板或載體172的另一具體實施例，其中含有像是矽、聚合物、氧化鈹的臨時性或可犧牲基底材料，或是其他適當的低成本、硬固性材料，以供結構性支撐。在圖5a中，在該載體172上構成有介面層或雙側式條帶173以作為臨時性的黏著連附膜層或蝕刻停阻層。
複數個半導體晶粒174是以晶圓形式所提供，即類似於圖3a者。各個半導體晶粒174具有一背側表面178以及一作用表面180，此作用表面含有按如依據該晶粒之電氣設計與功能而構成於該晶粒內且為電氣互連的主動裝置、被動裝置、導體層及介電層所實作之類比或數位電路。例如，該電路可含有一或更多構成於該作用表面180內的電晶體、二極體和其他電路構件，藉以實作像是DSP、ASIC、記憶體或是其他信號處理電路的類比電路或數位電路。該半導體晶粒174亦可含有即如電感器、電容器和電阻器的IPD以供進行RF信號處理。
導電層182是利用PVD、CVD、電解塗鍍及無電塗鍍製程或是其他適當的金屬沉積製程以構成於該作用表面180上。該導體層182可為Al、Cu、Sn、Ni、Au、Ag或是其他適當導電材料的覆層。該導體層182稍後是作為連至該類比及數位電路188的電感器橋接而成為該作用表面180的一部份。
絕緣或介電層190係利用PVD、CVD、網版印刷、旋轉塗鍍、噴灑塗鍍、燒結或熱性氧化作業以構成於該半導體晶粒124的作用表面180及導體層182上。該絕緣層190含有一或更多SiO2、Si3N4、SiON、Ta2O5、Al2O3、聚醯亞胺、BCB、PBO或是其他適當介電材料的覆層。
導電層192是利用PVD、CVD、電解塗鍍及無電塗鍍製程或是其他適當的金屬沉積製程以構成於該絕緣層190上。該導體層192可為Al、Cu、Sn、Ni、Au、Ag或是其他適當導電材料的覆層。該導體層192係經電氣連接至該導體層182和該類比及數位電路188。
在192及190上藉由Cu塗鍍、焊球接附或接線連附處理而形成一導體插頭196。絕緣或介電層194係經構成於該絕緣層190及該導體層192上，並且在當按晶圓形式時進行切割之前，會先利用PVD、CVD、網版印刷、旋轉塗鍍、噴灑塗鍍、疊覆、鑄造、燒結或熱性氧化以曝出該導體層196，參見圖3a-3b。該絕緣層194含有一或更多SiO2、Si3N4、SiON、Ta2O5、Al2O3、聚醯亞胺、BCB、PBO或是其他適當介電材料的覆層。在一具體實施例裡，該絕緣層194的厚度為15-90μm，並且含有像是具有填充物之聚合物材料的高電阻材料。
或另者，在當按晶圓形式時進行切割之前，會先利用雷射鑽鑿、機械鑽鑿或者深層反應離子蝕刻(DRIE)以構成複數個透過該絕緣層194的通道。該等通道向下延伸至該導體層192。該等通道可利用電解塗鍍、無電塗鍍製程或是其他適當的金屬沉積製程填充以Al、Cu、Sn、Ni、Au、Ag、Ti、W、聚矽或其他適當導電材料，藉以構成z方向垂直的互連導體插頭196。該等導體插頭196係經電氣連接至該導體層192。該導體層192可對於該等導體插頭196提供對準容忍度。
在切割該晶圓之後，即類似於圖3c，可利用撿拾及放置操作以將該半導體晶粒174安放且架置在該載體172及該介面層173上。該絕緣層194可在該半導體晶粒174與該介面層173之間提供15-90μm的間距或分離198，即如圖5b所示。
在圖5c中，密封劑或鑄造化合物200是利用膏劑印刷、沖壓鑄造、傳動鑄造、液體密封劑鑄造、真空疊覆、旋轉塗鍍或是其他適當的塗佈器以沉積在該半導體晶粒174及該介面層173上。該密封劑200可為聚合物合成材料，即如具有填充物的環氧樹脂、具有填充物的環氧丙烯酸酯或是具有適當填充物的聚合物。該密封劑200為非導體性，並且環境保護該半導體裝置不致受到外部構件及污染物所影響。
可在一選擇性背側研磨操作中移除該密封劑200的一部分表面202，即類似於圖4e者，藉以平坦化該密封劑並且曝出該半導體晶粒174的背側表面178俾進行ESD控制。
在圖5d裡，可藉由化學蝕刻、機械剝除、CMP、機械研磨、熱性烘烤、雷射掃瞄或濕性剝離來移除該等載體172與介面層173以曝出該等導體插頭196。
絕緣或介電層204是利用PVD、CVD、網版印刷、旋轉塗鍍、噴灑塗鍍、燒結或熱性氧化作業以構成於該密封劑200中相反於該表面202的表面205上。該絕緣層204含有一或更多SiO2、Si3N4、SiON、Ta2O5、Al2O3、聚醯亞胺、BCB、PBO或是其他適當介電材料的覆層。該絕緣層204的厚度為5-50μm。該絕緣層204之一局部係經去除以曝出該等導體插頭196。
在圖5e中，導電層206是利用電解塗鍍、無電塗鍍製程或其他適當金屬沉積製程以構成於該絕緣層204上而作為節段206a-206h。該導體層206a-206h含有Al、Cu、Sn、Ni、Au、Ag或是其他適當導電材料的覆層。導體層206a-166h可根據該半導體晶粒174的設計與功能而為電氣共通或電氣隔離。
該導體層206的個別區段在平面視圖上可為纏繞或捲圈形式，藉以產生或展現電感性質。例如，該等導體層206d、206e、206f及206g可組成纏繞或螺旋式電感器支翼，即類似於圖4j者。該等電感器支翼206d-206g係經設置在一互連層裡，此者係部份地或全然地位於該半導體晶粒174之形跡的內部。該等電感器支翼206d-206g是經由該等導體插頭196和該導體層192所電氣連接至該導體層182，而此導體層運作如電感器橋接以利將該等電感器支翼電氣連接至該等類比及數位電路188。由於該絕緣層194的厚度(15-90μm)以及該絕緣層204的厚度(5-50μm)之故，因此該等電感器支翼206d-206g是以20-140μm與該半導體晶粒174分離。在一具體實施例裡，該等電感器支翼206d-206g是以100μm與該半導體晶粒174分離。該等電感器支翼206d-206g與該半導體晶粒174之間的分離可降低渦流損失並且提高Q因數。
在圖5f裡，絕緣或鈍化層208是利用PVD、CVD、網版印刷、旋轉塗鍍、噴灑塗鍍、燒結或熱性氧化作業以構成於該絕緣層204及該導體層206之上。該絕緣層208含有一或更多SiO2、Si3N4、SiON、Ta2O5、Al2O3或是其他具有類似絕緣及結構性質之材料，的覆層。該絕緣層208的一部份係經移除以曝出該等導體層206a、206c及206h。
在該等所曝出導體層206a、206c及206h上可利用汽化作業、電解塗鍍、無電塗鍍、焊球滴落或是網版印刷製程以沉積一導電凸起材料。該凸起材料可為Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料以及該等的組合，並具有選擇性的通流溶液。例如，該凸起材料可為共晶Sn/Pb、高鉛焊料，或是無鉛焊料。該凸起材料係利用適當的接附或連附製程以連附於該導體層206。在一具體實施例裡，該凸起材料是藉由將該材料加熱至高於其熔點所回流，藉以構成球形焊球或凸起210。在一些應用項目中，該等凸起210係經二次回流以供改善對該導體層206的電氣接觸。該等凸起亦可為壓縮連附於該導體層206。該等凸起210是代表一種能夠在該導體層206上形成的互連結構類型。該互連結構亦可運用釘頭凸起、微型凸起或者其他的電氣互連。
圖6a-6g顯示該基板或載體212的另一具體實施例，其中含有像是矽、聚合物、氧化鈹的臨時性或可犧牲基底材料，或是其他適當的低成本、硬固性材料，以供結構性支撐。在圖6a中，在該載體212上構成有介面層或雙側式條帶213以作為臨時性的黏著連附膜層或蝕刻停阻層。
複數個半導體晶粒214是以晶圓形式所提供，即類似於圖3a者。各個半導體晶粒214具有一背側表面218以及一作用表面220，此作用表面含有按如依據該晶粒之電氣設計與功能而構成於該晶粒內且為電氣互連的主動裝置、被動裝置、導體層及介電層所實作之類比或數位電路。例如，該電路可含有一或更多構成於該作用表面220內的電晶體、二極體和其他電路構件，藉以實作像是DSP、ASIC、記憶體或是其他信號處理電路的類比電路或數位電路。該半導體晶粒214亦可含有即如電感器、電容器和電阻器的IPD以供進行RF信號處理。
導電層222是利用PVD、CVD、電解塗鍍及無電塗鍍製程或是其他適當的金屬沉積製程以構成於該作用表面220上。該導體層222可為Al、Cu、Sn、Ni、Au、Ag或是其他適當導電材料的覆層。該導體層222稍後是作為連至該類比及數位電路228的電感器橋接而成為該作用表面220的一部份。
絕緣或介電層230係利用PVD、CVD、網版印刷、旋轉塗鍍、噴灑塗鍍、燒結或熱性氧化作業以構成於該半導體晶粒214的作用表面220及導體層222上。該絕緣層230含有一或更多SiO2、Si3N4、SiON、Ta2O5、Al2O3、聚醯亞胺、BCB、PBO或是其他適當介電材料的覆層。
導電層232是利用PVD、CVD、電解塗鍍及無電塗鍍製程或是其他適當的金屬沉積製程以構成於該絕緣層230上。該導體層232可為Al、Cu、Sn、Ni、Au、Ag或是其他適當導電材料的覆層。該導體層232係經電氣連接至該導體層222。
在當按晶圓形式進行切割之前會先於該絕緣層230及該導體層232上構成一犧牲層234，即如圖3a-3b所示。該犧牲層234含有一或更多乾性膜層及背側研磨條帶、液體光阻或是保護膏劑的覆層。在一具體實施例裡，該絕緣層234的厚度為15-90μm。
在切割該晶圓之後，即類似於圖3c，可利用撿拾及放置操作以將該半導體晶粒214安放且架置在該載體212及該介面層213上。該犧牲層234可在該半導體晶粒214與該介面層213之間提供15-90μm的間距或分離238，即如圖6b所示。
在圖6c中，密封劑或鑄造化合物240是利用膏劑印刷、沖壓鑄造、傳動鑄造、液體密封劑鑄造、真空疊覆、旋轉塗鍍或是其他適當的塗佈器以沉積在該半導體晶粒214及該介面層213上。該密封劑240可為聚合物合成材料，即如具有填充物的環氧樹脂、具有填充物的環氧丙烯酸酯或是具有適當填充物的聚合物。該密封劑240為非導體性，並且環境保護該半導體裝置不致受到外部構件及污染物所影響。
可在一選擇性背側研磨操作中移除該密封劑242的一部分表面240，即類似於圖4e者，藉以平坦化該密封劑並且曝出該半導體晶粒214的背側表面218俾進行ESD控制。
在圖6d裡，可藉由化學蝕刻、機械剝除、CMP、機械研磨、熱性烘烤、雷射掃瞄或濕性剝離以移除該等載體212、介面層213與黏著層234，留下位在該半導體晶粒214下方的腔洞246。
在圖6e裡，絕緣或介電層252是利用PVD、CVD、網版印刷、旋轉塗鍍、噴灑塗鍍、燒結或熱性氧化作業以構成於該密封劑240中相反於該表面242的表面254上且進入該腔洞246。該絕緣層252含有一或更多SiO2、Si3N4、SiON、Ta2O5、Al2O3、聚醯亞胺、BCB、PBO或是其他適當介電材料的覆層。在一具體實施例裡，該絕緣層252係按如單層或雙層介電材料所沉積。該絕緣層252的厚度為5-50μm。該絕緣層252之一局部係經去除以曝出該導體層232。
在圖6f中，導電層256是利用電解塗鍍、無電塗鍍製程或其他適當金屬沉積製程以構成於該絕緣層252上而作為節段256a-256h。該導體層256a-256h含有Al、Cu、Sn、Ni、Au、Ag或是其他適當導電材料的覆層。例如，該導體層256可含有Ti/Cu或TiW/Cu的種源層，而經選擇性Cu塗鍍並隨後進行種源層濕性蝕刻。該等導體層256b及256f延伸進入該絕緣層252的所移除局部而接觸到該導體層232。該等導體層256a-256h可根據該半導體晶粒214的設計與功能而為電氣共通或電氣隔離。
該導體層256的個別區段在平面視圖上可為纏繞或捲圈形式，藉以產生或展現電感性質。例如該等導體層256d、256e、256f及256g可組成纏繞或螺旋式電感器支翼，即類似於圖4j者。該等電感器支翼256d-256g係經設置在一互連層裡，此者係部份地或全然地位於該半導體晶粒214之形跡的內部。該等電感器支翼256d-256g是經由該導體層232所電氣連接至該導體層222，而此導體層運作如電感器橋接以將該等電感器支翼電氣連接至該等類比及數位電路228。由於該絕緣層252的厚度之故，因此該等電感器支翼256d-256g是以25-160μm與該半導體晶粒214分離。在一具體實施例裡，該等電感器支翼256d-256g是以120μm與該半導體晶粒214分離。該等電感器支翼256d-256g與該半導體晶粒214之間的分離可降低渦流損失並且提高Q因數。
在圖6g裡，絕緣或鈍化層258是利用PVD、CVD、網版印刷、旋轉塗鍍、噴灑塗鍍、燒結或熱性氧化作業以構成於該絕緣層252及該導體層256之上。該絕緣層258含有一或更多SiO2、Si3N4、SiON、Ta2O5、Al2O3或是其他具有類似絕緣及結構性質之材料，的覆層。該絕緣層258的一部份係經移除以曝出該等導體層256a、256c及256h。
在該等所曝出導體層256a、256c及256h上可利用汽化作業、電解塗鍍、無電塗鍍、焊球滴落或是網版印刷製程以沉積一導電凸起材料。該凸起材料可為Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料以及該等的組合，並具有選擇性的通流溶液。例如，該凸起材料可為共晶Sn/Pb、高鉛焊料，或是無鉛焊料。該凸起材料係利用適當的接附或連附製程以連附於該導體層256。在一具體實施例裡，該凸起材料是藉由將該材料加熱至高於其熔點所回流，藉以構成球形焊球或凸起260。在一些應用項目中，該等凸起260係經二次回流以供改善對該導體層256的電氣接觸。該等凸起亦可為壓縮連附於該導體層256。該等凸起260是代表一種能夠在該導體層256上形成的互連結構類型。該互連結構亦可運用釘頭凸起、微型凸起或者其他的電氣互連。
圖7a-7e顯示另一具體實施例，此者續接自圖6d，而具有藉由剝除該犧牲保護層234以曝出該半導體晶粒214的腔洞246。當按晶圓形式時，可在該所曝出導體層232上於該腔洞246內利用汽化作業、電解塗鍍、無電塗鍍、焊球滴落或是網版印刷製程以沉積一導電凸起材料，即如圖7a所示。該凸起材料可為Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料以及該等的組合，並具有選擇性的通流溶液。例如，該凸起材料可為共晶Sn/Pb、高鉛焊料，或是無鉛焊料。該凸起材料係利用適當的接附或連附製程以連附於該導體層232。在一具體實施例裡，該凸起材料是藉由將該材料加熱至高於其熔點所回流，藉以構成球形焊球或凸起270。在一些應用項目中，該等凸起270係經二次回流以供改善對該導體層232的電氣接觸。該等凸起亦可為壓縮連附於該導體層232。該等凸起270是代表一種能夠在該導體層232上形成的互連結構類型。該互連結構亦可運用釘頭凸起、微型凸起或者其他的電氣互連。
圖7b顯示一具有研磨條帶262和保護襯墊264的具體實施例，而該等在當按晶圓形式時構成於該等凸起270及該絕緣層230上。在一具體實施例裡，該條帶262可為耐熱樹脂。該背側研磨條帶262以及該保護襯墊264可在背側研磨與切割作業的過程中提供結構性支撐，像是圖3c及4e所示者。
在圖7c裡，絕緣或介電層272是利用PVD、CVD、網版印刷、旋轉塗鍍、噴灑塗鍍、燒結或熱性氧化作業以構成於該密封劑240中相反於該表面242的表面274上而進入該腔洞246且在該等凸起270上。該絕緣層272含有一或更多SiO2、Si3N4、SiON、Ta2O5、Al2O3、聚醯亞胺、BCB、PBO或是其他適當介電材料的覆層。在一具體實施例裡，該絕緣層272係按如單層或雙層介電材料所沉積。該絕緣層272的厚度為5-50μm。該絕緣層272之一局部係經去除以曝出該等凸起270。
在圖7d中，導電層276是利用電解塗鍍、無電塗鍍製程或其他適當金屬沉積製程以構成於該絕緣層272上而作為節段276a-276h。該導體層276a-276h含有Al、Cu、Sn、Ni、Au、Ag或是其他適當導電材料的覆層。例如，該導體層276可含有Ti/Cu或TiW/Cu的種源層，而經選擇性Cu塗鍍並隨後進行種源層濕性蝕刻。該等導體層276b及276f延伸進入該絕緣層272的所移除局部而接觸到該等凸起270。該等導體層276a-276h可根據該半導體晶粒214的設計與功能而為電氣共通或電氣隔離。
該導體層276的個別區段在平面視圖上可為纏繞或捲圈形式，藉以產生或展現電感性質。例如該等導體層276d、276e、276f及276g可組成纏繞或螺旋式電感器支翼，即類似於圖4j者。該等電感器支翼276d-276g係經設置在一互連層裡，此者係部份地或全然地位於該半導體晶粒214之形跡的內部。該等電感器支翼276d-276g是經由該等凸起270及該導體層232所電氣連接至該導體層222，而此導體層運作如電感器橋接以利將該等電感器支翼電氣連接至該等類比及數位電路228。由於該絕緣層272的厚度之故，因此該等電感器支翼276d-276g是以25-160μm與該半導體晶粒214分離。在一具體實施例裡，該等電感器支翼276d-276g是以120μm與該半導體晶粒214分離。該等電感器支翼276d-276g與該半導體晶粒214之間的分離可降低渦流損失並且提高Q因數。
在圖7e裡，絕緣或鈍化層278是利用PVD、CVD、網版印刷、旋轉塗鍍、噴灑塗鍍、燒結或熱性氧化作業以構成於該絕緣層272及該導體層276之上。該絕緣層278含有一或更多SiO2、Si3N4、SiON、Ta2O5、Al2O3或是其他具有類似絕緣及結構性質之材料的覆層。該絕緣層278的一部份係經移除以曝出該等導體層276a、276c及276h。
在該等所曝出導體層276a、276c及276h上可利用汽化作業、電解塗鍍、無電塗鍍、焊球滴落或是網版印刷製程以沉積一導電凸起材料。該凸起材料可為Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料以及該等的組合，並具有選擇性的通流溶液。例如，該凸起材料可為共晶Sn/Pb、高鉛焊料，或是無鉛焊料。該凸起材料係利用適當的接附或連附製程以連附於該導體層276。在一具體實施例裡，該凸起材料是藉由將該材料加熱至高於其熔點所回流，藉以構成球形焊球或凸起280。在一些應用項目中，該等凸起280係經二次回流以供改善對該導體層276的電氣接觸。該等凸起亦可為壓縮連附於該導體層276。該等凸起280是代表一種能夠在該導體層276上形成的互連結構類型。該互連結構亦可運用釘頭凸起、微型凸起或者其他的電氣互連。
雖既已詳細說明本發明具體實施例，然熟諳本項技藝之人士將能瞭解確可對該等具體實施例進行修改及調適而不致悖離按如後載申請專利範圍中所陳述的本發明範疇。
50．．．電子裝置
52．．．印刷電路板
54．．．信號跡線
56．．．接線連附封裝
58．．．覆晶
60．．．焊球柵格陣列
62．．．凸起晶片載體
64．．．雙線內封裝
66．．．基面柵格陣列
68．．．多晶片模組
70．．．四側扁平無鉛封裝
72．．．四側扁平封裝
74．．．半導體晶粒
76．．．接觸板
78．．．中介載體
80．．．導體引腳
82．．．接線連附
84．．．密封劑
88．．．半導體晶粒
90．．．載體
92．．．黏著劑材料
94．．．接線連附
96．．．接觸板
98．．．接觸板
100．．．鑄造化合物或密封劑
102．．．接觸板
104．．．凸起
106．．．載體
108．．．作用範圍
110．．．凸起
112．．．凸起
114．．．信號線路
116．．．鑄造化合物或密封劑
120．．．晶圓
122．．．基底基板材料
124．．．半導體晶粒或元件
126．．．鋸切線道
128．．．背側表面
130．．．作用表面
132．．．導電層
134．．．接觸板
136．．．鋸切刀片或雷射切割機具
140．．．載體
142．．．介面層
144．．．黏著層
145．．．間隔
146．．．導體層
148．．．類比及數位電路
150．．．絕緣或介電物
152．．．密封劑或鑄造化合物
154．．．表面
156．．．研磨器
158．．．絕緣層
160．．．表面
162．．．導體層
164．．．絕緣或光阻層
166a-h．．．導體層
168．．．絕緣或鈍化層
170．．．球形焊球或凸起
172．．．載體
173．．．雙側式條帶
174．．．半導體晶粒
178．．．背側表面
180．．．作用表面
182．．．導體層
188．．．類比及數位電路
190．．．絕緣或介電層
192．．．導體層
194．．．絕緣或介電層
196．．．導體插頭
198．．．間距或分離
200．．．密封劑或鑄造化合物
202．．．表面
204．．．絕緣或介電層
205．．．表面
206．．．導體層
206a-h．．．導體層
208．．．絕緣層
210．．．球形焊球或凸起
212．．．載體
213．．．介面層或雙側式條帶
214．．．半導體晶粒
218．．．背側表面
220．．．作用表面
222．．．導體層
228．．．類比及數位電路
230．．．絕緣或介電層
232．．．導體層
234．．．犧牲層
238．．．間距或分離
240．．．密封劑
242．．．表面
246．．．腔洞
252‧‧‧絕緣或介電層
254‧‧‧表面
256‧‧‧導體層
256a-h‧‧‧導體層
258‧‧‧絕緣層
260‧‧‧球形焊球或凸起
270‧‧‧球形焊球或凸起
272‧‧‧絕緣或介電層
274‧‧‧表面
276‧‧‧導體層
276a-h‧‧‧導體層
278‧‧‧絕緣或鈍化層
280‧‧‧球形焊球或凸起
圖1顯示一PCB，此者具有經架置於其表面上的不同類型封裝；
圖2a-2c顯示經架置於該PCB之半導體封裝的進一步細節；
圖3a-3c顯示一半導體晶圓，此者具有複數個由鋸切線道所分離的半導體晶粒；
圖4a-4k顯示構成在互連層內而具有與該半導體晶粒垂直分離之電感器的程序；
圖5a-5f顯示構成在互連層內而具有與該半導體晶粒垂直分離之電感器的第二具體實施例；
圖6a-6g顯示構成在互連層內而具有與該半導體晶粒垂直分離之電感器的第三具體實施例；以及
圖7a-7e顯示構成在互連層內而具有與該半導體晶粒垂直分離之電感器的第四具體實施例。
124．．．半導體晶粒或元件
130．．．作用表面
132．．．導電層
134．．．接觸板
146．．．導體層
148．．．類比及數位電路
150．．．絕緣或介電物
158．．．絕緣層
160．．．表面
162．．．導體層
166a-h．．．導體層
168．．．絕緣或鈍化層
170．．．球形焊球或凸起

Claims (15)

  1. 一種製造半導體裝置之方法，其中包含：提供一半導體晶粒，此者具有複數個經構成於該半導體晶粒之第一表面上的凸起；將密封劑沉積在與該半導體晶粒的該第一表面相對之該半導體晶粒的第二表面上；在該密封劑和該等凸起上構成一絕緣層；以及在該絕緣層上按纏繞組態方式構成一第一導體層以用該第一導體層展現電感性質，而該第一導體層具有距於該半導體晶粒而按如該密封劑與該絕緣層所決定的分離。
  2. 如申請專利範圍第1項所述之方法，進一步包含：移除形成在該等凸起上的該絕緣層之一局部；以及在構成該第一導體層之前，該絕緣層及該等凸起上構成一第二導體層。
  3. 如申請專利範圍第1項所述之方法，其中該第一導體層以20-140微米與該半導體晶粒分離。
  4. 如申請專利範圍第1項所述之方法，進一步包含：提供可穿透黏著層；以及在沉積該密封劑之前，在該可穿透黏著層內部份地沉積該等凸起。
  5. 一種製造半導體裝置之方法，其中包含：提供一半導體晶粒；在該半導體晶粒的作用表面上構成一第一絕緣層；在該半導體晶粒和該第一絕緣層上沉積一密封劑； 在該密封劑和該半導體晶粒的該作用表面上構成一第二絕緣層；以及在該第二絕緣層的表面上按纏繞組態方式構成一第一導體層以展現電感性質，該第二絕緣層的表面與具有該第一導體層的該半導體晶粒相對。
  6. 如申請專利範圍第5項所述之方法，進一步包含：在該半導體晶粒上構成電路；以及在該半導體晶粒上構成電氣連接該等電路的第二導體層。
  7. 如申請專利範圍第5項所述之方法，進一步包含將該第一導體層的電感器支翼部份地設置在該半導體晶粒的形跡內。
  8. 如申請專利範圍第5項所述之方法，進一步包含：在構成該第二絕緣層之前，移除該第一絕緣層。
  9. 如申請專利範圍第5項所述之方法，進一步包含在該半導體晶粒上形成複數個凸起。
  10. 如申請專利範圍第5項所述之方法，進一步包含透過該第二絕緣層所形成的導體通道。
  11. 一種半導體裝置，其中包含：一半導體晶粒；一第一絕緣層，此者係經構成在該半導體晶粒的第一表面上；一密封劑，此者係經沉積於與該半導體晶粒的該第一表面相對之該半導體晶粒的第二表面上； 一第二絕緣層，此者係經構成在該第一絕緣層、該密封劑以及該半導體晶粒的該第一表面上；以及一導體層，此者係在該第二絕緣層上按纏繞組態方式所構成以用該導體層展現電感性質，該導體層藉由該第一絕緣層和該第二絕緣層而與該半導體晶粒分離。
  12. 如申請專利範圍第11項所述之半導體裝置，其中該導體層以20-140微米與該半導體晶粒分離。
  13. 如申請專利範圍第11項所述之半導體裝置，進一步包含在該第一絕緣層中設置的導體插頭。
  14. 如申請專利範圍第11項所述之半導體裝置，進一步包含在該導體層中形成且在該半導體晶粒的形跡內部份地設置的電感器支翼。
  15. 如申請專利範圍第11項所述之半導體裝置，進一步包含透過該第二絕緣層所形成的導體通道。
TW100144143A 2010-12-10 2011-12-01 形成在互連層之內與半導體晶粒垂直分離的電感器之半導體裝置和方法 TWI538124B (zh)

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