TWI567866B - 半導體元件以及使用提供結構支撐之封膠劑來形成具有直通矽晶穿孔的互連結構之方法 - Google Patents

半導體元件以及使用提供結構支撐之封膠劑來形成具有直通矽晶穿孔的互連結構之方法 Download PDF

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TWI567866B
TWI567866B TW099114343A TW99114343A TWI567866B TW I567866 B TWI567866 B TW I567866B TW 099114343 A TW099114343 A TW 099114343A TW 99114343 A TW99114343 A TW 99114343A TW I567866 B TWI567866 B TW I567866B
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conductive
forming
substrate
layer
interconnect structure
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TW099114343A
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TW201101428A (en
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納薩彭 蘇司王上尚爾
潘迪Ｃ 瑪莉姆蘇
丘在勳
葛蘭 歐曼丹
吳興華
量王 囯
瓊斯Ａ 卡普拉斯
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史達晶片有限公司
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Description

半導體元件以及使用提供結構支撐之封膠劑來形成具有直通矽晶穿孔的互連結構之方法
本發明大體上關於半導體元件，且更特別地，關於一種半導體元件以及使用提供結構支撐之封膠劑來形成具有直通矽晶穿孔之互連結構之方法。
半導體元件常見於現代電子產品中。半導體元件在電性構件之數量及密度上有所變化。分立式半導體元件大體上包含某類型電性構件，例如，發光二極體(LED)、小訊號電晶體、電阻器、電容器、電感器及功率式金氧半導體場效電晶體(MOSFET)。整合式半導體元件典型地包含成千上萬個電性構件。整合式半導體元件範例包含微控制器、微處理機、電荷耦合元件(CCD)、太陽能蓄電池及數位微型反射鏡元件(DMD)。
半導體元件執行廣泛功能，例如，高速計算、傳輸並接收電磁波訊號、控制電子元件、轉換光線成為電力及產生電視顯示器之視覺投影。半導體元件見於娛樂、通訊、電力轉換、網路、電腦及消費產品領域中。半導體元件也見於軍事應用、航空、汽車、工業控制及辦公設備中。
半導體元件利用半導體材料之電特性。半導體材料之原子結構讓它的導電性可受到施加電場或透過摻雜製程來操控。摻雜技術將雜質引入該半導體材料內以操控該半導體元件之導電性。
一半導體元件包含主動及被動電性結構。包含二極體及場效電晶體之主動結構控制電流流動。藉由改變摻雜位準及施加電場或基極電流，該電晶體不是增加就是限制該電流流動。包含電阻器、電容器及電感器之被動結構在執行各種電性功能所需電壓與電流間產生某種關係。該些被動及主動結構被電性連接以執行高速計算和其它有用功能。
半導體元件大體上為使用二複合製程，也就是前端製程和後端製程來製造之，每一個製程可能涉及數百個步驟。前端製程涉及在一半導體晶圓表面上形成複數個晶粒。每一個晶粒典型地一模一樣且內含電性連接之主動及被動構件所形成之電路。後端製程涉及單粒化來自該已完成晶圓之個別晶粒並構裝該晶粒以提供結構支撐及環境隔離。
半導體製程之一目標為製造較小的半導體元件。較小的元件典型地消耗較少電力、具有較高執行效率且可更有效率地被製造。此外，較小的半導體元件具有一較小佔用空間，其可期待提供較小的終端產品。一較小晶粒尺寸可經由改善該前端製程以產生內含較小、較高密度主動和被動構件之晶粒而得。後端製程可經由改善電性連接和構裝材料而產生具有一較小佔用空間之半導體元件構裝。
包含多個層級(立體元件整合)上之半導體元件之半導體構裝及一外部印刷電路板(PCB)或基板之間之電性互連典型地利用接線、貫穿導通孔(THV)或直通矽晶穿孔(TSV)來達成。接線需要額外構裝區域以在該些導線中形成轉彎處。為了使用貫穿導通孔或直通矽晶穿孔來產生電性互連，一暫時載體被黏結至該構裝基板以在形成該些貫穿導通孔或直通矽晶穿孔時提供結構支撐。對於例如小於250微米(μm)之薄晶圓而言，過度操控會引起斷裂和脫落。該暫時載體增添製造成本。用於該暫時載體之黏結材料將處理溫度限制至約攝氏200度。
在一實施例中，本發明為一種半導體元件之製造方法，包括之步驟為提供一暫時基板及在該基板第一側中形成一通孔。該通孔部分延伸至該基板。該方法近一步包含之步驟為在該通孔中形成一第一絕緣層、將一導電材料沉積於該通孔中以形成一直通矽晶穿孔、在該基板第一側上形成一第一互連結構、將一半導體晶粒或構件安裝至該第一互連結構、將一封膠劑沉積於該第一互連結構和半導體晶粒或構件上、移除與該基板第一側相對之基板第二側中之一部分以減少它的厚度並露出該直通矽晶穿孔及在該基板第二側上形成一第二互連結構。該第二互連結構為電性連接至該直通矽晶穿孔。
在另一實施例中，本發明為一種半導體元件之製造方法，包括之步驟為提供一基板、在該基板第一側中形成一通孔、將一導電材料沉積於該通孔中以形成一導電通孔、在該基板第一側上形成一第一互連結構、將一半導體晶粒或構件安裝至該第一互連結構、將一封膠劑沉積於該第一互連結構和半導體晶粒或構件上、移除與該基板第一側相對之基板第二側中之一部分以減少它的厚度並露出該導電通孔及在該基板第二側上形成一第二互連結構。該第二互連結構為電性連接至該導電通孔。
在另一實施例中，本發明為一種半導體元件之製造方法，包括之步驟為提供一基板、形成一貫穿該基板第一側之導電通孔、在該基板第一側上形成一第一互連結構、將一半導體晶粒或構件安裝至該第一互連結構、將一封膠劑沉積於該第一互連結構和半導體晶粒或構件上及移除與該基板第一側相對之基板第二側中之一部分以減少它的厚度並露出該導電通孔。
在另一實施例中，本發明為一種半導體元件，包括一基板及貫穿該基板第一側所形成之導電通孔。一第一互連結構形成於該基板第一側上。一半導體晶粒或構件被安裝至該第一互連結構。一封膠劑沉積於該第一互連結構和半導體晶粒或構件上。該封膠劑在與該基板第一側相對之基板第二側中之一部分被移除以減少它的厚度並露出該導電通孔時支撐該半導體元件。一第二互連結構形成於該基板第二側上。該第二互連結構為電性連接至該導電通孔。
本發明下列說明參考圖形描述於下列說明之一或更多實施例中，其中類似編號代表相同或類似構件。雖然本發明以最佳模式來描述以達成本發明目的，然而那些熟知此項技術之人士應理解到本發明要涵蓋下列揭示及圖式所支持附上之申請專利範圍及它們等效例所定義之本發明精神及範圍所包含之替代例、修改例和等效例。
半導體元件大體上為使用二複合製程：前端製程和後端製程來製造之。前端製程涉及在一半導體晶圓表面上形成複數個晶粒。在該晶圓上之每一個晶粒內含主動及被動電性構件，其為電性連接以形成功能性電性電路。例如電晶體及二極體之主動電性構件具有控制電流流動之能力。例如電容器、電感器、電阻器和變壓器之被動電性構件在執行電性電路功能所需電壓和電流間產生某種關係。
被動及主動構件為經由包含摻雜、沉積、微影成像、蝕刻及平坦化之一系列製程而形成於該半導體晶圓表面上。摻雜技術經由例如離子植入或熱擴散類之技術將雜質引入該半導體材料中。該摻雜製程改變主動元件內部半導體材料之導電性，以轉換該半導體材料成為一絕緣體、導體，或動態地改變該半導體材料導電性以回應一電場或基極電流。電晶體內含依需求安排之各種摻雜類型與程度之區域以使該電晶體可依據該電場或基極電流來增進或限制電流流動。
主動及被動構件為由具有不同電特性之材料層所形成。該些材料層可由欲沉積之材料類型所部分決定之各類沉積技術來形成之。例如，薄膜沉積技術可包含化學氣相沉積(CVD)、物理氣相沉積(PVD)、電鍍及無電鍍各製程。每一層大體上經由圖案化而形成主動構件、被動構件、或構件間之電性連接部分。
該些材料層可使用微影成像技術來圖案化之，其包含將例如光阻劑之感光性材料沉積於欲圖案化之材料層上。使用光將一圖案自一光罩轉印至該光阻劑。該光阻劑圖案中遇到光的部分使用一溶劑來移除之，以露出下層中欲圖案化的部分。該光阻劑其餘部分被移除，留下一圖案化層。替代性地，一些材料類型為經由直接沉積材料於使用例如無電鍍及電鍍類技術之先前沉積/蝕刻製程所形成之區域或孔隙中而進行圖案化。
將一薄膜材料沉積於一現成圖案上可擴大該下層圖案並產生一不均勻平坦表面。一均勻平坦表面被需要以產生較小且更密集封裝之主動及被動構件。平坦化技術可被使用以移除該晶圓表面之材料並產生一均勻平坦表面。平坦化技術涉及以一拋光墊片來拋光該晶圓表面。一研磨材料及腐蝕性化學藥品於拋光期間被添加至該晶圓表面。結合研磨之機械性動作及化學藥品之腐蝕性動作可移除任何不規則拓樸，產生一均勻平坦表面。
後端製程指切割或單粒化該已完成晶圓成為該個別晶粒並接著構裝該晶粒以提供結構支撐及環境隔離。為了單粒化該晶粒，將該晶圓沿著所謂割鋸道或劃線之晶圓無功能區域做記號並切開。使用一雷射切割工具或鋸片切割該晶圓成晶粒。單粒化後，個別晶粒被安裝至包含接腳或接觸墊片以與其它系統構件互相連接之構裝基板上。該半導體晶粒上所形成之接觸墊片接著被連接至該構裝內之接觸墊片。該電性連接可搭配錫球凸塊、短柱凸塊、導電膏、或接線來進行之。一封膠劑或其它封膠材料被沉積在該構裝上以提供實體支撐及電性隔離。該已完成構裝接著被插入一電性系統中，且該半導體元件功能對於其它系統構件是有用的。
圖1說明具有在表面上安裝有複數個半導體構裝之晶片載體基板或印刷電路板52之電子元件50。電子元件50可具有某半導體構裝類型或多種半導體構裝類型，視應用而定。基於說明目的，不同半導體構裝類型示於圖1中。
電子元件50可為使用該些半導體構裝來執行一或更多電性功能之獨立系統。替代性地，電子元件50可為一較大型系統之子構件。例如，電子元件50可為能夠插入一電腦內之繪圖卡、網路界面卡或其它訊號處理卡。該半導體構裝可包含微處理器、記憶體、特殊用途積體電路(ASIC)、邏輯電路、類比電路、射頻電路、離散元件或其它半導體晶粒或電性構件。
在圖1中，為了安裝在該印刷電路板上之半導體構裝之結構支撐及電性互連，印刷電路板52提供一總基板。傳導訊號軌跡線54使用蒸鍍製程、電鍍製程、無電鍍製程、網印製程或其它合適金屬沉積製程來形成於印刷電路板52之某一表面上或多層內。訊號軌跡線54提供該些半導體構裝、安裝構件及其它外部系統構件中每一個間之電性通訊。軌跡線54也提供至該些半導體構裝中每一個之電力及接地連接。
在一些實施例中，一半導體元件具有二構裝級。第一級構裝為用以機械性和電性地黏結該半導體晶粒至一中介載體之技術。第二級構裝涉及機械性和電性地黏結該中介載體至該印刷電路板。在其它實施例中，一半導體元件可以只具有該第一級構裝，其中，該晶粒經由機械性和電性方式直接安裝至該印刷電路板。
基於說明目的，包含打線接合構裝56及覆晶構裝58之一些第一級構裝類型被示於印刷電路板52上。此外，包含錫球陣列(BGA)構裝60、凸塊晶片載體(BCC)62、雙列式構裝(DIP)、平面陣列(LGA)構裝66、多晶片模組(MCM)構裝68、四邊扁平無引腳構裝(QFN)70及四邊扁平構裝72之一些第二級構裝類型顯示安裝於印刷電路板52上。依據該些系統需求，搭配第一及第二級構裝型式之任意結合以及其它電子構件所建構之半導體構裝之任意結合可被連接至印刷電路板52。在一些實施例中，電子元件50包含一單黏結半導體構裝，而其它實施例需要多個連接構裝。經由結合單一基板上之一或更多半導體構裝，製造商可整合預製構件至電子元件及系統中。因為該些半導體構裝包含複雜功能，故可使用較便宜構件及一流線型製程來製造電子元件。所產元件較不可能失敗，且對於消費者而言製造成本較低而使所產元件較便宜。
圖2a-2c顯示示範性半導體構裝。圖2a說明安裝在印刷電路板52上之雙列式構裝64之進一部細部。半導體晶粒74包含一內含類比或數位電路之作用區域，該些電路被配置為形成於該晶粒內並根據該晶粒之電性設計進行電性互連之主動元件、被動元件、導電層和介電層。例如，該電路可包含一或更多電晶體、二極體、電感器、電容器、電阻器和形成於該半導體晶粒74之作用區域內之其它電路構件。接觸墊片76為例如鋁(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)或銀(Ag)中之一或更多導電材料層，且被電性連接至形成於半導體晶粒74內之電路構件。在組合雙列式構裝64期間，半導體晶粒74使用一金矽合金層或例如熱環氧樹脂類之黏接材料來安裝至一中介載體78。該構裝主體包含例如聚合物或陶瓷類之絕緣構裝材料。導線80及接線82提供半導體晶粒74及印刷電路板52間之電性互連。封膠劑84被沉積在該構裝上以阻止濕氣和微粒進入該構裝並污染晶粒74或接線82而提供環境保護。
圖2b說明安裝於印刷電路板52上之凸塊晶片載體62之進一步細部。半導體晶粒88使用一底部填膠或環氧樹脂黏接材料92來安裝於載體90上。接線94提供接觸墊片96及98間之第一級封裝互連。封膠化合物或封膠劑100被沉積於半導體晶粒88及接線94上以提供該元件實體支撐和電性隔離。接觸墊片102為使用例如電鍍或無電鍍之合適金屬沉積製程來形成於印刷電路板52之表面上以阻止氧化作用。接觸墊片102被電性連接至印刷電路板52之一或更多傳導訊號軌跡線54。凸塊104為形成於凸塊晶片載體62之接觸墊片98及印刷電路板52之接觸墊片102之間。
在圖2c中，半導體晶粒58為面向下安裝至具有一覆晶式第一級構裝之中介載體106。半導體晶粒58之作用區域108包含根據該晶粒電性設計所形成做為主動元件、被動元件、導電層和介電層而配置之類比或數位電路。例如，該電路可包含一或更多電晶體、二極體、電感器、電容器、電阻、及作用區域108內之其它電路構件。半導體晶粒58為透過凸塊110電性及機械性地連接至載體106。
錫球陣列構裝60使用凸塊112以電性及機械性地連接至具有一錫球陣列式第二級構裝之印刷電路板52。半導體晶粒58為透過凸塊110、訊號線114和凸塊112來電性連接至印刷電路板52之傳導訊號軌跡線54。一封膠化合物或封膠劑116被沉積於半導體晶粒58及載體106上以提供該元件實體支撐和電性隔離。該覆晶半導體元件提供自半導體晶粒58上之主動元件至印刷電路板52上之傳導軌跡線之一短導電路徑，用以減少訊號傳送距離、降低電容並改進整體電路執行效率。在另一實施例中，可不用中介載體106而使用覆晶式第一級構裝方式將該半導體晶粒58機械性及電性地直接連接至印刷電路板52。
圖3a-3h說明一種使用提供結構支撐之封膠劑來形成用於立體元件之具有直通矽晶穿孔之互連結構之方法。在圖3a中，一半導體晶圓118包含利用矽、聚合物、聚合物複合材料、金屬、陶瓷、玻璃、玻璃環氧化物、氧化鈹或用於結構支撐之其它合適低成本硬式材料之底材所製造之基板。替代性地，該基板可為例如鍺、砷化鎵、磷化銦或碳化矽類之半導體底材。複數個半導體晶粒可使用如上所述之半導體製程來形成於基板上。每一個半導體晶粒包含一內含類比或數位電路之作用區域120，該些電路被配置為形成於該晶粒內並根據該晶粒之電性設計及功能進行電性互連之主動元件、被動元件、導電層和介電層。例如，該電路可包含一或更多電晶體、二極體和形成於作用區域120內之其它電路構件以配置例如數位訊號處理器(DSP)、特殊用途積體電路、記憶體或其它訊號處理電路之基頻類比電路或數位電路。該半導體晶粒也可包含用於射頻(RF)訊號處理之整合被動元件(IPD)，例如，電感器、電容器和電阻器。
包含於半導體晶圓118內之整合被動元件提供例如共振器、高通濾波器、低通濾波器、帶通濾波器、對稱性高品質因數共振變壓器、匹配網路及調諧電容器類之高頻應用所需之電性特徵曲線。該些整合被動元件可充當前端無線射頻構件使用，其可被定位在該天線及收發器之間。該電感器可為一高達100千兆赫操作之高品質因數平衡-不平衡變換器、變壓器或線圈。在一些應用中，多個平衡-不平衡變換器形成於同一基板上以進行多頻段操作。例如，二或更多平衡-不平衡變換器被使用於行動電話或其它全球行動通訊系統(GSM)之四頻段中，每一個平衡-不平衡變換器專門提供該四頻元件中之一頻段操作。一典型射頻系統在一或更多半導體構裝中需要多個整合被動元件及其它高頻電路以執行所需之電性功能。
複數個通孔使用例如深反應式離子蝕刻(DRIE)之雷射鑽孔或蝕刻製程來形成於半導體晶圓118中。一絕緣層121被形成以沿著該些通孔之側壁和底部排列。該絕緣層121可為二氧化矽(SiO2)、氮化矽(Si3N4)、氮氧化矽(SiON)、五氧化二鉭(Ta2O5)、氧化鋁(Al2O3)、聚醯亞胺、苯環丁烯(BCB)、聚苯噁唑(PBO)或其它合適介電材料中其中一層或更多層。該絕緣層121使用物理氣相沉積、化學氣相沉積或熱氧化製程來形成之。
使用物理氣相沉積、化學氣相沉積、濺鍍、電鍍、無電鍍製程或其它合適金屬沉積製程將一導電材料122沉積於絕緣層121上之通孔中。導電材料122可為鋁、銅、錫、鎳、金、銀、鎢、多晶矽或其它合適導電材料中其中一層或更多層。該些通孔中之導電材料122充當導電直通矽晶穿孔作用。
在圖3b中，一導電層124為使用物理氣相沉積、化學氣相沉積、濺鍍、電鍍、無電鍍製程或其它合適金屬沉積製程來形成於直通矽晶穿孔122及半導體晶圓118上。導電層124可為鋁、銅、錫、鎳、金、銀或其它合適導電材料中其中一層或更多層。導電層124中之個別部分可依據該半導體元件之功能而為共電性或電性隔離。
一絕緣或保護層126形成於導電層124及半導體晶圓118之作用表面120上。該絕緣層126可為二氧化矽、氮化矽、氮氧化矽、五氧化二鉭、氧化鋁或具有類似絕緣特性之其它材料中其中一層或更多層。該絕緣層126使用物理氣相沉積、化學氣相沉積、印刷、旋塗、噴塗、燒結或熱氧化製程來形成之。以一蝕刻製程移除一部分絕緣層126而露出導電層124。
一導電層128使用物理氣相沉積、化學氣相沉積、濺鍍、電鍍、無電鍍製程或其它合適金屬沉積製程來形成於導電層124及絕緣層126上。導電層128可為鋁、銅、錫、鎳、金、銀或其它合適導電材料中其中一層或更多層。導電層128中之個別部分可依據該半導體元件之功能而為共電性或電性隔離。
一絕緣或保護層130形成於導電層128及絕緣層126上。該絕緣層130可為二氧化矽、氮化矽、氮氧化矽、五氧化二鉭、氧化鋁或具有類似絕緣特性之其它材料中其中一層或更多層。該絕緣層130使用物理氣相沉積、化學氣相沉積、印刷、旋塗、噴塗、燒結或熱氧化製程來形成之。以電漿或化學蝕刻製程移除一部分絕緣層130而露出導電層128。
導電柱或杆132形成於導電層128上。導電柱132可為銅、鋁、鎢、金、焊錫或其它合適導電材料。在一實施例中，該些導電柱132可為銅且以一電鍍製程形成之。一厚光阻層被沉積於絕緣層130和導電層128上。該光阻層可為一液體或具有15至130微米厚度之乾式薄膜。可施用二光阻層以得到期待厚度。在一實施例中，導電柱具有2-120微米之高度。該光阻層為使用微影成像技術進行圖案化。使用電鍍製程將銅沉積於該光阻層之圖案化通孔中。該光阻層被剝離並留下個別導電柱132。在另一實施例中，焊料圓球或短柱凸塊可被形成於導電層128上。
一絕緣或保護層134形成於導電柱132四周。該絕緣層134可為二氧化矽、氮化矽、氮氧化矽、五氧化二鉭、氧化鋁或具有類似絕緣特性之其它材料中其中一層或更多層。該絕緣層134使用物理氣相沉積、化學氣相沉積、印刷、旋塗、噴塗、燒結或熱氧化製程來形成之。以一蝕刻製程移除一部分絕緣層134而露出導電柱132。
在圖3c中，一導電層136使用物理氣相沉積、化學氣相沉積、濺鍍、電鍍、無電鍍製程或其它合適金屬沉積製程來形成於導電柱132上。導電層136可為鋁、銅、錫、鎳、金、銀或其它合適導電材料中其中一層或更多層。導電層136為與導電柱132進行電性接觸之凸塊下金屬化層(UBM)。凸塊下金屬化層136可為具有黏接層、阻障層及晶種或濕潤層之多金屬堆疊。該黏接層形成於導電柱132上且可為鈦、氮化鈦(TiN)、鈦鎢(TiW)、鋁或鉻(Cr)。該阻障層形成於該黏接層上且可由鎳、鎳釩(NiV)、鉑(Pt)、鈀(Pd)、鈦鎢或鉻銅(CrCu)所構成。該阻障層禁止銅擴散進入該晶粒之作用區域內。該晶種層可為銅、鎳、鎳釩、金或鋁。該晶種層形成於該阻障層上且充當導電柱132及接下來之凸塊或其它互連結構間之中間導電層。凸塊下金屬化層136提供一低電阻互連給導電柱132，以及對焊料擴散和提供焊料濕潤能力之晶種層之阻障。
一導電材料使用蒸鍍、電鍍、無電鍍、錫球滴落、或網印製程來沉積於凸塊下金屬化層136上。該導電材料可為鋁、錫、鎳、金、銀、鉛、鉍、銅、焊錫及上述之結合，加上一選擇性助焊劑材料。例如，該導電材料可為共晶錫/鉛、高鉛焊錫或無鉛焊錫。使用一合適黏接或黏結製程將該導電材料黏結至凸塊下金屬化層136。在一實施例中，該導電材料經由將該材料加熱超過它的熔點而進行回焊以形成圓球或凸塊138。在一些應用中，凸塊138被回焊一第二時間以改進對凸塊下金屬化層136之電性接觸。該些凸塊也可被壓縮黏結至凸塊下金屬化層136。凸塊138代表可被形成於凸塊下金屬化層136上之某類型互連結構。該互連結構也可使用接線、導電膏、短柱凸塊、微小凸塊或其它電性互連。
每一個半導體晶粒140具有冶金性和電性地連接至凸塊138之接觸墊片142。每一個半導體晶粒140包含一內含類比或數位電路之作用區域，該些電路配置為形成於該晶粒內並根據該晶粒之電性設計及功能進行電性互連之主動元件、被動元件、導電層和介電層。該半導體晶粒也可包含用於射頻訊號處理之整合被動元件。使用黏結物146將一被動元件或構件144結構性和電性地連接至凸塊下金屬化層136。半導體晶粒140和被動元件144、結合形成於作用區域120中之整合被動元件提供一立體半導體結構。
該半導體元件被膠封以在額外互連結構形成期間保護該元件並提供堅固的結構支撐。圖3d顯示使用一錫膏印刷、壓縮成型、轉注成型、液體封膠成型或其它合適塗抹器來沉積於圖3c所述結構上之封膠劑或封膠化合物150。封膠劑150可為環氧樹脂、環氧丙烯酯、聚合物或聚合複合材料。封膠劑150為無導電性且在環境上保護該半導體元件隔離外部構件及污染。
在圖3e中，半導體晶圓118被反轉且背部表面152之厚度為經由機械研磨、化學機械拋光、濕式蝕刻、乾式蝕刻、電漿蝕刻或另一薄化製程降低之。既然半導體晶圓118被封膠劑150所覆蓋，該結構為夠堅固，足以降低基板厚度至小於300微米。在一實施例中，該基板厚度被降低至10-50微米。一暫時載體或卷帶並不需要，此因封膠劑150提供支撐以維持該元件結構上的完整性之故，即使該降低之基板厚度亦然。
在圖3f中，一絕緣或保護層154形成於背部表面152和直通矽晶穿孔122上。該絕緣層154可為二氧化矽、氮化矽、氮氧化矽、五氧化二鉭、氧化鋁或具有類似絕緣特性之其它材料中其中一層或更多層。該絕緣層154使用物理氣相沉積、化學氣相沉積、印刷、旋塗、噴塗、燒結或熱氧化製程來形成之。以一蝕刻製程移除一部分絕緣層154而露出直通矽晶穿孔122。
一導電層156使用物理氣相沉積、化學氣相沉積、濺鍍、電鍍、無電鍍製程或其它合適金屬沉積製程來形成於直通矽晶穿孔122及絕緣層154上。導電層156可為鋁、銅、錫、鎳、金、銀或其它合適導電材料中其中一層或更多層。導電層156為與直通矽晶穿孔122進行電性接觸之凸塊下金屬化層。
在第3g圖中，一導電材料使用蒸鍍、電鍍、無電鍍、錫球滴落、或網印製程來沉積於凸塊下金屬化層156上。該導電材料可為鋁、錫、鎳、金、銀、鉛、鉍、銅、焊錫及上述之結合，加上一選擇性助焊劑材料。例如，該導電材料可為共晶錫/鉛、高鉛焊錫或無鉛焊錫。使用一合適黏接或黏結製程將該導電材料黏結至凸塊下金屬化層156。在一實施例中，該導電材料經由將該材料加熱超過它的熔點而進行回焊以形成圓球或凸塊158。在一些應用中，凸塊158被回焊一第二時間以改進對凸塊下金屬化層136之電性接觸。該些凸塊也可被壓縮黏結至凸塊下金屬化層156。凸塊158代表可被形成於凸塊下金屬化層156上之某類型互連結構。該互連結構也可使用接線、導電膏、短柱凸塊、微小凸塊或其它電性互連。
在圖3h中，半導體晶圓118再度被反轉並被單粒化成半導體元件160，其使用凸塊158來冶金性及電性地連接至印刷電路板168之接觸墊片166。半導體晶粒140和被動元件144以及作用區域120中之被動和主動元件透過凸塊138和158、凸塊下金屬化層136和156、直通矽晶穿孔122、導電柱132、黏結物146與導電層124和128來電性連接至印刷電路板168。
該封膠製程在額外互連結構形成期間使該基板或晶圓具有結構性堅固。該封膠劑可背部研磨以實際降低它的厚度。至印刷電路板168之電性連接為利用直通矽晶穿孔122來產生於該晶圓背部上，藉此降低矽面積和構裝尺寸並增加元件執行效率。該封膠劑消除至一暫時載體之黏結及移除之需求、降低製造成本、減少斷裂和脫落、簡化操控並可有較高處理溫度。在該基板背部上至該印刷電路板之電性連接降低矽面積及相關構裝尺寸和厚度。
形成立體元件之互連結構之另一實施例使用圖3a-3d中之製程。據此，直通矽晶穿孔122、導電層124和128、凸塊下金屬化層136、導電柱132、凸塊138、半導體晶粒140、被動元件144、黏結物146及絕緣層126、130和134已被形成於半導體晶圓118上。封膠劑150被沉積於該結構122-146上以在額外互連結構形成期間提供結構支撐。
在圖4a中，半導體晶圓118被反轉且背部表面152之厚度為經由機械研磨、化學機械拋光、濕式蝕刻、乾式蝕刻、電漿蝕刻或另一薄化製程降低之。既然半導體晶圓118被封膠劑150所覆蓋，該結構為夠堅固，足以降低基板厚度至小於300微米。在一實施例中，該基板厚度被降低至10-50微米。一暫時載體或卷帶並不需要，此因封膠劑150提供支撐以維持該元件結構上的完整性之故，即使該降低之基板厚度亦然。
一絕緣或保護層170形成於背部表面152和直通矽晶穿孔122上。該絕緣層170可為二氧化矽、氮化矽、氮氧化矽、五氧化二鉭、氧化鋁或具有類似絕緣特性之其它材料中其中一層或更多層。該絕緣層170使用物理氣相沉積、化學氣相沉積、印刷、旋塗、噴塗、燒結或熱氧化製程來形成之。以一蝕刻製程移除一部分絕緣層170而露出直通矽晶穿孔122。
一導電層172使用物理氣相沉積、化學氣相沉積、濺鍍、電鍍、無電鍍製程或其它合適金屬沉積製程來形成於直通矽晶穿孔122及絕緣層170上。導電層172可為鋁、銅、錫、鎳、金、銀或其它合適導電材料中其中一層或更多層。導電層172為與直通矽晶穿孔122進行電性接觸之重分配層(RDL)。重分配層172擴增直通矽晶穿孔122之電連接性。
在第4b圖中，一絕緣或保護層174形成於絕緣層170和重分配層172上。該絕緣層174可為二氧化矽、氮化矽、氮氧化矽、五氧化二鉭、氧化鋁或具有類似絕緣特性之其它材料中其中一層或更多層。該絕緣層174使用物理氣相沉積、化學氣相沉積、印刷、旋塗、噴塗、燒結或熱氧化製程來形成之。以一蝕刻製程移除一部分絕緣層174而露出重分配層172。
一導電層176使用物理氣相沉積、化學氣相沉積、濺鍍、電鍍、無電鍍製程或其它合適金屬沉積製程來形成於重分配層172及絕緣層174上。導電層176可為鋁、銅、錫、鎳、金、銀或其它合適導電材料中其中一層或更多層。導電層176為與重分配層172進行電性接觸之凸塊下金屬化層。
在圖4c中，一導電材料為使用蒸鍍、電鍍、無電鍍、錫球滴落或網印製程來沉積於凸塊下金屬化層176上。該導電材料可為鋁、錫、鎳、金、銀、鉛、鉍、銅、焊錫及上述之結合，加上一選擇性助焊劑材料。例如，該導電材料可為共晶錫/鉛、高鉛焊錫或無鉛焊錫。使用一合適黏接或黏結製程將該導電材料黏結至凸塊下金屬化層176。在一實施例中，該導電材料經由將該材料加熱超過它的熔點而進行回焊以形成圓球或凸塊178。在一些應用中，凸塊178被回焊一第二時間以改進對凸塊下金屬化層176之電性接觸。該些凸塊也可被壓縮黏結至凸塊下金屬化層176。凸塊178代表可被形成於凸塊下金屬化層176上之某類型互連結構。該互連結構也可使用接線、導電膏、短柱凸塊、微小凸塊或其它電性互連。
在圖4d中，半導體晶圓118再度被反轉並被單粒化成半導體元件180，其使用凸塊178來冶金性及電性地連接至印刷電路板188之接觸墊片186。半導體晶粒140和被動元件144以及作用區域120中之被動和主動元件透過凸塊138和158、重分配層172、直通矽晶穿孔122、凸塊下金屬化層136和156、導電柱132、黏結物146與導電層124和128來電性連接至印刷電路板188。
該封膠製程在額外互連結構形成期間使該基板或晶圓具有結構性堅固。該封膠劑可背部研磨以實際降低它的厚度。至印刷電路板188之電性連接為利用直通矽晶穿孔122來產生於該晶圓背部上，藉此降低矽面積和構裝尺寸並增加元件執行效率。該封膠劑消除至一暫時載體之黏結及移除之需求、降低製造成本、減少斷裂和脫落、簡化操控並可有較高處理溫度。在該基板背部上至該印刷電路板之電性連接降低矽面積及相關構裝尺寸和厚度。
儘管本發明一或更多實施例已被詳加說明，熟知此項技術之人士會理解到對那些實施例之修正和改寫可被進行而不偏離下列申請專利範圍所提之本發明範圍。
50．．．電子元件
52．．．印刷電路板
54．．．軌跡線
56．．．打線接合構裝
58．．．覆晶構裝
60．．．錫球陣列構裝
62．．．凸塊晶片載體
64．．．雙列式構裝
66．．．平面陣列構裝
68．．．多晶片模組構裝
70．．．四邊扁平無引腳構裝
72．．．四邊扁平構裝
74．．．半導體晶粒
76．．．接觸墊片
78．．．中介載體
80．．．導線
82．．．接線
84．．．封膠劑
88．．．半導體晶粒
90．．．載體
92．．．底部填膠或環氧樹脂黏接材料
94．．．接線
96．．．接觸墊片
98．．．接觸墊片
100．．．封膠化合物或封膠劑
102．．．接觸墊片
104．．．凸塊
106．．．載體
108．．．作用區域
110．．．凸塊
112．．．凸塊
114．．．訊號線
116．．．封膠化合物或封膠劑
118．．．半導體晶圓
120．．．作用表面
121．．．絕緣層
122．．．導電層
124．．．導電層
126．．．絕緣或保護層
128．．．導電層
130．．．絕緣或保護層
132．．．導電柱或杆
134．．．絕緣層
136．．．導電層
138．．．圓球或凸塊
140．．．半導體晶粒
142．．．接觸墊片
144．．．被動元件或構件
146．．．黏結物
150．．．封膠劑或封膠化合物
152．．．背部表面
154．．．絕緣或保護層
156．．．導電層
158．．．圓球或凸塊
160．．．半導體元件
166．．．接觸墊片
168．．．印刷電路板
170．．．絕緣或保護層
172．．．導電層
174．．．絕緣或保護層
176．．．導電層
178．．．圓球或凸塊
180．．．半導體元件
186．．．接觸墊片
188．．．印刷電路板
圖1說明在表面上安裝有各類型構裝之印刷電路板。
圖2a-2c說明安裝至該印刷電路板之代表性半導體構裝之進一步細部。
圖3a-3h說明一種使用提供結構支撐之封膠劑來形成一具有直通矽晶穿孔之互連結構以用於立體元件之方法。
圖4a-4d說明一種使用提供結構支撐之封膠劑來形成一具有直通矽晶穿孔和背部重分配層之互連結構以用於立體元件之方法。
118．．．半導體晶圓
120．．．作用表面
121．．．絕緣層
122．．．導電層
124．．．導電層
126．．．絕緣或保護層
128．．．導電層
130．．．絕緣或保護層
132．．．導電柱或杆
134．．．絕緣層
136．．．導電層
138．．．圓球或凸塊
140．．．半導體晶粒
142．．．接觸墊片
144．．．被動元件或構件
146．．．黏結物
150．．．封膠劑或封膠化合物
152．．．背部表面
154．．．絕緣或保護層
156．．．導電層
158．．．圓球或凸塊
160．．．半導體元件
166．．．接觸墊片
168．．．印刷電路板

Claims (15)

  1. 一種製造半導體元件之方法，包括：提供基板；在該基板的第一表面中形成複數個通孔；將導電材料沉積於該通孔中以形成複數個導電通孔；在該基板的該第一表面上形成第一互連結構，其藉由：(a)在該導電通孔上形成複數個導電柱，(b)在該導電柱上及四周形成第一絕緣層且在該第一絕緣層中具有延伸至該導電柱的開口，及(c)在該導電柱上的該開口內形成第一導電層；安裝半導體晶粒或構件，該半導體晶粒或構件包含被黏接至該第一導電層的複數個凸塊；將封膠劑沉積於該第一互連結構和半導體晶粒或構件上；移除與該基板的該第一表面相對之該基板的第二表面之部分以減少厚度並露出該導電通孔；形成第二互連結構於該基板的該第二表面上且電性連接至該導電通孔；及在形成該第二互連結構之後將該基板單粒化。
  2. 如申請專利範圍第1項之方法，其中，形成該第一互連結構進一步包含：在該導電通孔上形成第二導電層；在該第二導電層和基板上形成第二絕緣層；在該第二導電層上形成第三導電層；及 在該第三導電層和第二絕緣層上形成第三絕緣層。
  3. 如申請專利範圍第1項之方法，進一步包含透過該第二互連結構將該半導體元件安裝至印刷電路板。
  4. 如申請專利範圍第1項之方法，其中，形成該第二互連結構包含：在該基板的該第二表面上形成第二絕緣層；在該導電通孔上形成第二導電層；在該第二絕緣層和第二導電層上形成第三絕緣層；及在該第二導電層上形成第三導電層。
  5. 如申請專利範圍第1項之方法，其中，該封膠劑在移除該基板的該第二表面之該部分時提供結構支撐。
  6. 一種半導體元件之製造方法，包括：提供基板；形成貫穿該基板的第一表面之複數個導電通孔；在該基板的該第一表面上形成第一互連結構，其藉由：(a)在該導電通孔上形成複數個導電柱，及(b)在該導電柱上及四周形成第一絕緣層且在該第一絕緣層中具有延伸至該導電柱的開口；將包含複數個凸塊的半導體晶粒或構件安裝至該第一互連結構，而該凸塊被配置在該導電柱上；將封膠劑沉積於該第一互連結構和半導體晶粒或構件上；移除與該基板的該第一表面相對之該基板的該第二表面之部分以減少厚度並露出該導電通孔；及 在移除該基板的該第二表面之該部分之後將該基板單粒化。
  7. 如申請專利範圍第6項之方法，進一步包含形成第二互連結構於該基板的該第二表面上且電性連接至該導電通孔。
  8. 如申請專利範圍第7項之方法，進一步包含透過該第二互連結構將該半導體元件安裝至印刷電路板。
  9. 如申請專利範圍第7項之方法，其中，形成該第二互連結構包含：在該基板的該第二表面上形成第二絕緣層；及在該導電通孔上形成第一導電層。
  10. 如申請專利範圍第6項之方法，其中，形成該第一互連結構包含：在該導電通孔上形成第一導電層；在該第一導電層和基板上形成第二絕緣層；在該第一導電層上形成第二導電層；在該第二導電層和第二絕緣層上形成第三絕緣層；在該導電柱上形成第三導電層；及電性連接該半導體晶粒或構件至該第三導電層。
  11. 一種半導體元件，包括：基板；貫穿該基板所配置之複數個導電通孔；在該基板的第一表面上所配置之第一互連結構，其中該第一互連結構包含： (a)在該導電通孔上所形成之複數個導電柱，及(b)在該導電柱上及四周所形成之第一絕緣層，而在該第一絕緣層中具有延伸至該導電柱的開口；安裝至該第一互連結構之包含複數個凸塊的複數個半導體晶粒或構件，而該凸塊被配置在該導電柱上；及沉積於該第一互連結構和半導體晶粒或構件上之封膠劑。
  12. 如申請專利範圍第11項之半導體元件，其中，該第一互連結構包含：配置於該導電通孔上之第一導電層；配置於基板和該第一導電層上之第二絕緣層；配置於該第一導電層上之第二導電層；配置於該第二導電層和第二絕緣層上之第三絕緣層；及配置於該導電柱上之第三導電層，該第三導電層透過該凸塊電性連接至該半導體晶粒或構件。
  13. 如申請專利範圍第11項之半導體元件，進一步包含第二互連結構，其配置在與該基板的該第一表面相對之該基板的第二表面上且電性連接至該導電通孔。
  14. 如申請專利範圍第11項之半導體元件，其中，該封膠劑之表面是與該基板之側表面共平面。
  15. 如申請專利範圍第13項之半導體元件，其中，該第二互連結構包含：配置於該基板的該第二表面上之第二絕緣層； 配置於該導電通孔上之第一導電層；配置於該第二絕緣層和第一導電層上之第三絕緣層；及配置於該第一導電層上之第二導電層。
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