TWI515810B - 半導體元件以及在垂直互連結構附近形成非流動的底部填充材料的方法 - Google Patents

半導體元件以及在垂直互連結構附近形成非流動的底部填充材料的方法 Download PDF

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TWI515810B
TWI515810B TW099106849A TW99106849A TWI515810B TW I515810 B TWI515810 B TW I515810B TW 099106849 A TW099106849 A TW 099106849A TW 99106849 A TW99106849 A TW 99106849A TW I515810 B TWI515810 B TW I515810B
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interconnect structure
semiconductor
carrier
encapsulant
forming
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TW099106849A
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TW201113963A (en
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黃銳
官怡荷
林耀劍
鄒勝原
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史達晶片有限公司
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Description

半導體元件以及在垂直互連結構附近形成非流動的底部填充材料的方法
本發明概括關於半導體元件，且尤指一種半導體元件以及在垂直互連結構附近形成非流動(no-flow)的底部填充(underfill)材料的方法。
半導體元件常見於現代電子產品。半導體元件為於電氣構件的數目與密度而變化。離散的半導體元件通常含有一個型式的電氣構件，例如：發光二極體(LED，light emitting diode)、電晶體、電阻器、電容器、電感器與功率(power)金屬氧化物半導體場效電晶體(MOSFET，metal oxide semiconductor field effect transistor)。積體的半導體元件典型為含有數百個到數百萬個電氣構件。積體的半導體元件之實例包括：微控制器、微處理器、電荷耦合元件(CCD，charge-coupled device)、太陽能電池與數位微鏡元件(DMD，digital micro-mirror device)。
半導體元件實行廣泛範圍的作用，諸如：高速計算、傳送及接收電磁訊號、控制電子元件、轉變陽光為電力及產生視覺投影以供電視顯像。半導體元件可見於娛樂、通訊、發電、網路、電腦與消費產品之領域。半導體元件亦可見於包括軍事、航空、汽車、工業控制器與辦公室設備之電子產品。
半導體元件利用半導體材料的電氣性質。半導體材料的原子結構允許其導電性為藉由電場施加或透過摻雜過程而操縱。摻雜引入雜質至半導體材料以操縱及控制半導體元件的導電性。
一種半導體元件含有主動與被動的電氣結構。主動結構(包括：電晶體)控制電流之流通。藉由改變摻雜位準及電場施加，電晶體促進或限制電流之流通。被動結構(包括：電阻器、二極體與電感器)建立於電壓與電流之間的一種關係，其為必要以實行種種電氣作用。被動與主動結構電氣連接以形成電路，致使半導體元件為能夠實行高速計算與其他有用的作用。
半導體元件通常運用二個複雜的製程所製造，即：前段(front-end)製造與後段(back-end)製造，各者涉及潛在為數百個步驟。前段製造涉及於半導體晶圓表面的複數個晶粒之形成。各個晶粒典型為相同且含有其藉由電氣連接主動與被動構件所形成的電路。後段製造涉及自所完成的晶圓以單一化個別的晶粒且封裝該晶粒以提供結構支撐與環境隔離。
半導體製造之一個目標產生較小的半導體元件。較小的元件典型為消耗較少的功率，具有較高的性能，且可為較有效率製造。此外，較小的半導體元件具有較小的使用空間，其針對於較小的最終產品為合意。較小晶粒尺寸可由於前段製程之改良而達成，造成具有較小、較高密度的主動與被動構件之晶粒。後段製程可由於電氣互連與封裝材料之改良而造成其具有較小的使用空間之半導體元件封裝。
於其含有多個階層的半導體元件(3D元件整合)的扇出晶圓階層晶片尺度封裝(FO-WLCSP，fan-out wafer level chip scale package)與外部元件之間的電氣互連可藉著傳導的矽通孔(TSV，through silicon via)、通孔(THV，through hole via)或鍍銅的傳導柱而達成。通孔運用雷射鑽孔或深度反應離子蝕刻(DRIE，deep reactive ion etching)以矽或有機材料而形成於晶粒的附近。通孔填充傳導材料，例如：藉由透過一種電鍍過程之銅沉積，以形成傳導TSV與THV。在垂直互連結構為形成後，一種晶圓階層模製化合物沉積於最終的製造階段。暫時的載體/晶圓塊台之尺寸必須定製以配合晶圓階層模製系統。TSV與THV之形成以及晶圓階層模製涉及特定的設備、緩慢的處理與高成本的製造步驟。
對於形成垂直互連結構於半導體封裝的需要存在。是以，於一個實施例，本發明為一種製造半導體元件的方法，包含步驟：提供一第一犧牲性(sacrificial)載體；形成一第一傳導層在第一犧牲性載體之上；形成一第一焊塊在第一傳導層之上；沉積一非流動的底部填充材料在第一犧牲性載體、第一傳導層與第一焊塊之上；壓縮一第一半導體晶粒或構件至非流動的底部填充材料以電氣接觸第一傳導層；平面化非流動的底部填充材料與第一焊塊的一第一表面；及，形成一第一互連結構在非流動的底部填充材料的第一表面之上。第一互連結構為電氣連接至第一焊塊。該種方法更包括步驟：安裝一第二犧牲性載體在第一互連結構之上；移除第一犧牲性載體；及，形成其相對於第一互連結構之一第二互連結構在非流動的底部填充材料的一第二表面之上。第二互連結構電氣連接至第一焊塊、第一互連結構與第一半導體晶粒或構件。該種方法更包括步驟：移除第二犧牲性載體。
於另一個實施例，本發明為一種製造半導體元件的方法，包含步驟：提供一第一載體；形成一z方向的互連結構在第一載體之上；沉積一非流動的底部填充材料在第一載體與z方向的互連結構之上；壓縮一第一半導體晶粒或構件至非流動的底部填充材料；及，形成一第一互連結構在非流動的底部填充材料的一第一表面之上。第一互連結構電氣連接至z方向的互連結構。
於另一個實施例，本發明為一種製造半導體元件的方法，包含步驟：提供一第一載體；形成一z方向的互連結構在第一載體之上；沉積一囊封物在第一載體與z方向的互連結構之上；壓縮一第一半導體晶粒或構件至囊封物；及，形成一第一互連結構在囊封物的一第一表面之上。第一互連結構電氣連接至z方向的互連結構。
於另一個實施例，本發明為一種半導體元件，包含：一第一傳導層；及，形成在第一傳導層之上的z方向的互連結構。一非流動的底部填充材料沉積在第一傳導層與z方向的互連結構之上。一第一半導體晶粒或構件壓縮至非流動的底部填充材料。一第一互連結構形成在非流動的底部填充材料的一第一表面之上。第一互連結構電氣連接至z方向的互連結構。
本發明參考圖式而描述於以下說明的一或多個實施例，其中，同樣的參考符號代表相同或類似元件。儘管本發明依據用於達成本發明的目標之最佳模式而描述，將為熟悉此技術人士所理解的是：意圖以涵蓋如可為納入於由隨附的申請專利範圍與以下揭露內容與圖式所支持的其等效者所界定之本發明的精神與範疇內的替代、修改與等效者。
半導體元件通常運用二個複雜的製程所製造：前段製造與後段製造。前段製造涉及於半導體晶圓表面的複數個晶粒之形成。於晶圓上的各個晶粒含有主動與被動的電氣構件，其為電氣連接以形成作用的電路。主動電氣構件(諸如：電晶體)具有能力以控制電流之流通。被動電氣構件(諸如：電容器、電感器、電阻器與變壓器)建立於電壓與電流之間的一種關係，其為必要以實行電路作用。
被動與主動構件藉由其包括摻雜、沉積、光刻、蝕刻與平面化之一連串的處理步驟而形成於半導體晶圓的表面上。摻雜為藉由諸如離子植入或熱擴散之技術而引入雜質至半導體材料。摻雜過程修改於主動元件之半導體材料的導電性，轉變半導體材料成為一種永久的絕緣體、永久的導體，或響應於電場而改變半導體材料的導電性。電晶體含有變化型式與摻雜程度的區域，其隨著必要而配置以致使電晶體為能夠於電場施加時而促進或限制電流的流通。
主動與被動構件由具有不同的電氣性質之數層材料所形成。諸層可藉由其部分為所沉積的材料型式所決定之種種沉積技術所形成。舉例而言，薄膜沉積可能涉及化學汽相沉積(CVD，chemical vapor deposition)、物理汽相沉積(PVD，physical vapor deposition)、電解電鍍及無電電鍍過程。各層通常圖案化以形成部分的主動構件、被動構件或於構件之間的電氣連接。
諸層可運用光刻法所圖案化，光刻法涉及例如光阻的光敏材料之沉積於將作圖案化之層上。一圖案(pattern)運用光線而轉移自一光罩至光阻。受到光線之光阻圖案部分運用一種溶劑所移除，暴露將作圖案化之下面層的部分者。移除光阻的其餘部分，留下一圖案化層。或者是，一些型式的材料藉由直接沉積材料至其運用諸如無電及電解電鍍法的技術之一種先前沉積/蝕刻過程所形成的區域或空隙而圖案化。
沉積一薄膜的材料於現存的圖案上可能擴大在下面的圖案且產生一不均勻平坦表面。一均勻平坦表面需要以產生較小且較密集封裝的主動與被動構件。平面化可運用以移除自晶圓表面的材料且產生一均勻平坦表面。平面化涉及磨光晶圓表面為具有一磨光墊。一種研磨材料與腐蝕化學製品於磨光期間而添加至晶圓表面。研磨料的機械作用與化學製品的腐蝕作用之組合者為移除任何不規則的拓撲結構，造成一均勻平坦表面。
後段製造是指將所完成的晶圓切割或單一化成為個別的晶粒且接著封裝該晶粒以供結構支撐與環境隔離。欲將晶粒單一化，晶圓沿著稱為鋸道或劃線之晶圓的非作用區域而刻劃及切斷。晶圓運用一種雷射切割裝置或鋸條而單一化。在單一化之後，個別晶粒安裝至一封裝基板，其包括接腳或接觸墊以供互連於其他的系統構件。形成在半導體晶粒之上的接觸墊接著連接至於封裝內的接觸墊。電氣連接可藉著焊塊、柱塊、導電糊膏或線接合而作成。一種囊封物或其他的模製材料沉積於封裝之上以提供實際支撐與電氣隔離。完成的封裝接著插入至一種電氣系統且該半導體元件的功能性成為可用於其他的系統構件。
圖1為說明電子元件10，其具有一晶片載體基板或印刷電路板(PCB，printed circuit board) 12，印刷電路板12具有安裝於其表面之複數個半導體封裝。電子元件10可具有一個型式的半導體封裝或多個型式的半導體封裝，視應用而定。不同型式的半導體封裝為了說明而顯示於圖1。
電子元件10可為一種獨立系統，其運用該等半導體封裝以實行一種電氣作用。或者是，電子元件10可為一較大系統的一個子構件。舉例而言，電子元件10可為一圖形卡、網路介面卡或其可為插入至電腦之其他的訊號處理卡。半導體封裝可包括：微處理器、記憶體、特定應用積體電路(ASIC，application specific integrated circuit)、邏輯電路、類比電路、射頻電路、離散元件或其他的半導體晶粒或電氣構件。
於圖1，PCB 12提供一種通用的基板以供其安裝於PCB的半導體封裝之結構支撐及電氣互連。傳導訊號線跡14運用蒸鍍、電解電鍍、無電電鍍、網印、PVD或其他適合金屬沉積過程而形成在PCB 12的一表面上或於PCB 12的諸層內。訊號線跡14提供於各個半導體封裝、安裝構件與其他外部系統構件之間的電氣連通。線跡14亦提供對於各個半導體封裝之電力與接地連接。
於一些實施例，一種半導體元件具有二個封裝階層。第一階層封裝用於機械及電氣式附接半導體晶粒至一載體的一種技術。第二階層封裝涉及：機械及電氣式附接該載體至PCB。於其他實施例，一種半導體元件可僅具有第一階層封裝，其中，該晶粒為機械及電氣式直接安裝至PCB。
為了說明，數個型式的第一階層封裝顯示於PCB 12，包括：線接合封裝16與倒裝晶片18。此外，數個型式的第二階層封裝顯示為安裝於PCB 12，包括：球柵陣列(BGA，ball grid array) 20、塊形晶片載體(BCC，bump chip carrier) 22、雙列直插封裝(DIP，dual in-line package) 24、岸柵陣列(LGA，land grid array) 26、多晶片模組(MCM，multi-chip module) 28、四面扁平無引線封裝(QFN，quad flat non-leaded package) 30與四面扁平封裝32。視系統需求而定，任何組合的第一與第二階層封裝型式所構成之任何組合的半導體封裝以及其他的電子構件可連接至PCB 12。於一些實施例，電子元件10包括單一個附接的半導體封裝，而其他實施例需要多個互連的封裝。藉由組合一或多個半導體封裝在單一個基板之上，製造業者可將事先作成的構件納入至電子元件及系統。因為半導體封裝包括複雜的功能性，電子元件可運用較便宜的構件及一種有效率的製程所製造。造成的元件較不可能失效且較不昂貴以製造，造成對於消費者之較低的成本。
圖2a說明其安裝於PCB 12之DIP 24的進一步細節。DIP 24包括具有接觸墊36之半導體晶粒34。半導體晶粒34包括：一主動區域，其含有類比或數位電路而實施為主動元件、被動元件、傳導層與介電層，形成於半導體晶粒34之內且為根據晶粒的電氣設計而電氣互連。舉例而言，該電路可包括：一或多個電晶體、二極體、電感器、電容器、電阻器與其形成於晶粒34之主動區域內的其他電路元件。接觸墊36為以一種傳導材料所作成，諸如：鋁(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)或銀(Ag)，且為電氣連接至其形成於晶粒34之內的電路元件。接觸墊36藉由PVD、CVD、電解電鍍或無電電鍍過程所形成。於DIP 24之組裝期間，半導體晶粒34運用一種金-矽的共熔層或諸如熱環氧化物的黏著材料而安裝至一載體38。封裝本體包括一種絕緣封裝材料，諸如：聚合物或陶瓷。導體引線40連接至載體38且線接合42形成於引線40與晶粒34的接觸墊36之間而作為一第一階層封裝。囊封物44沉積在封裝上以供環境保護，藉由阻止濕氣與微粒而免於進入封裝及污染晶粒34、接觸墊36或線接合42。DIP 24藉由插入引線40至其形成穿過PCB 12的孔而連接至PCB 12。焊料46流通環繞引線40且進入孔以實際及電氣式連接DIP 24至PCB 12。焊料46可為任何的金屬或導電材料，例如：Sn、鉛(Pb)、Au、Ag、Cu、鋅(Zn)、鉍(Bi)與其合金，具有一種選用的助熔材料。舉例而言，焊料可為共熔Sn/Pb、高鉛或無鉛。
圖2b為說明其安裝於PCB 12之BCC 22的進一步細節。半導體晶粒47藉由線接合型式的第一階層封裝而連接至一載體。BCC 22以一種BCC型式的第二階層封裝而安裝至PCB 12。具有接觸墊48之半導體晶粒47運用一種底部填充(underfill)或環氧樹脂的黏著材料50而安裝在一載體上。半導體晶粒47包括：一主動區域，其含有類比或數位電路而實施為主動元件、被動元件、傳導層與介電層，形成於半導體晶粒47之內且為根據晶粒的電氣設計而電氣互連。舉例而言，該電路可包括：一或多個電晶體、二極體、電感器、電容器、電阻器與其形成於晶粒47之主動區域內的其他電路元件。接觸墊48為以一種傳導材料所作成，諸如：Al、Cu、Sn、Ni、Au或Ag，且為電氣連接至其形成於晶粒47之內的電路元件。接觸墊48藉由PVD、CVD、電解電鍍或無電電鍍過程所形成。線接合54及接合墊56與58電氣連接半導體晶粒47的接觸墊48至BCC 22的接觸墊52而形成第一階層封裝。模製化合物或囊封物60沉積在半導體晶粒47、線接合54、接觸墊48與接觸墊52之上，以提供針對於該元件的實際支撐及電氣隔離。接觸墊64運用蒸鍍、電解電鍍、無電電鍍、網印、PVD或其他適合金屬沉積過程而形成在PCB 12之一表面上且典型為電鍍以防止氧化。接觸墊64電氣連接至一或多個傳導訊號線跡14。焊料沉積於BCC 22的接觸墊52與PCB 12的接觸墊64之間。焊料回流以形成凸塊66，其形成於BCC 22與PCB 12之間的機械及電氣連接。
於圖2c，半導體晶粒18以一種倒裝晶片型式的第一階層封裝而安裝為面對朝下至載體76。BGA 20以一種BGA型式的第二階層封裝而附接至PCB 12。主動區域70含有類比或數位電路而實施為主動元件、被動元件、傳導層與介電層，形成於半導體晶粒18之內且為根據晶粒的電氣設計而電氣互連。舉例而言，該電路可包括：一或多個電晶體、二極體、電感器、電容器、電阻器與其形成於半導體晶粒18的主動區域70之內的其他電路元件。半導體晶粒18透過大量個別傳導焊塊或球78而電氣及機械式附接至載體76。焊塊78形成在其配置於主動區域70的凸塊墊或互連位置80之上。凸塊墊80以一種傳導材料所作成，諸如：Al、Cu、Sn、Ni、Au或Ag，且電氣連接至其形成於主動區域70的電路元件。凸塊墊80藉由PVD、CVD、電解電鍍或無電電鍍過程所形成。焊塊78藉由一種焊料回流過程而電氣及機械式連接至於載體76的接觸墊或互連位置82。
BGA 20藉由大量個別傳導焊塊或球86而電氣及機械式附接至PCB 12。焊塊形成在凸塊墊或互連位置84之上。凸塊墊84透過其路由通過載體76之導線90而電氣連接至互連位置82。接觸墊88運用蒸鍍、電解電鍍、無電電鍍、網印、PVD或其他適合金屬沉積過程而形成在PCB 12之一表面上且典型為電鍍以防止氧化。接觸墊88電氣連接至一或多個傳導訊號線跡14。焊塊86藉由一種焊料回流過程而電氣及機械式連接至於PCB 12的接觸墊或接合墊88。模製化合物或囊封物92沉積在半導體晶粒18與載體76之上，以提供針對於該元件的實際支撐及電氣隔離。倒裝晶片式半導體元件提供自於半導體晶粒18的主動元件至於PCB 12的傳導軌跡之一短的導電路徑，藉以縮小訊號傳播距離、降低電容及改良整體電路性能。於另一個實施例，半導體晶粒18可運用倒裝晶片型式的第一階層封裝且無載體76而機械及電氣式直接附接至PCB 12。
圖3a至31為說明一種形成於一扇出晶圓階層晶片尺度封裝(FO-WLCSP，fan-out wafer level chip scale package)之垂直(z方向)互連結構的過程。於圖3a，一犧牲性的晶圓形式基板或載體100含有暫置或犧牲性的底座材料，諸如：矽、聚合物、聚合複合物、金屬、陶瓷、玻璃、玻璃環氧化物、氧化鈹或用於結構支撐之其他適合的低成本、剛性的材料或塊狀半導體材料。於一個實施例，載體100直徑為20.3公分(cm)。一選用的介面層可形成在載體100之上而作為一暫時的接合膜或蝕刻阻止層。
一導電層102運用一種沉積與圖案化過程以個別的部分或片段而形成在載體100的一頂表面之上。導電層102運用PVD、CVD、濺鍍、電解電鍍、無電電鍍過程或其他適合金屬沉積過程而形成。導電層102可為一或多層的Al、Cu、Sn、Ni、Au、Ag或其他適合導電材料。視半導體晶粒的設計與作用而定，導電層102的個別部分可為電氣共同或電氣隔離。導電層102的一些部分操作為用於稍後形成的焊塊之一凸塊下的金屬化層(UBM，under bump metallization layer)或凸塊墊。UBM 102可為一種多金屬堆疊且具有黏著層、障壁層與晶種或濕潤層。黏著層形成在載體100或介面層之上且可為Ti、氮化鈦(TiN)、鈦鎢(TiW)、Al或鉻(Cr)。障壁層形成在黏著層之上且可為由Ni、鎳釩(NiV)、鉑(Pt)、鈀(Pd)、TiW或鉻銅(CrCu)所作成。障壁層禁止Cu之擴散至該晶粒的主動區域。晶種層可為Cu、Ni、NiV、Au或Al。晶種層形成在障壁層之上且作用為用於後續的焊塊或其他的互連結構之一中間導電層。於一個實施例，UBM 102含有多層之選擇性電鍍的Ni/Au、Ti/Cu、TiW/Cu、Ti/Cu/NiV/Cu或其組合。UBM 102提供一低電阻性的互連以及對於焊料擴散之障壁與針對於焊料濕潤性之晶種層。
一導電焊料運用一種蒸鍍、電解電鍍、無電電鍍、球滴或網印過程而沉積在導電層102之上。焊料可為任何的金屬或導電材料，例如：Sn、Ni、Au、Ag、Pb、Bi與其合金，具有一種選用的助熔材料。舉例而言，焊料可為共熔Sn/Pb、高鉛或無鉛。焊料為藉由將材料加熱為高於其熔點而回流以形成圓球或凸塊104。於一些應用，焊塊104回流第二次以改良對於導電層102之電氣接觸。焊塊104代表其可形成在導電層102之上的一個型式的垂直、z方向互連結構。多列的焊塊104提高z方向互連容量。互連結構亦可運用接合線、傳導柱、柱塊、微凸塊或其他的電氣互連。
圖3b顯示一種非流動的底部填充材料(NFM，no-flow underfill material) 105為運用旋轉塗覆、分配或疊合而沉積在載體100、導電層102之上且環繞焊塊104。NFM 105可為其具有高的熱膨脹係數(CTE，coefficient of thermal expansion)與高的玻璃轉變溫度之一種環氧樹脂。美國專利第6,180,696號與第6,794,761號描述其他適合的非流動的底部填充材料且為以參照方式而納入於本文。NFM 105的量沉積為控制至其覆蓋焊塊104的一主要部分且暴露焊塊的其餘部分之一厚度。
於圖3c，半導體晶粒106安裝在載體100之上且接觸墊107為運用焊料、微凸塊或其他電氣互連而電氣接觸導電層102。半導體晶粒106受到力量而壓縮至NFM 105，例如：運用熱壓縮接合或超音波接合，以形成一壓縮接合至載體100。焊料微凸塊回流以電氣連接接觸墊107至導電層102，而同時助熔及非流動的底部填充材料105之聚合化。半導體晶粒106各自包括一基板，具有一主動區域，其含有類比或數位電路而實施為主動元件、被動元件、傳導層與介電層，形成於晶粒之內且根據晶粒的電氣設計與作用而電氣互連。舉例而言，該電路可包括一或多個電晶體、二極體與形成於其主動表面內的其他電路元件，以實施類比電路或基頻數位電路，諸如：數位訊號處理器(DSP，digital signal processor)、記憶體或其他訊號處理電路。半導體晶粒106亦可含有用於射頻(RF)訊號處理之積體被動元件(IPD，integrated passive device)，諸如：電感器、電容器與電阻器。於另一個實施例，一個離散構件可安裝在載體100之上且電氣連接至導電層102。半導體晶粒106可為倒裝晶片型式的晶粒或無凸塊之其他的半導體晶粒。
於對於圖3b與3c所示的結構之一個替代實施例，半導體晶粒108安裝在載體100之上且接觸墊109為運用焊料、微凸塊或其他電氣互連而電氣接觸導電層102。半導體晶粒108各自包括一基板，具有一主動區域，其含有類比或數位電路而實施為主動元件、被動元件、傳導層與介電層，形成於晶粒之內且根據晶粒的電氣設計與作用而電氣互連。舉例而言，該電路可包括一或多個電晶體、二極體與形成於其主動表面之內的其他電路元件，以實施類比電路或基頻數位電路，諸如：DSP、記憶體或其他訊號處理電路。半導體晶粒108亦可含有用於射頻訊號處理之IPD，諸如：電感器、電容器與電阻器。
圖3e顯示一種囊封物或模製化合物110為運用一種糊膏印製、壓縮模製、轉移模製、液體囊封物模製、真空疊合或其他適合施加器而沉積在載體100、導電層102之上且環繞焊塊104。囊封物110可為其具有如同NFM 105的類似性質之聚合物複合材料，諸如：具有填料的環氧樹脂、具有填料的環氧丙烯酸酯或具有適當填料的聚合物。囊封物110的量沉積為控制至其暴露焊塊104的一頂部分之一厚度。或者是，囊封物110的一部分藉由一種蝕刻過程所移除以暴露焊塊104。囊封物110為非傳導性且環境保護半導體元件為免於外部元件與污染物的損害。
在於圖3b與3c所述的過程或於圖3d與3e所述的過程之後，NFM 105(或囊封物110)固化及硬化於圖3f。半導體晶粒106(或半導體晶粒108)與焊塊104延伸在NFM 105(或囊封物110)之上，如於圖3f所示。NFM 105(或囊封物110)免除對於先前技術所見之晶圓階層模製的需要。其餘說明相關於圖3b與3c，雖然於圖3d與3e所示的過程與結構已瞭解。
於圖3g，一種研磨機112為移除NFM 105、焊塊104、與半導體晶粒106的背表面之一部分以產生一平坦表面。或者是，NFM 105、焊塊104與半導體晶粒106的背表面之部分者可藉由化學蝕刻、機械脫落或CMP所移除。
於圖3h，一頂側建立的互連結構114形成在NFM 105、焊塊104與半導體晶粒106之上。建立的互連結構114包括一絕緣或鈍化層116，其含有一或多層的二氧化矽(SiO2)、氮化矽(Si3N4)、氮氧化矽(SiON)、五氧化二鉭(Ta2O5)、氧化鋁(Al2O3)或具有類似絕緣與結構性質的其他材料。絕緣層116運用PVD、CVD、印製、旋轉塗覆、噴灑塗覆、燒結或熱氧化而形成。
頂側建立的互連結構114更包括一導電層118，其運用一種圖案化與沉積過程而形成於絕緣層116。導電層118運用PVD、CVD、濺鍍、電解電鍍、無電電鍍過程或其他適合金屬沉積過程而形成。導電層118可為一或多層的Al、Cu、Sn、Ni、Au、Ag或其他適合導電材料。絕緣層116的一部分藉由一種蝕刻過程而移除以暴露導電層118。導電層118的一個部分電氣連接至焊塊104。視半導體元件的設計與作用而定，導電層118的其他部分可為電氣共同或電氣隔離。
於圖3i，一犧牲性的晶圓形式基板或載體120形成在建立的互連結構114之上。載體120含有暫置或犧牲性的底座材料，諸如：矽、聚合物、聚合複合物、金屬、陶瓷、玻璃、玻璃環氧化物、氧化鈹或用於結構支撐之其他適合的低成本、剛性材料或塊狀半導體材料。一選用的介面層可形成於載體120與建立的互連結構114之間而作為一暫時的接合膜或蝕刻阻止層。
於圖3j，載體100與選用的介面層藉由化學蝕刻、機械脫落、CMP、機械研磨、熱烘烤、雷射掃描或濕式剝除而移除。該組件倒轉且一底側建立的互連結構124形成在NFM 105與導電層102之上，如於圖3k所示。建立的互連結構124包括一絕緣或鈍化層126，其含有一或多層的SiO2、Si3N4、SiON、Ta2O5、Al2O3或具有類似絕緣與結構性質的其他材料。絕緣層126運用PVD、CVD、印製、旋轉塗覆、噴灑塗覆、燒結或熱氧化而形成。
底側建立的互連結構124更包括一導電層128，其運用一種圖案化與沉積過程而形成於絕緣層126。導電層128運用PVD、CVD、濺鍍、電解電鍍、無電電鍍過程或其他適合金屬沉積過程而形成。導電層128可為一或多層的Al、Cu、Sn、Ni、Au、Ag或其他適合導電材料。絕緣層126的一部分藉由一種蝕刻過程而移除以暴露導電層128。導電層128的一個部分電氣連接至焊塊104、導電層102與半導體晶粒106的接觸墊107。視半導體元件的設計與作用而定，導電層128的其他部分可為電氣共同或電氣隔離。
於建立的互連結構114與124之導電層與絕緣層可形成一或多個IPD。舉例而言，於二個導電層之間的一絕緣層可為一金屬-絕緣體-金屬(MIM，metal-insulator-metal)電容器。其他的導電層可於平視為繞製或盤捲以產生或呈現一電感器的性質。一電阻層亦可由TaxSiy或其他金屬矽化物、TaN、NiCr、TiN或摻雜聚矽而形成於建立的互連結構114與124之內。
IPD提供針對於高頻應用所需的電氣特性，諸如：共振器、高通濾波器、低通濾波器、帶通濾波器、對稱高品質(Hi-Q)共振變壓器、匹配網路與調諧電容器。IPD為可運用作為前端的無線射頻構件，其可定位於天線與收發器之間。IPD電感器可為其操作於高達100千兆赫茲(GHz)之一種高品質的平衡-不平衡轉換器(balun)、變壓器或線圈。於一些應用，多個平衡-不平衡轉換器形成於同一個基板，允許多頻帶的操作。舉例而言，二或多個平衡-不平衡轉換器運用於針對於行動電話或其他的全球行動通訊系統(GSM，global system for mobile communication)之一四頻帶(quad-band)，各個平衡-不平衡轉換器專用於四頻帶元件之一個頻帶的操作。一種典型射頻(RF)系統需要於一或多個半導體封裝之多個IPD與其他高頻電路以實行必要的電氣作用。
一導電焊料運用一種蒸鍍、電解電鍍、無電電鍍、球滴或網印過程而沉積在導電層128之上。焊料可為任何的金屬或導電材料，例如：Sn、Ni、Au、Ag、Pb、Bi與其合金，具有一種選用的助熔材料。舉例而言，焊料可為共熔Sn/Pb、高鉛或無鉛。焊料藉由將材料加熱為高於其熔點而回流以形成圓球或凸塊130。於一些應用，焊塊130回流第二次以改良對於導電層128之電氣接觸。焊塊130代表其可形成在導電層128之上的一個型式的互連結構。互連結構亦可運用接合線、3-D互連、導電糊膏、柱塊、微凸塊或其他的電氣互連。
半導體晶粒106以鋸條或雷射切割裝置132而單一化為個別的半導體元件134，如於圖31所示。
圖4顯示在單一化之後的半導體封裝134。焊塊104提供於頂側互連建立層114與底側互連建立層124之間的z方向互連。z方向互連形成於非流動的底部填充材料以簡化製程且降低成本。導電層118透過焊塊104而電氣連接至導電層102與128及半導體晶粒106的接觸墊107。
圖5顯示堆疊的半導體封裝134。焊塊104提供於頂側互連建立層114與底側互連建立層124之間的z方向互連。導電層118透過焊塊104而電氣連接至導電層102與128及各個半導體封裝134的半導體晶粒106的接觸墊107。
於圖6，一半導體晶粒140安裝至建立的互連結構114。焊塊142電氣連接半導體晶粒140的接觸墊144至導電層118。諸如具有適當的流變與絕緣性質的環氧樹脂之一底部填充材料146沉積在半導體晶粒140之下以供消除應力及防止污染。焊塊104及建立的互連結構114與124提供於半導體晶粒140與半導體晶粒106之間的z方向互連。於半導體晶粒140之內的電氣構件透過接觸墊144、焊塊142與104、建立的互連結構114與124及接觸墊107而路由至半導體晶粒106的電氣構件。
儘管本發明之一或多個實施例為已經詳細說明，熟悉此技術人士將理解的是：對於彼等實施例的修改與調適可作成而未脫離如以下申請專利範圍所陳述之本發明的範疇。
10．．．電子元件
12．．．印刷電路板
14．．．訊號線跡
16．．．線接合封裝
18．．．倒裝晶片
20．．．球柵陣列
22．．．塊形晶片載體
24．．．雙列直插封裝
26．．．岸柵陣列
28．．．多晶片模組
30．．．四面扁平無引線封裝
32．．．四面扁平封裝
34、47．．．半導體晶粒
36、48、52、64、88．．．接觸墊
38、76．．．載體
40．．．導體引線
42、54．．．線接合
44．．．囊封物
46．．．焊料
50．．．底部填充或環氧樹脂黏著材料
56、58‧‧‧接合墊
60、92‧‧‧模製化合物或囊封物
66‧‧‧凸塊
70‧‧‧主動區域
78、86‧‧‧焊塊或球
80‧‧‧凸塊墊
82‧‧‧接觸墊或互連位置
84‧‧‧凸塊墊或互連位置
90‧‧‧導線
100‧‧‧載體
102、118、128‧‧‧導電層
104、130、142‧‧‧焊塊
105‧‧‧非流動的底部填充材料(NFM)
106、108、140‧‧‧半導體晶粒
107、109、144‧‧‧接觸墊
110‧‧‧囊封物或模製化合物
112‧‧‧研磨機
114、124‧‧‧互連結構
116、126‧‧‧絕緣或鈍化層
120‧‧‧基板或載體
132‧‧‧鋸條或雷射切割裝置
134‧‧‧半導體元件(半導體封裝)
146‧‧‧底部填充材料
圖1為說明一種具有安裝於其表面的不同型式的封裝之印刷電路板(PCB)；
圖2a至2c為說明其安裝於PCB的代表的半導體封裝之進一步細節；
圖3a至31為說明一種形成環繞垂直互連結構之非流動的底部填充材料之方法；
圖4為說明其具有環繞垂直互連結構之非流動的底部填充材料之FO-WLCSP；
圖5為說明其透過垂直互連結構而電氣連接之堆疊FO-WLCSP；及
圖6為說明其安裝至FO-WLCSP且透過垂直互連結構而電氣連接之一種半導體晶粒。
102．．．導電層
104．．．焊塊
105．．．非流動的底部填充材料(NFM)
106．．．半導體晶粒
107．．．接觸墊
114．．．互連結構
116．．．絕緣或鈍化層
118．．．導電層

Claims (14)

  1. 一種製造半導體元件的方法，包含：提供一第一載體；形成一z方向的互連結構在第一載體之上，其中該z方向的互連結構包括一焊塊；沉積一囊封物在第一載體、與z方向的互連結構之上；壓縮一第一半導體晶粒或構件至該囊封物；及形成一第一互連結構在該囊封物的一第一表面之上，第一互連結構電氣連接至該z方向的互連結構。
  2. 如申請專利範圍第1項之方法，其中，該囊封物包括一非流動的底部填充材料。
  3. 如申請專利範圍第1項之方法，更包括：平面化該囊封物與z方向的互連結構之一表面。
  4. 如申請專利範圍第1項之方法，更包括：安裝一第二載體在第一互連結構之上；移除第一載體；形成相對於第一互連結構之一第二互連結構在該囊封物的一第二表面之上，第二互連結構電氣連接至該z方向的互連結構；及移除第二載體。
  5. 如申請專利範圍第1項之方法，其中，第一互連結構包括一積體被動元件。
  6. 如申請專利範圍第1項之方法，更包括：堆疊複數個半導體元件；及 透過該z方向的互連結構而電氣連接該等半導體元件。
  7. 一種製造半導體元件的方法，包含：提供一第一載體；形成一z方向的互連結構在該第一載體之上；沉積一囊封物在該第一載體和該z方向的互連結構之上；壓縮一第一半導體晶粒或構件至在該囊封物中；平面化該囊封物的一第一表面以及該z方向的互連結構；及形成一第一互連結構在該囊封物的該第一表面之上，該第一互連結構電氣連接至該z方向的互連結構。
  8. 如申請專利範圍第7項之方法，更包括：一第二互連結構，其相對於該第一互連結構而形成在該囊封物的一第二表面之上，該第二互連結構電氣連接至該z方向的互連結構。
  9. 如申請專利範圍第7項之方法，其中，該囊封物包括一非流動的底部填充材料。
  10. 如申請專利範圍第7項之方法，其中，第一互連結構包括一積體被動元件。
  11. 一種製造半導體元件的方法，包含：提供一第一載體；形成一z方向的互連結構在該第一載體之上；沉積一囊封物在該第一載體之上且在該z方向的互連結構周圍，使得該z方向的互連結構的一上表面被暴露； 將一第一半導體晶粒或構件嵌在該囊封物中，使得該半導體晶粒的一上表面沉積在該囊封物之上；及形成一第一互連結構在該囊封物的一第一表面之上，該第一互連結構電氣連接至該z方向的互連結構。
  12. 如申請專利範圍第11項之方法，其中，該囊封物包括一非流動的底部填充材料。
  13. 如申請專利範圍第11項之方法，更包括：一第二互連結構，其相對於該第一互連結構而形成在該囊封物的一第二側之上，該第二互連結構電氣連接至該z方向的互連結構。
  14. 如申請專利範圍第11項之方法，更包括：平面化該囊封物的一表面以及該z方向的互連結構。
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