TWI488261B - 半導體元件和形成三維垂直指向之整合電容器的方法 - Google Patents

半導體元件和形成三維垂直指向之整合電容器的方法 Download PDF

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Publication number
TWI488261B
TWI488261B TW099106255A TW99106255A TWI488261B TW I488261 B TWI488261 B TW I488261B TW 099106255 A TW099106255 A TW 099106255A TW 99106255 A TW99106255 A TW 99106255A TW I488261 B TWI488261 B TW I488261B
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Taiwan
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layer
conductor
encapsulant
semiconductor
interconnect structure
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TW099106255A
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TW201041084A (en
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Rui Huang
Heap Hoe Kuan
Yaojian Lin
Seng Guan Chow
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Stats Chippac Ltd
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    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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Description

半導體元件和形成三維垂直指向之整合電容器的方法
本發明大體上關於半導體元件，且更明確地說，本發明關於半導體元件和形成三維(3-D)垂直指向之整合電容器的方法。
在現代電子產品中常會發現半導體元件。半導體元件會有不同數量及密度的電氣組件。離散式半導體元件通常含有一種類型的電氣組件，舉例來說，發光二極體(Light Emitting Diode，LED)、電晶體、電阻器、電容器、電感器以及功率金屬氧化物半導體場效電晶體(Metal Oxide Semiconductor Field Effect Transistor，MOSFET)。積體式半導體元件通常含有數百個至數百萬個電氣組件。積體式半導體元件的範例包含：微控制器、微處理器、電荷耦合元件(Charged-Coupled Device，CCD)、太陽能電池以及數位式微鏡元件(Digital Micro-mirror Device，DMD)。
半導體元件會實施各式各樣的功能，例如，高速計算、傳送和接收電磁訊號、控制電子元件、將太陽光轉換成電力以及創造電視顯示器的視覺投射。在娛樂產品、通訊產品、發電產品、網路產品、電腦產品以及消費性產品等領域中都會發現半導體元件。在包含下面的電子產品中同樣會發現半導體元件：軍事設備、航空設備、自動車設備、工業控制器設備以及辦公室設備。
半導體元件會利用半導體材料的電氣特性。半導體材料的原子結構使得可藉由施加電場或是經由摻雜處理來操縱其導電性。摻雜會將雜質引入該半導體材料之中，以便操縱及控制該半導體元件的傳導性。
一半導體元件會含有主動式電氣結構與被動式電氣結構。主動式結構(其包含電晶體)會控制電流的流動。藉由改變摻雜程度以及電場的施加，該電晶體會提高或限制電流的流動。被動式結構(其包含電阻器、二極體以及電感器)會創造用以實施各式各樣電氣功能所需要的電壓和電流之間的關係。該等被動式結構與主動式結構會被電氣連接而形成讓該半導體元件實施高速計算及其它實用功能的電路。
半導體元件通常會使用兩種複雜的製程來製造，也就是，前端製造和後端製造，每一者皆可能涉及數百道步驟。前端製造涉及在一半導體晶圓的表面上形成複數個晶粒。每一個晶粒通常相同並且含有藉由電氣連接主動式組件和被動式組件而形成的電路。後端製造涉及從已完成的晶圓中單體化裁切個別的晶粒並且封裝該晶粒，用以提供結構性支撐及環境隔離。
半導體製造的其中一個目標便為製造較小的半導體元件。較小的元件通常會消耗較少電力，具有較高效能，並且能夠更有效地生產。此外，較小的半導體元件還具有較小的覆蓋面積，這為較小的末端產品所需要的。藉由改善前端製程可以達成較小的晶粒尺寸，從而導致具有較小、較高密度之主動式組件和被動式組件的晶粒。後端製程可以藉由改善電氣互連及封裝材料而導致具有較小覆蓋面積的半導體元件封裝。
半導體製造的另一個目標為生產更高效能的半導體元件。藉由形成能夠運作在更高速度處之主動式器件便能夠達成提高元件效能的目的。在高頻應用中，射頻(Radio Frequency，RF)元件、無線通訊元件、整合被動式元件(Integrated Passive Device，IPD)通常都會被含在該半導體元件裡面。IPD的範例包含：電阻器、電容器以及電感器。一種典型的RF系統需要在一或多個半導體封裝中用到多個IPD，用以實施所需要的電氣功能。
整合電容器通常為藉由下面的方式製成，也就是，平面式金屬-絕緣體-金屬(Metal-Insulator-Metal，MIM)電容器：形成一第一金屬層；在該第一金屬層的上方形成一絕緣層；以及在該絕緣層的上方形成一第二金屬層。該平面式MIM電容器會佔用大量的矽面積，特別是大數值元件(large value device)，例如去耦合電容器(decoupling capacitor)。離散式電容器會被使用在大數值應用中，但是需要利用表面黏著技術(Surface Mount Technology，SMT)整合在系統級封裝(System-in-Package，SiP)之中，這非常昂貴並且可能會降低製造良率。
本技術領域需要不會消耗大量矽面積的大數值整合被動式元件。據此，於其中一實施例中，本發明為一種製造半導體元件的方法，其包括下面步驟：提供一暫時性載板；在該暫時性載板的上方沉積一晶種層；在該晶種層的上方垂直地形成複數個導體柱；在該等導體柱的上方形成一保形絕緣層；以及在該保形絕緣層的上方形成一保形導體層。一第一導體柱、保形絕緣層以及保形導體層會構成一垂直指向之整合電容器。該方法進一步包含下面步驟：將一半導體晶粒或組件黏著在該晶種層的上方；將一囊封劑沉積在該半導體晶粒或組件的上方以及該保形導體層附近；以及在該囊封劑的第一側上方形成一第一互連結構。該第一互連結構會被電氣連接至一第二導體柱。該方法進一步包含下面步驟：移除該暫時性載板，以及在該囊封劑中和該囊封劑的第一側反向的第二側上方形成一第二互連結構。
於另一實施例中，本發明為一種製造半導體元件的方法，其包括下面步驟：提供一載板；在該載板的上方垂直地形成複數個導體柱；在該等導體柱的上方形成一保形絕緣層；以及在該保形絕緣層的上方形成一保形導體層。一第一導體柱、保形絕緣層以及保形導體層會構成一垂直指向之整合電容器。該方法進一步包含下面步驟：將一半導體晶粒或組件黏著在該載板的上方；將一囊封劑沉積在該半導體晶粒或組件的上方以及該保形導體層附近；以及在該囊封劑的第一側上方形成一第一互連結構。該第一互連結構被電氣連接至該半導體晶粒或組件以及垂直指向之整合電容器。
於另一實施例中，本發明為一種製造半導體元件的方法，其包括下面步驟：提供一載板；在該載板的上方沉積一垂直指向之整合電容器；將一半導體晶粒或組件黏著在該載板的上方；以及將一囊封劑沉積在該半導體晶粒或組件的上方以及該垂直指向之整合電容器附近。
於另一實施例中，本發明為一種半導體元件，其包括一半導體晶粒或組件以及垂直指向之整合電容器。一囊封劑會被沉積在該半導體晶粒或組件的上方以及該垂直指向之整合電容器附近。一第一互連結構被形成在該囊封劑的第一側上方。該第一互連結構被電氣連接至該半導體晶粒或組件以及垂直指向之整合電容器。一第二互連結構被形成在該囊封劑中和該囊封劑的第一側反向的第二側上方。
本文會參考圖式，在下面說明中的一或多個實施例之中說明本發明，在圖式中，相同的元件符號代表面相同或雷同的元件。雖然本發明針對用於達成本發明之目的的最佳模式來說明本發明；不過，熟習本技術的人士便會明白，本發明希望涵蓋受到下面揭示內容和圖式支持的隨附申請專利範圍及它們的等效範圍所定義之本發明的精神與範疇內所包含的替代例、修正例以及等效例。
半導體元件通常會使用兩種複雜的製程來製造：前端製造和後端製造。前端製造涉及在一半導體晶圓的表面上形成複數個晶粒。該晶圓上的每一個晶粒皆含有主動式電氣組件和被動式電氣組件，它們被電氣連接而形成功能性電路。主動式電氣組件(例如電晶體)能夠控制電流的流動。被動式電氣組件(例如電容器、電感器、電阻器以及變壓器)會創造用以實施各式各樣電氣功能所需要的電壓和電流之間的關係。
被動式組件和主動式組件會藉由一連串的製程步驟被形成在該半導體晶圓的表面上方，該等製程步驟包含：摻雜、沉積、光微影術、蝕刻以及平坦化。摻雜會藉由下面的技術將雜質引入半導體材料之中，例如：離子植入或是熱擴散。摻雜製程會改變主動式元件中半導體材料的導電性，將該半導體材料轉換成永久性絕緣體、永久性導體，或是響應於電場來改變半導體材料傳導性。電晶體含有不同類型和摻雜程度的多個區域，它們會在必要時被排列成用以在施加一電場時讓該電晶體會提高或限制電流的流動。
主動式組件和被動式組件為由具有不同電氣特性的多層材料構成。該等層能夠藉由各式各樣的沉積技術來形成，其部分取決於要被沉積的材料的類型。舉例來說，薄膜沉積可能包含：化學氣相沉積(Chemical Vapor Deposition，CVD)製程、物理氣相沉積(Physical Vapor Deposition，PVD)製程、電解質電鍍製程以及無電極電鍍製程。每一層通常都會被圖樣化，以便形成主動式組件、被動式組件或是組件之間的電氣連接線的一部分。
該等層能夠利用光微影術來圖樣化，其涉及在要被圖樣化的層的上方沉積光敏材料，舉例來說，光阻。圖樣會利用光從一光罩處被轉印至該光阻。該光阻圖樣中受到光作用的部分會利用溶劑移除，從而露出下方層之中要被圖樣化的部分。該光阻中的剩餘部分會被移除，從而留下一已圖樣化層。或者，某些類型的材料會利用無電極電鍍以及電解質電鍍之類的技術，藉由將材料直接沉積至先前沉積及/或蝕刻製程所形成的區域或空隙之中而被圖樣化。
在一既有圖樣的上方沉積一薄膜材料可能會擴大下方圖樣並且產生一不均勻平坦的表面。生產較小且更密集封裝的主動式組件和被動式組件需要用到均勻平坦的表面。平坦化作用可用來從晶圓的表面處移除材料，並且產生均勻平坦的表面。平坦化作用涉及利用一研磨墊來研磨晶圓的表面。有研磨作用的材料以及腐蝕性的化學藥劑會在研磨期間被加到晶圓的表面。化學藥劑的研磨性作用及腐蝕性作用所組成的組合式機械作用會移除任何不規律的拓樸形狀，從而產生均勻平坦的表面。
後端製造指將已完成的晶圓切割或單體化裁切成個別晶粒，並且接著封裝該晶粒，以達結構性支撐及環境隔離的效果。為單體化裁切晶粒，晶圓會沿著該晶圓中被稱為切割道(saw street)或切割線(scribe)的非功能性區域被刻痕並且折斷。該晶圓會利用雷射切割元件或鋸片來進行單體化裁切。經過單體化裁切之後，個別晶粒便會被黏著至包含接針或接觸觸墊的封裝基板，以便和其它系統組件互連。被形成在該半導體晶粒上方的接觸觸墊接著便會被連接至該封裝裡面的接觸觸墊。該等電氣連接線可利用焊料凸塊、短柱凸塊、導電膏或是焊線來製成。一囊封劑或是其它鑄模材料會被沉積在該封裝的上方，用以提供物理性支撐和電氣隔離。接著，已完成的封裝便會被插入一電氣系統之中並且讓其它系統組件可取用該半導體元件的功能。
圖1圖解一電子元件10，其具有一晶片載體基板或是印刷電路板(Printed Circuit Board，PCB)12，在其表面上黏著複數個半導體封裝。電子元件10可能為某一類型的半導體封裝或是多種類型的半導體封裝，端視應用而定。為達解釋目的，圖1中顯示不同類型的半導體封裝。
電子元件10可能為一單機型系統，其會使用該等半導體封裝來實施一電氣功能。或者，電子元件10亦可能為一較大型系統中的一子組件。舉例來說，電子元件10可能為一圖形卡、一網路介面卡或是能夠被插入在一電腦之中的其它訊號處理卡。該半導體封裝可能包含：微處理器、記憶體、特定應用積體電路(Application Specific Integrated Circuits，ASIC)、邏輯電路、類比電路、RF電路、離散式元件或是其它半導體晶粒或電氣組件。
在圖1中，PCB 12提供一通用基板，用以結構性支撐及電氣互連被黏著在該PCB之上的半導體封裝。多條導體訊號線路14會利用下面製程被形成在PCB 12的一表面上方或是多層裡面：蒸發製程、電解質電鍍製程、無電極電鍍製程、網印製程、PVD製程或是其它合宜的金屬沉積製程。訊號線路14會在該等半導體封裝、被黏著的組件以及其它外部系統組件中的每一者之間提供電氣通訊。線路14還會電力連接及接地連接至每一個該等半導體封裝。
於某些實施例中，一半導體元件會有兩個封裝層。第一層封裝為一種用於將該半導體晶粒機械性且電氣性附接至一載板的技術。第二層封裝則涉及將該載板機械性且電氣性附接至該PCB。於其它實施例中，一半導體元件可能僅有該第一層封裝，其中，該晶粒會直接被機械性及電氣性黏著至該PCB。
為達解釋目的，圖中在PCB 12之上顯示數種類型的第一層封裝，其包含焊線封裝16以及覆晶18。除此之外，圖中還顯示被黏著在PCB 12之上的數種類型第二層封裝，其包含：球柵陣列(Ball Grid Array，BGA)20；凸塊晶片載板(Bump Chip Carrier，BCC)22；雙直列封裝(Dual In-line Package)24；平台格柵陣列(Land Grid Array，LGA)26；多晶片模組(Multi-Chip Module，MCM)28；方形扁平無導線封裝(Quad Flat Non-leaded package，QFN) 30；以及方形扁平封裝32。端視系統需求而定，被配置成具有第一層封裝樣式和第二層封裝樣式之任何組合以及其它電子組件的半導體封裝任何組合皆能夠被連接至PCB 12。於某些實施例中，電子元件10包含單一附接半導體封裝；而其它實施例則要求多個互連封裝。藉由在單一基板上方組合一或多個半導體封裝，製造商便能夠將事先製造的組件併入電子元件和系統之中。因為該等半導體封裝包含精密的功能，所以，電子元件能夠使用較便宜的組件及有效率的製程來製造。所產生的元件比較不可能失效而且製造價格較低廉，從而讓消費者的成本會較低。
圖2a所示的為被黏著在PCB 12之上的DIP 24的進一步細節。DIP 24包含半導體晶粒34，其具有多個接觸觸墊36。半導體晶粒34包含一含有類比電路或數位電路的主動區，該等類比電路或數位電路會被施行為被形成在半導體晶粒34裡面的主動式元件、被動式元件、導體層以及介電層，並且會根據該晶粒的電氣設計進行電氣互連。舉例來說，該電路可能包含被形成在晶粒34之主動區裡面的一或多個電晶體、二極體、電感器、電容器、電阻器以及其它電路器件。接觸觸墊36為由導體材料(例如鋁(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)或是銀(Ag))製成，並且會被電氣連接至被形成在晶粒34裡面的電路器件。接觸觸墊36為藉由PVD製程、CVD製程、電解質電鍍製程或是無電極電鍍製程所構成。在DIP 24的組裝期間，半導體晶粒34會利用一金-矽共熔合金層或是膠黏材料(例如熱環氧樹脂)被黏著至一載板38。封裝主體包含一絕緣封裝材料，例如聚合物或是陶瓷。導體導線40會被連接至載板38而焊線42則會被形成在導線40及晶粒34的接觸觸墊36之間作為第一層封裝。囊封劑44會被沉積在該封裝的上方，防止濕氣和粒子進入該封裝及污染晶粒34、接觸觸墊36或焊線42，以達環境保護的目的。DIP 24會藉由將導線40插入被形成貫穿PCB 12的孔洞之中而被連接至PCB 12。焊料材料46會在導線40周遭流動並且流入該等孔洞之中，以便將DIP 24物理性及電氣性連接至PCB 12。焊料材料46可以是任何金屬或導電材料，舉例來說，Sn、鉛(Pb)、Au、Ag、Cu、鋅(Zn)、鉍(Bi)以及它們的合金，其會有一非必要的助熔材料。舉例來說，該焊料材料可以是Sn/Pb共熔合金、高鉛共熔合金或是無鉛共熔合金。
圖2b所示的為被黏著在PCB 12之上的BCC 22的進一步細節。半導體晶粒47會藉由焊線樣式的第一層封裝被連接至一載板。BCC 22會利用BCC樣式的第二層封裝被黏著至PCB 12。具有多個接觸觸墊48的半導體晶粒47會利用底層填充或環氧樹脂膠黏材料50被黏著在一載板的上方。半導體晶粒47包含一含有類比電路或數位電路的主動區，該等類比電路或數位電路會被施行為被形成在半導體晶粒47裡面的主動式元件、被動式元件、導體層以及介電層，並且會根據該晶粒的電氣設計進行電氣互連。舉例來說，該電路可能包含被形成在晶粒47之主動區裡面的一或多個電晶體、二極體、電感器、電容器、電阻器以及其它電路器件。接觸觸墊48為由導體材料(例如Al、Cu、Sn、Ni、Au或是Ag)製成，並且會被電氣連接至被形成在晶粒47裡面的電路器件。接觸觸墊48為藉由PVD製程、CVD製程、電解質電鍍製程或是無電極電鍍製程所構成。焊線54以及焊接觸墊56和58會將半導體晶粒47的接觸觸墊48電氣連接至BCC 22的接觸觸墊52而形成第一層封裝。鑄模化合物或囊封劑60會被沉積在半導體晶粒47、焊線54、接觸觸墊48以及接觸觸墊52的上方，用以為該元件提供物理性支撐以及電氣隔離。多個接觸觸墊64會利用下面製程被形成在PCB 12的一表面上方並且通常會被電鍍以防止氧化：蒸發製程、電解質電鍍製程、無電極電鍍製程、網印製程、PVD製程或是其它合宜的金屬沉積製程。接觸觸墊64會電氣連接至一或多條導體訊號線路14。焊料材料會被沉積在BCC 22的接觸觸墊52和PCB 12的接觸觸墊64之間。該焊料材料會回焊而形成多個凸塊66，該等凸塊66會在BCC 22和PCB 12之間形成機械性和電氣性連接。
在圖2c中，半導體晶粒18會利用覆晶樣式的第一層封裝以面朝下的方式被黏著至載板76。BGA 20會利用BGA樣式的第二層封裝被附接至PCB 12。含有類比電路或數位電路的主動區70會根據該晶粒的電氣設計進行電氣互連，該等類比電路或數位電路會被施行為被形成在半導體晶粒18裡面的主動式元件、被動式元件、導體層以及介電層。舉例來說，該電路可能包含被形成在半導體晶粒18之主動區70裡面的一或多個電晶體、二極體、電感器、電容器、電阻器以及其它電路器件。半導體晶粒18會經由大量的個別導體焊料凸塊或焊球78被電氣性及機械性附接至載板76。焊料凸塊78會被形成在設置於主動區70之上的凸塊觸墊或互連部位80的上方。凸塊觸墊80為由導體材料(例如Al、Cu、Sn、Ni、Au或是Ag)製成，並且會被電氣連接至被形成在主動區70之中的電路器件。凸塊觸墊80為藉由PVD製程、CVD製程、電解質電鍍製程或是無電極電鍍製程所構成。焊料凸塊78會藉由回焊製程被電氣性及機械性連接至載板76之上的接觸觸墊或互連部位82。
BGA 20會藉由大量的個別導體焊料凸塊或焊球86被電氣性及機械性附接至PCB 12。該等焊料凸塊會被形成在凸塊觸墊或互連部位84的上方。該等凸塊觸墊84會經由繞送經過載板76的導體線路90被電氣連接至互連部位82。接觸觸墊88會利用下面製程被形成在PCB 12的一表面上方並且通常會被電鍍以防止氧化：蒸發製程、電解質電鍍製程、無電極電鍍製程、網印製程、PVD製程或是其它合宜的金屬沉積製程。接觸觸墊88會電氣連接至一或多條導體訊號線路14。焊料凸塊86會藉由回焊製程被電氣性及機械性連接至PCB 12之上的接觸觸墊或焊接觸墊88。鑄模化合物或囊封劑92會被沉積在半導體晶粒18和載板76的上方，用以為該元件提供物理性支撐以及電氣隔離。該覆晶半導體元件會從半導體晶粒18上的主動式元件至PCB 12上的傳導軌提供一條短的電氣傳導路徑，以便縮短訊號傳播距離，降低電容，並且改善整體電路效能。於另一實施例中，該半導體晶粒18會利用覆晶樣式的第一層封裝直接被機械性及電氣性附接至PCB 12，而沒有載板76。
圖3a至3g所示的為在一半導體封裝中形成一三維(3-D)垂直指向之整合電容器的製程。在圖3a中，一暫時性基板或載板100含有仿真或犧牲基材，例如，矽、聚合物、聚合複合物、金屬、陶瓷、玻璃、玻璃環氧樹脂、氧化鈹或是其它合宜的低成本、剛性材料或半導體材料塊，以達結構性支撐的目的。
一晶種層102會利用可熱脫模或可光脫模的暫時性黏合膜被塗敷至載板100。晶種層102可能為Cu或是具有濕式蝕刻選擇性的其它金屬薄膜。晶種層102為利用層疊、PVD、CVD、電化學沉積來沉積。晶種層102可能為一暫時性黏合膜或蝕刻阻止層。
複數個導體柱或立柱104a至104e會被形成在晶種層102的上方。為形成導體柱104，一光阻層會被沉積在晶種層102的上方。該光阻層的一部分會藉由蝕刻顯影製程來曝光並移除。導體柱104a至104e會利用電解質電鍍製程、無電極電鍍製程、或是選擇性電鍍製程被形成在已被移除的光阻部分之中。導體柱104可能為Cu、Al、鎢(W)、Au、焊料或是其它合宜的導電材料。導體柱104的高度範圍從20至200微米(μm)。於其中一實施例中，導體柱104的高度為50至100μm。該光阻會被剝除，從而留下個別的導體柱104a至104e。視情況，另一屏障薄膜層可能會被沉積在柱體104之上。
在圖3b中，一部分導體柱104a至104c會藉由下面製程被移除：蝕刻製程、研磨製程或是片切或研磨製程。經過蝕刻製程或研磨製程之後，導體柱104a至104c的垂直輪廓通常會降低20至50μm。導體柱104d至104e的垂直輪廓則會保持不變。或者，104a至104c以及104d至104e之間的不同高度能夠藉由步進微影術和電鍍製程來實現。
在圖3c中，一介電層106會被保形塗敷在導體柱104a至104e以及晶種層102的上方。該保形介電層106可能為SiO2 、Si3 N4 、SiON、五氧化二鉭(Ta2 O5 )、三氧化二鋁(Al2 O3 )、聚亞醯胺、環苯丁烯(BCB)、聚苯并噁唑纖維(polybenzoxazole，PBO)或是具有電氣絕緣特性的其它材料。該介電層106會利用下面方法被圖樣化或毯覆沈積：PVD、CVD、印刷、噴塗、旋塗、燒結、熱氧化或是層疊。該介電層106可能為單層或是多層。
一導電層108會被圖樣化並保形沉積在介電層106的上方。導體層108會利用PVD製程、CVD製程、電解質電鍍製程、無電極電鍍製程或是其它合宜的金屬沉積製程來構成。導體層108可由下面所製成的一或多層：Al、Cu、Sn、Ni、Au、Ag或是其它合宜的導電材料。應該注意的係，具有保形介電層106和導體層108的導體柱104a至104c的垂直輪廓仍然小於具有保形介電層106和導體層108的導體柱104d至104e的垂直輪廓。
在圖3d中，半導體晶粒110會被黏著至導體柱104d和104e之間的導體層108。半導體晶粒110包含類比電路或數位電路，該等類比電路或數位電路會被施行為被形成在其主動表面上方的主動式元件和被動式元件、導體層以及介電層，並且會根據該晶粒的電氣設計進行電氣互連。舉例來說，該電路可能包含被形成在該主動表面裡面的一或多個電晶體、二極體以及其它電路器件，用以施行基頻數位電路，例如，數位訊號處理器(Digital Signal Processor，DSP)、記憶體或是其它訊號處理電路。該半導體晶粒可能還含有用於RF訊號處理的IPD，例如，電感器、電容器以及電阻器。於另一實施例中，一被動式組件可能會被黏著至導體柱104d至104e之間的導體層108。
圖3e顯示一利用下面方法被沉積在半導體晶粒110和導體層108的上方的囊封劑或鑄模化合物114：錫膏印刷法(paste printing)、壓縮成型法(compression molding)、轉印成型法(transfer molding)、液態囊封劑成型法(liquid encapsulant molding)、真空層疊法(vacuum lamination)或是其它合宜的塗敷器。囊封劑114可為聚合物複合材料，例如，有填充劑的環氧樹脂、有填充劑的環氧丙烯酸酯或是有合宜填充劑的聚合物。囊封劑114為非導體並且會對該半導體元件進行環境保護，避免受到外部元素和污染物破壞。
在圖3f中，會利用背面研磨(backgrinding)製程移除一部分的囊封劑114、導體層108以及介電層106，以便露出導體柱104d與104e的頂端側。此外，暫時性載板100會應用熱或光來脫除晶種層102。或者，亦可藉由下面製程來移除載板100：化學蝕刻製程、機械式剝除製程、CMP製程、機械式研磨製程、熱烘烤製程、雷射掃描製程、電漿蝕刻製程或是其它大塊材料薄化製程。
在圖3g中，晶種層102、介電層106以及導體層108會藉由蝕刻製程被選擇性移除，用以露出半導體晶粒110的接觸觸墊112以及導體柱104d與104e的底端側。導體柱104d至104e具有垂直(z方向)互連的功能，其會從囊封劑114的其中一側延伸至該囊封劑的反向側。導體柱104a至104c上方的一部分導體層108以及導體柱104a至104c下方的一部分晶種層102仍保持在原來的地方。
圖4所示的為圖3g中的區域115的進一步細節。導體柱104a至104c的運作如同金屬-絕緣體-金屬(MIM)垂直指向之整合電容器116的第一金屬電極。導體層108為MIM電容器116的第二金屬電極。介電層106為該等第一金屬電極和第二金屬電極之間的中間絕緣體。導體層108會延伸到介電層106和晶種層102外面，以達快速互連的目的，而不必電氣短路至導體柱104a至104c。MIM電容器116為三維(3-D)構造，x-方向、y-方向以及z-方向。平行於第一電容器電極和第二電容器電極的平面會垂直於和半導體晶粒110之主動表面平行的平面。MIM電容器116會垂直延伸到囊封劑114之中，以便節省晶粒面積並且提供更大的電容密度。MIM電容器116能夠有大數值，舉例來說，>1奈法拉，以達去耦合的目的，而不需要有和大數值平面式電容器相關聯的典型大覆蓋面積。
在圖5中，一互連結構117會被形成在囊封劑114的上方。該互連結構117包含一整合被動式元件(IPD)。一導電層118會利用沉積和圖樣化製程被形成在囊封劑114、導體層108、以及導體柱104d之頂端側的上方。導體層118會利用PVD製程、CVD製程、電解質電鍍製程、無電極電鍍製程或是其它合宜的金屬沉積製程來構成。導體層108可能為由下面所製成的一或多層：Al、Cu、Sn、Ni、Au、Ag或是其它合宜的導電材料。該第一互連結構117會被電氣連接至導體柱104d至104e以及MIM電容器116。
一電阻層120會利用PVD或CVD被圖樣化且沉積在囊封劑114的上方。電阻層120為鉭質矽化物(TaxSiy)或是其它金屬矽化物、TaN、鎳鉻合金(NiCr)、TiN或是電阻為數介於5和100 ohm/sq之間之經摻雜的多晶矽。
一絕緣層或鈍化層122會被形成在囊封劑114、導體層118以及電阻層120的上方。該鈍化層122可能為SiO2 、Si3 N4 、SiON、Ta2 O5 、Al2 O3 或是具有合宜絕緣特性及結構特性的其它材料。該鈍化層122會利用下面方法被圖樣化或毯覆沈積：PVD、CVD、印刷、旋塗、燒結、熱氧化或是層疊。該鈍化層122可能為單層或是多層。一部分的鈍化層122會被蝕刻製程移除，以便露出導體層118以及電阻層120。
一導電層124會利用圖樣化和沉積製程被形成在鈍化層122以及導體層118的上方。導體層124包含多個個別部分或區段124a至124g。導體層124會利用PVD製程、CVD製程、電解質電鍍製程、無電極電鍍製程或是其它合宜的金屬沉積製程來構成。導體層124可由下面所製成的一或多層：Al、Cu、Sn、Ni、Au、Ag或是其它合宜的導電材料。導體層124中的該等個別部分可電氣共用或是電氣隔離，端視該半導體晶粒的設計以及功能而定。
一絕緣層或鈍化層126會被形成在鈍化層122以及導體層124的上方。該鈍化層126可為SiO2 、Si3 N4 、SiON、Ta2 O5 、Al2 O3 或是具有合宜絕緣特性及結構特性的其它材料。該鈍化層126會利用下面方法被圖樣化或毯覆沈積：PVD、CVD、印刷、旋塗、燒結、熱氧化或是層疊。該鈍化層126可為單層或是多層。一部分的鈍化層126會被蝕刻製程移除，以便露出導體層124。
導體層124b至124e會構成一或多個IPD 117，於本案例中，為一電感器。該等導體層124b至124e通常會纏繞或盤繞在平面圖中，以便產生或呈現所希望的電感特性。導體層124f與124g會電氣連接至電阻層120，成為另一個IPD。
由導體層124b至124e以及電阻層120所構成的IPD會提供高頻應用所需的電氣特性，例如：共振器、高通濾波器、低通濾波器、旁通濾波器、對稱型高Q值共振變壓器、匹配網路以及調諧電容器。該等IPD可以作為能夠被設置在天線和收發器之間的前端無線RF組件。該IPD電感器可為一高Q值平衡/非平衡阻抗轉換器(balun)、變壓器或是線圈，其運作在高達100個十億赫茲處。於某些應用中，多個平衡/非平衡阻抗轉換器會被形成在同一個基板之上，從而允許多頻帶操作。舉例來說，二或多個平衡/非平衡阻抗轉換器會被使用在行動電話或是用於行動通訊(GSM)的其它全球系統的四頻(quad-band)之中，每一個平衡/非平衡阻抗轉換器皆專屬於該四頻元件的一操作頻帶。一典型的RF系統在一或多個半導體封裝之中會需要用到多個IPD以及其它高頻電路，以便實施必要的電氣功能。
該等高頻電氣元件會產生下面非所希的干擾或是會受到下面非所希干擾的影響：電磁干擾(Electromagnetic Interference，EMI)；射頻干擾(Radio Frequency Interference，RFI)；或是其它元件間干擾，例如，電容性、電感性或是傳導性耦合，亦稱為串訊(cross-talk)。電感器124b至124e會被囊封劑114垂直分開並且會偏離半導體晶粒110，以便降低EMI、RFI以及其它元件間干擾。
一互連結構127會被形成在囊封劑114的上方。該互連結構127會電氣連接至導體柱104d至104e、半導體晶粒110以及MIM電容器116。該互連結構127包含一利用圖樣化和沉積製程被形成在囊封劑114、導體層108以及導體柱104d至104e的底端側上方的導電層128。導體層128會利用PVD製程、CVD製程、電解質電鍍製程、無電極電鍍製程或是其它合宜的金屬沉積製程來構成。導體層128可由下面所製成的一或多層：Al、Cu、Sn、Ni、Au、Ag或是其它合宜的導電材料。
一絕緣層或鈍化層130會被形成在囊封劑114、晶種層102以及導體層128的上方。該鈍化層130可為SiO2 、Si3 N4 、SiON、Ta2 O5 、Al2 O3 或是具有合宜絕緣特性及結構特性的其它材料。該鈍化層130會利用下面方法被圖樣化或毯覆沈積：PVD、CVD、印刷、旋塗、燒結、熱氧化或是層疊。該鈍化層130可為單層或是多層。一部分的鈍化層130會被蝕刻製程移除，以便露出導體層108和128。
一導電層132會利用圖樣化和沉積製程被形成在鈍化層130以及導體層128的上方。導體層132會利用PVD製程、CVD製程、電解質電鍍製程、無電極電鍍製程或是其它合宜的金屬沉積製程來構成。導體層132可由下面所製成的一或多層：Al、Cu、Sn、Ni、Au、Ag或是其它合宜的導電材料。
一絕緣層或鈍化層134會被形成在鈍化層130以及導體層132的上方。該鈍化層134可為SiO2 、Si3 N4、SiON、Ta2 O5 、Al2 O3 或是具有合宜絕緣特性及結構特性的其它材料。該鈍化層134會利用下面方法被圖樣化或毯覆沈積：PVD、CVD、印刷、旋塗、燒結、熱氧化或是層疊。該鈍化層134可為單層或是多層。一部分的鈍化層134會被蝕刻製程移除，以便露出導體層132。
一導電焊料材料會利用下面製程被沉積在導體層132的上方：蒸發製程、電解質電鍍製程、無電極電鍍製程、丸滴製程(ball drop)或是網印製程。該焊料材料可為任何金屬或是導電材料，舉例來說，Sn、Ni、Au、Ag、Pb、Bi以及它們的合金，其會有一非必要的助熔材料。舉例來說，該焊料材料可以是Sn/Pb共熔合金、高鉛共熔合金或是無鉛共熔合金。該焊料材料會因將該材料加熱至其熔點以上而被回焊，用以形成球狀的丸體或凸塊136。於某些應用中，焊料凸塊136會二次回焊，以便改善和導體層132的電氣接觸。焊料凸塊136代表能夠被形成在導體層132上方的其中一種類型的互連結構。該互連結構亦能夠使用焊線、3-D互連線、導電膏、短柱凸塊、微凸塊或是其它電氣互連線。
圖6所示的為在一半導體封裝中形成3-D垂直指向之整合電容器的替代實施例。一晶種層140會利用可熱脫模或可光脫模的暫時性黏合膜被塗敷至一暫時性載板，和圖3a雷同。晶種層140可為Cu或是具有濕式蝕刻選擇性的其它金屬薄膜。晶種層140為利用層疊、PVD、CVD或是電化學沉積來沉積。晶種層140可為一暫時性黏合膜或蝕刻阻止層。
複數個導體柱或立柱142a至142d會被形成在晶種層140的上方。一光阻層會被沉積在晶種層140的上方。一部分光阻層會藉由蝕刻顯影製程來曝光並移除。導體柱142a至142d會利用電解質電鍍製程、無電極電鍍製程、或是選擇性電鍍製程被形成在已被移除的光阻部分之中。導體柱142可為Cu、Al、W、Au、焊料或是其它合宜的導電材料。導體柱142的高度範圍從20至200μm，典型數值為50至100μm。該光阻會被剝除，從而留下個別的導體柱142a至142d。
一部分導體柱142d會藉由下面製程被移除：蝕刻製程、研磨製程或是片切製程，和圖3b雷同。經過蝕刻製程之後，導體柱142d的垂直輪廓會降低20至50μm。導體柱142a至142c的垂直輪廓則會保持不變。或者，142a至142c以及142d之間的不同高度能夠藉由步進微影術和電鍍製程來實現。
一介電層144會被保形塗敷在導體柱142a至142d以及晶種層140的上方，和圖3c雷同。該保形介電層144可為SiO2 、Si3 N4 、SiON、Ta2 O5 、Al2 O3 、聚亞醯胺、BCB、PBO或是具有絕緣特性的其它材料。該介電層144會利用下面方法被圖樣化或毯覆沈積：PVD、CVD、印刷、噴塗、旋塗、燒結、熱氧化或是層疊。該介電層144可為單層或是多層。
一導電層148會被圖樣化並保形沉積在介電層144的上方。導體層148會利用PVD製程、CVD製程、電解質電鍍製程、無電極電鍍製程或是其它合宜的金屬沉積製程來構成。導體層148可為由下面所製成的一或多層：Al、Cu、Sn、Ni、Au、Ag或是其它合宜的導電材料。應該注意的係，具有保形介電層144和導體層148的導體柱142d的垂直輪廓仍然小於具有保形介電層144和導體層148的導體柱142a至142c的垂直輪廓。
一半導體晶粒150會被黏著至導體柱142b和142c之間的導體層148，和圖3d雷同。半導體晶粒150包含類比電路或數位電路，該等類比電路或數位電路會被施行為被形成在其主動表面上方的主動式元件和被動式元件、導體層以及介電層，並且會根據該晶粒的電氣設計進行電氣互連。舉例來說，該電路可能包含被形成在該主動表面裡面的一或多個電晶體、二極體以及其它電路器件，用以施行基頻數位電路，例如，DSP、記憶體或是其它訊號處理電路。該半導體晶粒可能還含有用於RF訊號處理的IPD，例如，電感器、電容器以及電阻器。於另一實施例中，一被動式組件可能會被黏著至導體柱142b至142c之間的導體層148。
一囊封劑或鑄模化合物154會利用下面方法被沉積在半導體晶粒150和導體層148的上方：錫膏印刷法、壓縮成型法、轉印成型法、液態囊封劑成型法、真空層疊法或是其它合宜的塗敷器，和圖3e雷同。囊封劑154可為聚合物複合材料，例如，有填充劑的環氧樹脂、有填充劑的環氧丙烯酸酯或是有合宜填充劑的聚合物。囊封劑154為非導體並且會對該半導體元件進行環境保護，避免受到外部元素和污染物破壞。
背面研磨製程會被用來移除一部分的囊封劑154、導體層148以及介電層144，以便露出導體柱142a至142c的頂端側，和圖3f雷同。圖7所示的為被介電層144和導體層148包圍的導體柱142a的俯視圖。此外，該暫時性載板會應用熱或光來脫除晶種層140。或者，亦可藉由下面製程來移除該載板：化學蝕刻製程、機械式剝除製程、CMP製程、機械式研磨製程、熱烘烤製程、雷射掃描製程、電漿蝕刻製程或是其它大塊材料薄化製程。
晶種層140、介電層144以及導體層148會藉由蝕刻製程被選擇性移除，用以露出半導體晶粒150的接觸觸墊152以及導體柱142b與142c的底端側。導體柱142b至142c具有垂直z-互連的功能，其會從囊封劑154的其中一側延伸至該囊封劑的反向側。
和圖4雷同，導體柱142a和142d的運作如同第一垂直指向之整合MIM電容器和第二垂直指向之整合MIM電容器的第一金屬電極。導體層148為該等MIM電容器的第二金屬電極。介電層144為該等第一金屬電極和第二金屬電極之間的中間絕緣體。導體層148會延伸到介電層144和晶種層140外面，以達快速互連的目的，而不必電氣短路至導體柱142a與142d。該等MIM電容器為3-D構造，x-方向、y-方向以及z-方向。平行於第一電容器電極和第二電容器電極的平面會垂直於和半導體晶粒150之主動表面平行的平面。該等MIM電容器會垂直延伸到囊封劑154之中，以便節省晶粒面積並且提供更大的電容密度。該等MIM電容器能夠有大數值，以達去耦合的目的，而不需要有和大數值平面式電容器相關聯的典型大覆蓋面積。
一互連結構156會被形成在囊封劑154的上方。該互連結構156包含一或多個IPD。一導電層158會利用沉積和圖樣化製程被形成在囊封劑154、導體層148以及導體柱142b至142c之頂端側的上方。導體層158會利用PVD製程、CVD製程、電解質電鍍製程、無電極電鍍製程或是其它合宜的金屬沉積製程來構成。導體層158可由下面所製成的一或多層：Al、Cu、Sn、Ni、Au、Ag或是其它合宜的導電材料。導體層158中的該等個別部分可為電氣共用或是電氣隔離，端視該半導體晶粒的設計以及功能而定。
一電阻層159會利用PVD或CVD被圖樣化且沉積在囊封劑154的上方。電阻層159為TaxSiy或是其它金屬矽化物、TaN、NiCr、TiN或是電阻為數介於5和100 ohm/sq之間之經摻雜的多晶矽。
一絕緣層或鈍化層160會被形成在囊封劑154、導體層158以及電阻層159的上方。該鈍化層160可為SiO2、Si3 N4 、SiON、Ta2 O5 、Al2 O3 或是具有合宜絕緣特性及結構特性的其它材料。該鈍化層160會利用下面方法被圖樣化或毯覆沈積：PVD、CVD、印刷、旋塗、燒結、熱氧化或是層疊。該鈍化層160可為單層或是多層。一部分的鈍化層160會被蝕刻製程移除，以便露出導體層148、電阻層159以及導體柱142a。
一導電層162會利用圖樣化和沉積製程被形成在鈍化層160、導體柱142a、導體層148以及電阻層159的上方。導體層162包含多個個別部分或區段162a至162f。導體層162會利用PVD製程、CVD製程、電解質電鍍製程、無電極電鍍製程、或是其它合宜的金屬沉積製程來構成。導體層162可能為由下面所製成的一或多層：Al、Cu、Sn、Ni、Au、Ag或是其它合宜的導電材料。導體層162中的該等個別部分可為電氣共用或是電氣隔離，端視該半導體晶粒的設計以及功能而定。
一絕緣層或鈍化層164會被形成在鈍化層160以及導體層162的上方。該鈍化層164可為SiO2 、Si3 N4 、SiON、Ta2 O5 、Al2 O3 或是具有合宜絕緣特性及結構特性的其它材料。該鈍化層164會利用下面方法被圖樣化或毯覆沈積：PVD、CVD、印刷、旋塗、燒結、熱氧化或是層疊。該鈍化層164可為單層或是多層。一部分的鈍化層164會被蝕刻製程移除，以便露出導體層162。
導體層162c至162e會構成一或多個IPD，於本案例中，為一電感器。該等導體層162c至162e通常會纏繞或盤繞在平面圖中，以便產生或呈現所希的電感特性。導體層162a會電氣連接至導體柱142a以及半導體晶粒150，而導體層162b和162d則會電氣連接至電阻層159，成為另一個IPD。
由導體層162c至162e以及電阻層159所構成的IPD會提供高頻應用所需的電氣特性，例如：共振器、高通濾波器、低通濾波器、旁通濾波器、對稱型高Q值共振變壓器、匹配網路以及調諧電容器。該等IPD可以作為能夠被設置在天線和收發器之間的前端無線RF組件。該IPD電感器可為一高Q值平衡/非平衡阻抗轉換器、變壓器或是線圈，其運作在高達100個十億赫茲處。於某些應用中，多個平衡/非平衡阻抗轉換器會被形成在同一個基板之上，從而允許多頻帶操作。舉例來說，二或多個平衡/非平衡阻抗轉換器會被使用在行動電話或是其它GSM通訊的四頻之中，每一個平衡/非平衡阻抗轉換器皆專屬於該四頻元件的一操作頻帶。一典型的RF系統在一或多個半導體封裝之中會需要用到多個IPD以及其它高頻電路，以便實施必要的電氣功能。
該等高頻電氣元件會產生下面非所希的干擾或是會受到下面非所希干擾的影響：EMI；RFI；或是其它元件間干擾，例如，電容性、電感性或是傳導性耦合，亦稱為串訊。電感器142c至142e會被囊封劑154垂直分開並且會偏離半導體晶粒150，以便降低EMI、RFI以及其它元件間干擾。
一互連結構165會被形成在囊封劑154的上方。該互連結構165會電氣連接至導體柱142b至142c、半導體晶粒150以及MIM電容器142至148。該互連結構165包含一利用圖樣化和沉積製程被形成在囊封劑154、導體層148、以及導體柱142b至142c的底端側上方的導電層166。導體層166會利用PVD製程、CVD製程、電解質電鍍製程、無電極電鍍製程或是其它合宜的金屬沉積製程來構成。導體層166可為由下面所製成的一或多層：Al、Cu、Sn、Ni、Au、Ag或是其它合宜的導電材料。
一絕緣層或鈍化層168會被形成在囊封劑154、晶種層140以及導體層166的上方。該鈍化層168可為SiO2 、Si3 N4 、SiON、Ta2 O5 、Al2 O3 或是具有合宜絕緣特性及結構特性的其它材料。該鈍化層168會利用下面方法被圖樣化或毯覆沈積：PVD、CVD、印刷、旋塗、燒結、熱氧化或是層疊。該鈍化層168可為單層或是多層。一部分的鈍化層168會被蝕刻製程移除，以便露出導體層148和166。
一導電層170會利用圖樣化和沉積製程被形成在鈍化層168以及導體層166的上方。導體層170會利用PVD製程、CVD製程、電解質電鍍製程、無電極電鍍製程或是其它合宜的金屬沉積製程來構成。導體層170可為由下面所製成的一或多層：Al、Cu、Sn、Ni、Au、Ag或是其它合宜的導電材料。
一絕緣層或鈍化層172會被形成在鈍化層168以及導體層170的上方。該鈍化層172可為SiO2 、Si3 N4 、SiON、Ta2 O5 、Al2 O3 或是具有合宜絕緣特性及結構特性的其它材料。該鈍化層172會利用下面方法被圖樣化或毯覆沈積：PVD、CVD、印刷、旋塗、燒結、熱氧化或是層疊。該鈍化層172可為單層或是多層。一部分的鈍化層172會被蝕刻製程移除，以便露出導體層170。
一導電焊料材料會利用下面製程被沉積在導體層170的上方：蒸發製程、電解質電鍍製程、無電極電鍍製程、丸滴製程或是網印製程。該焊料材料可為任何金屬或是導電材料，舉例來說，Sn、Ni、Au、Ag、Pb、Bi以及它們的合金，其會有一非必要的助熔材料。舉例來說，該焊料材料可以是Sn/Pb共熔合金、高鉛共熔合金或是無鉛共熔合金。該焊料材料會因將該材料加熱至其熔點以上而被回焊，用以形成球狀的丸體或凸塊174。於某些應用中，焊料凸塊174會二次回焊，以便改善和導體層170的電氣接觸。焊料凸塊174代表能夠被形成在導體層170上方的其中一種類型的互連結構。該互連結構亦能夠使用焊線、3-D互連線、導電膏、短柱凸塊、微凸塊或是其它電氣互連線。
圖8所示的為半導體晶粒150的俯視圖，其會沿著該晶粒的側邊形成多個3-D垂直指向之整合電容器。導體柱142b和142c提供z方向互連。導體柱142a和142d的運作如同第一和第二垂直指向之整合MIM電容器176的第一金屬電極。導體層148為MIM電容器176的第二金屬電極。介電層144為該等第一金屬電極和第二金屬電極之間的中間絕緣體。
圖9所示的為半導體晶粒150的俯視圖，其會在該晶粒附近形成一3-D垂直指向之整合電容器。導體柱142b和142c提供z方向互連。導體柱142的運作如同垂直指向之整合MIM電容器178的第一金屬電極。導體層148為MIM電容器178的第二金屬電極。介電層144為該等第一金屬電極和第二金屬電極之間的中間絕緣體。
在圖10中顯示一半導體晶粒180，其具有另一3-D垂直指向之整合電容器配置。半導體晶粒180包含類比電路或數位電路，該等類比電路或數位電路會被施行為被形成在其主動表面上方的主動式元件和被動式元件、導體層以及介電層，並且會根據該晶粒的電氣設計進行電氣互連。舉例來說，該電路可能包含被形成在該主動表面裡面的一或多個電晶體、二極體、以及其它電路器件，用以施行基頻數位電路，例如，DSP、記憶體或是其它訊號處理電路。該半導體晶粒可能還含有用於RF訊號處理的IPD，例如，電感器、電容器以及電阻器。
多個矽質中介片184會被放置在半導體晶粒180的每一側之上。每一個矽質中介片184皆包含多個導體柱186以及3-D垂直指向之整合電容器188。矽質中介片184的進一步細節顯示在圖11之中。導體柱186具有垂直z-互連的功能，其會從該矽質中介片的其中一側延伸至該元件的反向側。每一個3-D垂直指向之整合MIM電容器188皆包含外導體層190以及內導體層194。一介電層196會被設置在導體層190和194之間。導體層194的運作如同該MIM電容器的第一金屬電極。導體層190為該MIM電容器的第二金屬電極。介電層196為該等第一金屬電極和第二金屬電極之間的中間絕緣體。矽質材料198會被形成在導體層190和194以及介電層196附近。
另一中介片結構200顯示在圖12之中。導體柱202具有垂直z-互連的功能，其會從該矽質中介片的其中一側延伸至該元件的反向側。每一個3-D垂直指向之整合MIM電容器204皆包含外導體層206以及內導體層208。一介電層210會被設置在導體層206和208之間。導體層206的運作如同該MIM電容器的第一金屬電極。導體層208為該MIM電容器的第二金屬電極。介電層210為該等第一金屬電極和第二金屬電極之間的中間絕緣體。矽質材料211會被形成在導體層206和208以及介電層210附近。
回頭參考圖10，一囊封劑或鑄模化合物212會利用下面方法被沉積在半導體晶粒180和矽質中介片184的上方：錫膏印刷法、壓縮成型法、轉印成型法、液態囊封劑成型法、真空層疊法或是其它合宜的塗敷器，囊封劑212可為聚合物複合材料，例如，有填充劑的環氧樹脂、有填充劑的環氧丙烯酸酯或是有合宜填充劑的聚合物。囊封劑212為非導體並且會對該半導體元件進行環境保護，避免受到外部元素和污染物破壞。
一互連結構214會被形成在囊封劑212的上方。該互連結構214包含一或多個IPD。一導電層216會利用沉積和圖樣化製程被形成在囊封劑212以及矽質中介片184的上方，用以形成個別的部分或區段。導體層216會利用PVD製程、CVD製程、電解質電鍍製程、無電極電鍍製程或是其它合宜的金屬沉積製程來構成。導體層216可能為由下面所製成的一或多層：Al、Cu、Sn、Ni、Au、Ag或是其它合宜的導電材料。導體層216中的該等個別部分可為電氣共用或是電氣隔離，端視該半導體晶粒的設計以及功能而定。
一電阻層218會利用PVD或CVD被圖樣化且沉積在囊封劑212的上方。電阻層218為TaxSiy或是其它金屬矽化物、TaN、NiCr、TiN、是電阻為數介於5和100 ohm/sq之間之經摻雜的多晶矽。
一絕緣層或鈍化層220會被形成在囊封劑212、矽質中介片184、導體層216以及電阻層218的上方。該鈍化層220可為SiO2 、Si3 N4 、SiON、Ta2 O5 、Al2 O3 或是具有合宜絕緣特性及結構特性的其它材料。該鈍化層220會利用下面方法被圖樣化或毯覆沈積：PVD、CVD、印刷、旋塗、燒結、熱氧化或是層疊。該鈍化層220可能為單層或是多層。一部分的鈍化層220會被蝕刻製程移除，以便露出矽質中介片184、導體層216以及電阻層218。
一導電層222會利用圖樣化和沉積製程被形成在鈍化層220、矽質中介片184、導體層216、以及電阻層218的上方。導體層222包含多個個別部分或區段222a至222f。導體層222會利用PVD製程、CVD製程、電解質電鍍製程、無電極電鍍製程或是其它合宜的金屬沉積製程來構成。導體層222可為由下面所製成的一或多層：Al、Cu、Sn、Ni、Au、Ag或是其它合宜的導電材料。導體層222中的該等個別部分可為電氣共用或是電氣隔離，端視該半導體晶粒的設計以及功能而定。
一絕緣層或鈍化層224會被形成在鈍化層220以及導體層222的上方。該鈍化層224可為SiO2 、Si3 N4 、SiON、Ta2 O5 、Al2 O3 或是具有合宜絕緣特性及結構特性的其它材料。該鈍化層224會利用下面方法被圖樣化或毯覆沈積：PVD、CVD、印刷、旋塗、燒結、熱氧化或是層疊。該鈍化層224可能為單層或是多層。一部分的鈍化層224會被蝕刻製程移除，以便露出導體層222。
導體層222c至222e會構成一或多個IPD，於本案例中，為一電感器。該等導體層222c至222e通常會纏繞或盤繞在平面圖中，以便產生或呈現所希的電感特性。導體層222a會電氣連接至MIM電容器188和半導體晶粒180，而導體層222b和222d則會電氣連接至電阻層218，成為另一個IPD。
由導體層222c至222e以及電阻層218所構成的IPD會提供高頻應用所需的電氣特性，例如：共振器、高通濾波器、低通濾波器、旁通濾波器、對稱型高Q值共振變壓器、匹配網路以及調諧電容器。該等IPD可以作為能夠被設置在天線和收發器之間的前端無線RF組件。該IPD電感器可為一高Q值平衡/非平衡阻抗轉換器(balun)、變壓器、或是線圈，其運作在高達100個十億赫茲處。於某些應用中，多個平衡/非平衡阻抗轉換器會被形成在同一個基板之上，從而允許多頻帶操作。舉例來說，二或多個平衡/非平衡阻抗轉換器會被使用在行動電話或是其它GSM通訊的四頻之中，每一個平衡/非平衡阻抗轉換器皆專屬於該四頻元件的一操作頻帶。一典型的RF系統在一或多個半導體封裝之中會需要用到多個IPD以及其它高頻電路，以便實施必要的電氣功能。
一互連結構223會被形成在囊封劑212的上方。該互連結構223會電氣連接至導體柱186、半導體晶粒180、以及MIM電容器188。該互連結構223包含一利用圖樣化和沉積製程被形成在囊封劑212和矽質中介片184上方的導電層226。導體層226會利用PVD製程、CVD製程、電解質電鍍製程、無電極電鍍製程或是其它合宜的金屬沉積製程來構成。導體層226可為由下面所製成的一或多層：Al、Cu、Sn、Ni、Au、Ag或是其它合宜的導電材料。
一絕緣層或鈍化層228會被形成在囊封劑212、矽質中介片184、以及導體層226的上方。該鈍化層228可為SiO2 、Si3 N4 、SiON、Ta2 O5 、Al2 O3 或是具有合宜絕緣特性及結構特性的其它材料。該鈍化層228會利用下面方法被圖樣化或毯覆沈積：PVD、CVD、印刷、旋塗、燒結、熱氧化或是層疊。該鈍化層228可能為單層或是多層。一部分的鈍化層228會被蝕刻製程移除，以便露出導體層186和226。
一導電層230會利用圖樣化和沉積製程被形成在鈍化層228以及導體層226的上方。導體層230會利用PVD製程、CVD製程、電解質電鍍製程、無電極電鍍製程或是其它合宜的金屬沉積製程來構成。導體層230可為由下面所製成的一或多層：Al、Cu、Sn、Ni、Au、Ag或是其它合宜的導電材料。
一絕緣層或鈍化層232會被形成在鈍化層228以及導體層230的上方。該鈍化層232可為SiO2 、Si3 N4 、SiON、Ta2 O5 、Al2 O3 或是具有合宜絕緣特性及結構特性的其它材料。該鈍化層232會利用下面方法被圖樣化或毯覆沈積：PVD、CVD、印刷、旋塗、燒結、熱氧化或是層疊。該鈍化層232可為單層或是多層。一部分的鈍化層232會被蝕刻製程移除，以便露出導體層230。
一導電焊料材料會利用下面製程被沉積在導體層230的上方：蒸發製程、電解質電鍍製程、無電極電鍍製程、丸滴製程或是網印製程。該焊料材料可為任何金屬或是導電材料，舉例來說，Sn、Ni、Au、Ag、Pb、Bi以及它們的合金，其會有一非必要的助熔材料。舉例來說，該焊料材料可以是Sn/Pb共熔合金、高鉛共熔合金、或是無鉛共熔合金。該焊料材料會因將該材料加熱至其熔點以上而被回焊，用以形成球狀的丸體或凸塊234。於某些應用中，焊料凸塊234會二次回焊，以便改善和導體層230的電氣接觸。焊料凸塊234代表能夠被形成在導體層230上方的其中一種類型的互連結構。該互連結構亦能夠使用焊線、3-D互連線、導電膏、短柱凸塊、微凸塊或是其它電氣互連線。
圖13所示的為一種覆晶類型半導體晶粒240，其焊料凸塊242會被黏著至互連結構214中的導體層222a、222b以及222f的頂端表面。半導體晶粒240會電氣連接至整合電容器188、導體柱186、互連結構223以及半導體晶粒180。一類覆晶類型半導體晶粒240亦能夠被黏著至圖5中互連結構117中的導體層124a、124f以及124g的頂端表面，以及圖6中互連結構156中的導體層162a、162b以及162f的頂端表面。
雖然本文已經詳細解釋過本發明的一或多個實施例；不過，熟練的技術人士便會瞭解，可以對該些實施例進行修正與改變，其並不會脫離後面申請專利範圍中所提出的本發明的範疇。
10．．．電子元件
12．．．晶片載體基板或印刷電路板(PCB)
14．．．導體訊號線路
16．．．焊線封裝
18．．．覆晶
20．．．球柵陣列(BGA)
22．．．凸塊晶片載板(BCC)
24．．．雙直列封裝(DIP)
26．．．平台格柵陣列(LGA)
28．．．多晶片模組(MCM)
30．．．方形扁平無導線封裝(QFN)
32．．．方形扁平封裝
34．．．半導體晶粒
36．．．接觸觸墊
38．．．載板
40．．．導體導線
42．．．焊線
44．．．囊封劑
46．．．焊料材料
47．．．半導體晶粒
48．．．接觸觸墊
50．．．底層填充或環氧樹脂膠黏材料
52．．．接觸觸墊
54．．．焊線
56．．．焊接觸墊
58．．．焊接觸墊
60．．．鑄模化合物或囊封劑
64．．．接觸觸墊
66．．．凸塊
70．．．主動區
76．．．載板
78．．．導體焊料凸塊或焊球
80．．．凸塊觸墊
82．．．接觸觸墊或互連部位
84．．．凸塊觸墊或互連部位
86．．．導體焊料凸塊或焊球
88．．．接觸觸墊
90．．．導體線路
92．．．鑄模化合物或囊封劑
100．．．暫時性基板或載板
102．．．晶種層
104a~104e．．．導體柱
106．．．介電層
108．．．導電層
110．．．半導體晶粒
112．．．接觸觸墊
114．．．囊封劑或鑄模化合物
115．．．圖4中所示之區域的細節
116．．．金屬-絕緣體-金屬(MIM)垂直指向之整合電容器
117．．．互連結構
118．．．導體層
120．．．電阻層
122．．．絕緣層或鈍化層
124a~124g．．．導電層部分或區段
126．．．絕緣層或鈍化層
127．．．互連結構
128．．．導電層
130．．．絕緣層或鈍化層
132．．．導電層
134．．．絕緣層或鈍化層
136．．．焊料凸塊
140．．．晶種層
142a~142d．．．導體柱
144．．．介電層
148．．．導電層
150．．．半導體晶粒
152．．．接觸觸墊
154．．．囊封劑或鑄模化合物
156．．．互連結構
158．．．導電層
159．．．電阻層
160．．．絕緣層或鈍化層
162a~162f．．．導體層
164．．．絕緣層或鈍化層
165．．．互連結構
166．．．導體層
168．．．絕緣層或鈍化層
170．．．導電層
172．．．絕緣層或鈍化層
174．．．焊料凸塊
176．．．垂直指向之整合MIM電容器
178．．．垂直指向之整合MIM電容器
180．．．半導體晶粒
182．．．接觸觸墊
184．．．矽質中介片
186．．．導體柱
188．．．垂直指向之整合MIM電容器
190．．．外導體層
194．．．內導體層
196．．．介電層
198．．．矽質材料
200．．．中介片結構
202．．．導體柱
204．．．垂直指向之整合MIM電容器
206．．．外導體層
208．．．內導體層
210．．．介電層
211．．．矽質材料
212．．．囊封劑或鑄模化合物
214．．．互連結構
216．．．導電層
218．．．電阻層
220．．．絕緣層或鈍化層
222a~222f．．．導電層
223．．．互連結構
224．．．絕緣層或鈍化層
226．．．導電層
228．．．絕緣層或鈍化層
230．．．導電層
232．．．絕緣層或鈍化層
234．．．焊料凸塊
240．．．覆晶類型半導體晶粒
242．．．焊料凸塊
圖1所示的為一印刷電路板(PCB)，在其表面上黏著不同類型的封裝；
圖2a至2c所示的為被黏著至該PCB的代表性半導體封裝的進一步細節；
圖3a至3g所示的為在一半導體封裝中形成一3-D垂直指向之整合電容器的製程；
圖4所示的為該3-D垂直指向之整合電容器的進一步細節；
圖5所示的為具有該3-D垂直指向之整合電容器的半導體封裝；
圖6所示的為一半導體封裝中的3-D垂直指向之整合電容器的替代實施例；
圖7所示的為該3-D垂直指向之整合電容器的俯視圖；
圖8所示的為具有該3-D垂直指向之整合電容器的半導體封裝的俯視圖；
圖9所示的為具有該3-D垂直指向之整合電容器另一實施例的半導體封裝的俯視圖；
圖10所示的為在一矽質中介片之中的3-D垂直指向之整合電容器；
圖11所示的為在具有3-D電容器和導體柱的矽質中介片的進一步細節；
圖12所示的為在具有3-D電容器和導體柱的矽質中介片的另一實施例；以及
圖13所示的為被黏著至圖10之頂端側互連結構的覆晶類型半導體晶粒。
102．．．晶種層
104a~104c．．．導體柱
106．．．介電層
108．．．導電層
116．．．金屬-絕緣體-金屬(MIM)垂直指向之整合電容器

Claims (16)

  1. 一種製造半導體元件的方法，其包括：在該半導體元件內形成複數個第一垂直導體結構；在該第一垂直導體結構的上方形成一絕緣層；在該絕緣層和該第一垂直導體結構的上方形成一導體層，作為一垂直指向之電容器；以及將一囊封劑沉積在該垂直指向之電容器的上方，該囊封劑在該第一垂直導體結構之間向下延伸。
  2. 如申請專利範圍第1項的方法，進一步包括：將一半導體晶粒配置在該半導體裝置內，以及將該囊封劑沉積在該半導體晶粒的上方。
  3. 如申請專利範圍第1項的方法，進一步包括：在該囊封劑的一第一表面的上方形成一第一互連結構；在與該囊封劑的第一表面相對的該囊封劑的一第二表面的上方形成一第二互連結構；以及在該第一互連結構以及該第二互連結構之間形成複數個第二垂直導體結構。
  4. 如申請專利範圍第3項的方法，其中，該第一互連結構包括一整合被動式元件。
  5. 如申請專利範圍第2項的方法，其中，該垂直指向之電容器沿著該半導體晶粒的側邊延伸。
  6. 如申請專利範圍第1項的方法，其中，該第一垂直導體結構包括複數個導體柱。
  7. 如申請專利範圍第3項的方法，進一步包括將一半導 體晶粒配置在該第一互連結構或該第二互連結構的上方。
  8. 一種製造半導體元件的方法，其包括：在該半導體元件內形成一垂直指向之電容器；在該半導體元件內形成複數個垂直導體結構，並且包括比該垂直指向之電容器的高度還高之高度；將一第一半導體晶粒或組件配置在該垂直導體結構之間；以及將一囊封劑沉積在該垂直指向之電容器、該垂直導體結構和該第一半導體晶粒或組件的上方。
  9. 如申請專利範圍第8項的方法，其中，形成該垂直指向之電容器包括：在該半導體元件內形成一導體柱；在該導體柱的上方形成一絕緣層；以及在該絕緣層的上方形成一導體層。
  10. 如申請專利範圍第8項的方法，進一步包括：在該囊封劑的一第一表面的上方形成一第一互連結構；以及在與該囊封劑的第一表面相對的該囊封劑的一第二表面的上方形成一第二互連結構，並且透過該垂直導體結構而電連接到該第一互連結構。
  11. 如申請專利範圍第10項的方法，其中，該第一互連結構包括一整合式被動元件。
  12. 如申請專利範圍第10項的方法，進一步包括將一第二半導體晶粒或組件配置在該第一互連結構或該第二互連結構的上方。
  13. 如申請專利範圍第8項的方法，其中，該垂直指向之電容器沿著該第一半導體晶粒或組件延伸。
  14. 一種半導體元件，其包括：一垂直指向之電容器，其包含(a)一導體柱；(b)一絕緣層，其保形地施加在該導體柱的上方；以及(c)一導體層，其保形地施加在該絕緣層的上方；一半導體晶粒，其配置在該半導體元件之內；以及一囊封劑，其沉積在該半導體晶粒和該垂直指向之電容器之上。
  15. 如申請專利範圍第14項的半導體元件，進一步包括：一第一互連結構，其形成在該囊封劑的一第一表面的上方；一第二互連結構，其形成在與該囊封劑的第一表面相對的該囊封劑的一第二表面的上方；以及一垂直導體結構，其形成在該第一互連結構和該第二互連結構之間。
  16. 如申請專利範圍第14項的半導體元件，其中，該垂直指向之電容器沿著該半導體晶粒延伸。
TW099106255A 2009-03-13 2010-03-04 半導體元件和形成三維垂直指向之整合電容器的方法 TWI488261B (zh)

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