CN103715108A - 半导体装置和将密封剂沉积在嵌入式wlcsp中的方法 - Google Patents

半导体装置和将密封剂沉积在嵌入式wlcsp中的方法 Download PDF

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CN103715108A
CN103715108A CN201310164479.8A CN201310164479A CN103715108A CN 103715108 A CN103715108 A CN 103715108A CN 201310164479 A CN201310164479 A CN 201310164479A CN 103715108 A CN103715108 A CN 103715108A
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semiconductor element
conductive layer
semiconductor
insulating barrier
sealant
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CN201310164479.8A
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Inventor
林耀剑
H-P.维尔茨
尹胜煜
P.C.马里穆图
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Stats Chippac Pte Ltd
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Stats Chippac Pte Ltd
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Priority to CN201911325388.1A priority Critical patent/CN110993514A/zh
Publication of CN103715108A publication Critical patent/CN103715108A/zh
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Abstract

半导体装置具有半导体晶片，其包括多个半导体管芯。在该半导体晶片上形成绝缘层。绝缘层的一部分通过LDA而去除来暴露半导体管芯的有源表面的一部分。在半导体管芯的有源表面上的接触盘上形成第一导电层。使半导体晶片单个化来将半导体管芯分开。半导体管芯设置在载体上，其中半导体管芯的有源表面偏离该载体。密封剂沉积在半导体管芯和载体上来覆盖半导体管芯的侧边以及有源表面的暴露部分。互连结构在第一导电层上形成。备选地，MUF材料沉积在半导体管芯的侧边以及有源表面的暴露部分上。

Description

半导体装置和将密封剂沉积在嵌入式WLCSP中的方法
要求国内优先权
本申请要求于2012年10月2日提交的美国临时申请号61/744,699的权益，该申请通过引用合并于此。
技术领域
本发明一般来说涉及半导体装置，并且更特别地，涉及半导体装置和将密封剂沉积在扇出晶片级芯片规模封装（Fo-WLCSP）中的半导体管芯的侧边和有源表面的暴露部分上的方法。
背景技术
通常在现代的电子产品中发现半导体装置。半导体装置在电组件的数量和密度方面不同。分立的半导体装置一般包含一个类型的电组件，例如发光二极管（LED）、小的信号晶体管、电阻器、电容器、感应器和功率金属氧化物半导体场效应晶体管（MOSFET）。集成半导体装置典型地包含数百至数百万的电组件。集成半导体装置的示例包括微控制器、微处理器、带电耦合装置（CCD）、太阳能电池和数字微镜装置（DMD）。
半导体装置执行广泛的功能，例如信号处理、高速计算、传送和接收电磁信号、控制电子装置、将太阳光变换为电以及对电视显示器创建视觉投影。在娱乐、通信、功率转换、网络、计算机和消费者产品的领域中发现半导体装置。还在军事应用、航空、汽车、工业控制器和办公设备中发现半导体装置。
半导体装置利用半导体材料的电特性。半导体材料的结构允许通过施加电场或基极电流或通过掺杂过程而操纵它的电导率。掺杂将杂质引入半导体材料来操纵和控制半导体装置的电导率。
半导体装置包含有源和无源电结构。有源结构（包括双极和场效应晶体管）控制电流的流动。通过改变掺杂水平和施加电场或基极电流，晶体管促进或限制电流的流动。无源结构（包括电阻器、电容器和感应器）创建执行多种电功能所必需的电压和电流之间的关系。无源和有源结构电连接来形成电路，其使半导体装置能够执行高速操作和其他有用的功能。
一般使用两个复杂的制造过程制造半导体装置，即，前端制造和后端制造，每个潜在地牵涉数百个步骤。前端制造牵涉在半导体晶片的表面上形成多个管芯。每个半导体管芯典型地是相同的并且包含通过电连接有源和无源组件而形成的电路。后端制造牵涉使来自完成的晶片的单独半导体管芯单个化并且封装该管芯来提供结构支承和环境隔离。如本文使用的术语“半导体管芯”指词的单数或复数形式两者，并且因此，可以指单个半导体装置和多个半导体装置两者。
半导体制造的一个目标是生产较小的半导体装置。较小的半导体装置典型地消耗更少的电力、具有更高的性能并且可以被更有效地生产。另外，较小的半导体装置具有更小的占用空间，这对于较小的最终产品是可期望的。较小的半导体管芯尺寸可以通过前端过程中的改进而实现，从而导致具有更小、更高密度的有源和无源组件的半导体管芯。后端过程可通过电互连和封装材料中的改进而导致具有较小占用空间的半导体装置封装件。
半导体管芯典型地封闭在半导体封装件内以用于管芯的电互连、结构支承和环境保护。如果半导体管芯的一部分暴露于外部元件，特别地当表面安装管芯时，半导体可能经历损坏或降级。例如，半导体管芯可能在处理和暴露于光期间损坏或降级。
发明内容
存在保护半导体封装件内的半导体管芯的需要。因此，在一个实施例中，本发明是制作半导体装置的方法，其包括以下步骤：提供包括多个半导体管芯的半导体晶片、在该半导体晶片上形成绝缘层、去除绝缘层的一部分来暴露半导体管芯的有源表面的一部分、将半导体管芯单个化来将半导体管芯分开以及将密封剂沉积在半导体管芯上来覆盖半导体管芯的侧边以及半导体管芯的有源表面的暴露部分。
在另一个实施例中，本发明是制作半导体装置的方法，其包括以下步骤：提供半导体管芯、在该半导体管芯上形成绝缘层、去除绝缘层的一部分来暴露半导体管芯的表面的一部分以及将密封剂沉积在半导体管芯上来覆盖半导体管芯的侧边以及半导体管芯的有源表面的暴露部分。
在另一个实施例中，本发明是半导体装置，其包括半导体管芯和在该半导体管芯上形成的绝缘层，其中该半导体管芯的表面的一部分没有绝缘层。密封剂沉积在半导体管芯上来覆盖半导体管芯的侧边以及没有绝缘层的半导体管芯的表面的所述部分。
在另一个实施例中，本发明是半导体装置，其包括半导体管芯和在该半导体管芯上形成的绝缘层，其中该半导体管芯的表面的一部分没有绝缘层。密封剂沉积在半导体管芯上来覆盖没有绝缘层的半导体管芯的表面的一部分。
在另一个实施例中，本发明是制作半导体装置的方法，其包括以下步骤：提供衬底、将半导体管芯安装到衬底、将模塑底部填充材料沉积在半导体管芯的侧表面以及半导体管芯的暴露表面上、和将密封剂沉积在模塑底部填充材料上。
附图说明
图1图示印刷电路板（PCB），其具有安装到它的表面的不同类型的封装件；
图2a-2c图示安装到PCB的代表性半导体封装件的另外的细节；
图3a-3c图示具有由锯道（saw street）分开的多个半导体管芯的半导体晶片；
图4a-4e图示将密封剂沉积在WLCSP中的半导体管芯的侧边以及有源表面的暴露部分上的过程；
图5图示WLCSP，其中半导体管芯的侧边和有源表面的暴露部分用密封剂覆盖；
图6a-6c图示具有由锯道分开的多个半导体管芯的半导体晶片；
图7a-7e图示将密封剂沉积在WLCSP中的半导体管芯的侧边以及有源表面的暴露部分上的另一个过程；以及
图8图示WLCSP，其中半导体管芯的侧边和有源表面的暴露部分用密封剂覆盖；
图9a-9h图示关于WLCSP中的半导体管芯的侧边以及有源表面的一部分沉积MUF材料的过程；
图10图示WLCSP，其中半导体管芯的侧边和有源表面的一部分用MUF材料覆盖；
图11图示设置在半导体管芯与衬底之间的MUF材料；以及
图12图示另一个WLCSP，其中半导体管芯的侧边和有源表面的一部分用MUF材料覆盖。
具体实施方式
在下面的描述中参考图（其中类似的数字代表相同或相似的元件）在一个或多个实施例中描述本发明。尽管根据用于实现本发明的目的的最佳模式描述本发明，本领域内技术人员将意识到意在涵盖如可包括在如由附上的权利要求和它们的等同物限定的本发明的精神和范围内的备选、修改和等同物，如由下面的公开和图支持的。
一般使用两个复杂的制造过程制造半导体装置：前端制造和后端制造。前端制造牵涉在半导体晶片的表面上形成多个管芯。晶片上的每个管芯包含有源和无源电组件，其电连接来形成功能电路。例如晶体管和二极管的有源电组件具有控制电流流动的能力。例如电容器、感应器和电阻器的无源电组件创建执行电路功能所必需的电压和电流之间的关系。
无源和有源组件通过一系列过程步骤（包括掺杂、沉积、光刻、蚀刻和平坦化）在半导体晶片的表面上形成。掺杂通过例如离子注入或热扩散的技术将杂质引入半导体材料内。掺杂过程通过响应于电场或基极电流来动态改变半导体材料电导率而在有源装置中修改半导体材料的电导率。晶体管包含具有在必要时布置以使晶体管能够在施加电场或基极电流时促进或限制电流流动的不同类型和程度的掺杂的区。
有源和无源组件由具有不同电特性的材料层形成。这些层可以通过部分由沉积材料的类型确定的多种沉积技术而形成。例如，薄膜沉积可以牵涉化学气相沉积（CVD）、物理气相沉积（PVD）、电解电镀和无电电镀过程。每个层一般被图案化来形成有源组件、无源组件或这些组件之间的电连接的部分。
后端制造指将完成的晶片切割或单个化为单独半导体管芯并且然后封装该半导体管芯以用于结构支承和环境隔离。为了将半导体管芯单个化，沿晶片的非功能区（叫作锯道或划痕）刻划晶片或使其断裂。使用激光切割工具或锯条来使晶片单个化。在单个化之后，单独半导体管芯安装到封装衬底，其包括用于与其他系统组件互连的插脚或接触盘。在半导体管芯上形成的接触盘然后连接到封装件内的接触盘。可以用焊料凸点、柱凸点、导电膏或引线接合作出电连接。密封剂或其他模塑材料沉积在封装件上来提供物理支承和电隔离。完成的封装件然后插入电系统内并且半导体装置的功能性对其他系统组件变得可用。
图1图示电子装置50，该电子装置50具有芯片载体衬底或印刷电路板（PCB）52，其具有安装在它的表面上的多个半导体封装件。该电子装置50可以具有一个类型的半导体封装件，或多个类型的半导体封装件，这取决于应用。为了说明目的，在图1中示出不同类型的半导体封装件。
电子装置50可以是使用半导体封装件来执行一个或多个电功能的独立系统。备选地，电子装置50可以是较大系统的子组件。例如，电子装置50可以是蜂窝电话、个人数字助理（PDA）、数字视频摄像机（DVC）或其他电子通信装置的一部分。备选地，电子装置50可以是显卡、网络接口卡或可以插入计算机内的其他信号处理卡。半导体封装件可以包括微处理器、存储器、专用集成电路（ASIC）、逻辑电路、模拟电路、RF电路、分立的装置或其他半导体管芯或电组件。小型化和重量减少对于被市场接受的产品是必要的。半导体装置之间的距离必须减小来实现更高的密度。
在图1中，PCB 52为安装在PCB上的半导体封装件的结构支承和电互连提供通用衬底。导电信号迹线54使用蒸发、电解电镀、无电电镀、丝网印刷或其他适合的金属沉积过程在表面上或在PCB 52的层内形成。信号迹线54在半导体封装件中的每个、安装的组件和其他外部系统组件之间提供电通信。迹线54还向半导体封装件中的每个提供电力和接地连接。
在一些实施例中，半导体装置具有两个封装级。第一级封装是用于使半导体管芯机械和电附连到中间载体的技术。第二级封装牵涉使中间载体机械和电附连到PCB。在其他实施例中，半导体装置可仅具有第一级封装，其中管芯直接机械和电安装到PCB。
为了说明目的，若干类型的第一级封装在PCB 52上示出，其包括接合线封装56和倒装芯片58。另外，若干类型的第二级封装示出安装在PCB 52上，其包括球栅阵列（BGA）60、凸点芯片载体（BCC）62、双列直插封装（DIP）64、焊盘栅阵列（LGA）66、多芯片模块（MCM）68、四侧无引脚扁平封装（QFN）70和四侧扁平封装72。取决于系统要求，半导体封装件的任何组合（配置有第一和第二级封装样式的任何组合）以及其他电子组件可以连接到PCB 52。在一些实施例中，电子装置50包括单个附连的半导体封装件，而其他实施例要求多个互连的封装件。通过在单个衬底上组合一个或多个半导体封装件，制造商可以将预制的组件并入电子装置和系统。因为半导体封装件包括高级功能性，电子装置可以使用较不昂贵的组件和流水线制造过程制造。所得的装置不太可能出故障并且制造起来较不昂贵，从而对消费者产生更低的成本。
图2a-2c示出示范性半导体封装件。图2a图示安装在PCB 52上的DIP 64的另外的细节。半导体管芯74包括包含模拟或数字电路的有源区，所述模拟或数字电路实现为根据该管芯的电设计在该芯片内形成并且电互连的有源装置、无源装置、导电层和介电层。例如，该电路可以包括一个或多个晶体管、二极管、感应器、电容器、电阻器和在半导体管芯74的有源区内形成的其他电路元件。接触盘76是一层或多层导电材料，例如铝（Al）、铜（Cu）、锡（Sn）、镍（Ni）、金（Au）或银（Ag），并且电连接到在半导体管芯74内形成的电路元件。在DIP 64的组装期间，半导体管芯74使用金硅共晶层或例如热环氧或环氧树脂的粘附剂材料安装到中间载体78。封装体包括例如聚合物或陶瓷的绝缘封装材料。导体引脚80和接合线82提供半导体管芯74和PCB 52之间的电互连。密封剂84沉积在封装件上，通过防止湿气或颗粒进入封装件并且污染半导体管芯74或接合线82而用于环境保护。
图2b图示安装在PCB 52上的BCC 62的另外的细节。半导体管芯88使用底部填充或环氧树脂粘附剂材料92安装在载体90上。接合线94提供接触盘96和98之间的第一级封装互连。模塑化合物或密封剂100沉积在半导体管芯88和接合线94上来提供装置的物理支承和电隔离。接触盘102使用例如电解电镀或无电电镀的适合的金属沉积过程在PCB 52的表面上形成来防止氧化。接触盘102电连接到PCB 52中的一个或多个导电信号迹线54。凸点104在BCC 62的接触盘98和PCB 52的接触盘102之间形成。
在图2c中，半导体管芯58用倒装芯片样式第一级封装安装而向下面向中间载体106。半导体管芯58的有源区108包含模拟或数字电路，其实现为根据该管芯的电设计形成的有源装置、无源装置、导电层和介电层。例如，该电路可以包括一个或多个晶体管、二极管、感应器、电容器、电阻器和有源区108内的其他电路元件。半导体管芯58通过凸点110电和机械地连接到载体106。
BGA 60使用凸点112用BGA样式第二级封装电并且机械地连接到PCB 52。半导体管芯58通过凸点110、信号线114和凸点112电连接到PCB 52中的导电信号迹线54。模塑化合物或密封剂116沉积在半导体管芯58和载体106上来提供装置的物理支承和电隔离。倒装芯片半导体装置提供从半导体管芯58上的有源装置到PCB 52上的导电轨道的短导电路径，以便减少信号传播距离，降低电容并且改进总体电路性能。在另一个实施例中，半导体管芯58可以使用倒装芯片样式第一级封装而没有中间载体106的情况下直接机械和电连接到PCB 52。
图3a示出具有例如硅、锗、砷化镓、磷化铟或碳化硅的基础衬底材料122用于结构支承的半导体晶片120。多个半导体管芯或组件124在晶片120上形成，它们由非有源的管芯间晶片区域或如上文描述的锯道126分开。锯道126提供切割区域来将半导体晶片120单个化成单独半导体管芯124。在一个实施例中，半导体晶片120直径是200-300毫米（mm）。
图3b示出半导体晶片120的一部分的横截面视图。每个半导体管芯124具有背表面128和包含模拟或数字电路的有源表面130，所述模拟或数字电路实现为根据该管芯的电设计和功能在该管芯内形成并且电互连的有源装置、无源装置、导电层和介电层。例如，该电路可包括一个或多个晶体管、二极管和在有源表面130内形成的其他电路元件，来实现模拟电路或数字电路，例如数字信号处理器（DSP）、ASIC、存储器或其他信号处理电路。半导体管芯124还可包含例如感应器、电容器和电阻器的集成无源装置（IPD）用于RF信号处理。
导电层132使用PVD、CVD、电解电镀、无电电镀过程或其他适合的金属沉积过程在有源表面130上形成。导电层132可以是Al、Cu、Sn、Ni、Au、Ag或其他适合的导电材料的一个或多个层。导电层132作为电连接到有源表面130上的电路的接触盘而操作。导电层132可以形成为并排设置在离半导体管芯124的边缘第一距离处的接触盘，如在图3b中示出的。备选地，导电层132可以形成为在多行中偏离的接触盘，使得第一行接触盘设置在离管芯的边缘第一距离处，并且与该第一行交替的第二行接触盘设置在离管芯的边缘第二距离处。
第一绝缘或钝化层134使用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化而在半导体管芯124和导电层132上形成。绝缘层134包含二氧化硅（SiO2）、氮化硅（Si3N4）、氮氧化硅（SiON）、五氧化二钽（Ta2O5）、氧化铝（Al2O3）、二氧化铪（HfO2）、苯并环丁烯（BCB）、聚酰亚胺（PI）、聚苯并恶唑（PBO）、聚合物或具有相似结构和绝缘特性的其他介电材料的一个或多个层。
导电层或重新分配层（RDL）136使用例如溅射、电解电镀和无电电解电镀的图案化和金属沉积过程而在第一绝缘层134上形成。导电层136可以是Al、Cu、Sn、Ni、Au、Ag或其他适合的导电材料的一个或多个层。导电层136的一部分电连接到半导体管芯124的导电层132。导电层136的其他部分可以电共用或电隔离，这取决于半导体管芯124的设计和功能。
第二绝缘或钝化层134在导电层136和第一绝缘层134上形成。多个绝缘层134和导电层136可以在半导体管芯124的有源表面130上形成。可以执行表面检查来检测钝化或RDL缺陷。
绝缘层134的一部分使用激光器138通过激光直接烧蚀（LDA）而去除来暴露导电层132以及沿半导体管芯124的表面边缘的有源表面130的部分140。即，沿半导体管芯124的表面边缘的有源表面130的部分140没有绝缘层134。备选地，绝缘层134的一部分通过图案化的光致抗蚀剂层的蚀刻过程而去除来暴露导电层132以及沿半导体管芯124的表面边缘的有源表面130的部分140。
在图3c中，导电层142在最后的再钝化后使用PVD、CVD、蒸发、电解电镀、无电电镀或其他适合的金属沉积过程而在导电层132和绝缘层134的暴露部分上形成。导电层142可以是Al、Cu、Sn、Ni、Au、Ag、钨（W）或其他适合的导电材料。导电层142是电连接到导电层132的UBM。UBM 142可以是具有粘附层、阻挡层和种子或润湿层的多金属堆叠。粘附层在导电层132上形成并且可以是钛（Ti）、氮化钛（TiN）、钨化钛（TiW）、Al或铬（Cr）。阻挡层在粘附层上形成并且可以是Ni、NiV、铂（Pt）、钯（Pd）、TiW或铜化铬（CrCu）。阻挡层抑制Cu扩散到管芯的有源区域内。种子层在阻挡层上形成并且可以是Cu、Ni、NiV、Au或Al。UBM 142提供到导电层132的低电阻互连，以及为了焊料润湿性提供对焊料扩散和种子层的阻挡。
在图3d中，使用锯条或激光切割工具144通过锯道126将半导体晶片120单个化为单独半导体管芯124。
图4a-4e与图1和2a-2c有关地图示将密封剂沉积在WLCSP中的半导体管芯的侧边以及有源表面的暴露部分上的过程。图4a示出包含例如硅、聚合物、氧化铍、玻璃或其他适合的低成本刚性材料的牺牲基底材料用于结构支承的载体或临时衬底150的一部分的横截面视图。接口层或双面带152在载体150上形成作为临时粘附接合膜、蚀刻停止层或热释放层。载体150可以是具有多个半导体管芯124的容量的大圆或矩形板（大于300mm）。
来自图3d的半导体管芯124使用例如取和放操作而安装到载体150和接口层152（其中绝缘层134朝载体取向）。图4b示出安装到载体150的接口层152作为重组晶片153的半导体管芯124。半导体管芯124的有源表面130凭借接触接口层的绝缘层134和/或导电层142而不接近或偏离接口层152，即，在接口层152与有源表面130的部分140之间存在间隔。
在图4c中，使用膏印刷、压缩模塑、传递模塑、液态密封剂模塑、真空叠层、旋涂或其他适合的涂抹器将密封剂或模塑化合物154沉积在半导体管芯124和载体150上。密封剂154可以是聚合复合材料，例如具有填充物的环氧树脂、具有填充物的环氧丙烯酸酯或具有合适的填充物的聚合物。密封剂154是非导电的并且在环境上保护半导体装置免受外部元件或污染物影响。特别地，密封剂154沿半导体管芯124的侧边设置并且设置在有源表面130与接口层152之间的间隔中并且从而覆盖半导体管芯124的侧边以及沿半导体管芯的表面边缘直至绝缘层134的有源表面130的暴露部分140。因此，密封剂154覆盖或接触半导体管芯124的至少五个表面，即，半导体管芯的四个侧表面和有源表面130的部分140。
在图4d中，载体150和接口层152通过化学蚀刻、机械去皮、化学机械平坦化（CMP）、机械研磨、热烘、UV光、激光扫描或湿法脱模而去除来暴露绝缘层134和导电层142。密封剂154的一部分使用激光器156通过LDA而去除。备选地，密封剂154的一部分通过图案化的光致抗蚀剂层的蚀刻过程而去除。沿半导体管芯124的表面边缘的有源表面130的部分140以及半导体管芯的侧边仍被密封剂154覆盖作为保护板，用于增加产出，特别当表面安装半导体管芯时。密封剂154还保护半导体管芯124免于降级（由于暴露于光而引起）。通过用等离子体、湿溶剂、一氧化铜或干法清洗中的一个或多个步骤来清洗绝缘层134和导电层142而制备半导体管芯124用于电测试。
在图4e中，导电凸点材料使用蒸发、电解电镀、无电电镀、落球或丝网印刷过程而沉积在导电层142上。在一个实施例中，用落球模板沉积凸点材料，即不需要掩模。凸点材料可以是具有可选的焊剂溶液的Al、Sn、Ni、Au、Ag、铅（Pb）、Bi、Cu、焊料及其组合。例如，凸点材料可以是共晶Sn/Pb、高铅焊料或无铅焊料。凸点材料使用适合的附连或接合过程接合到导电层142。在一个实施例中，通过将材料加热到它的熔点以上来形成球或凸点160而使凸点材料软熔。在一些应用中，凸点160再次被软熔来改进到导电层142的电接触。凸点160还可以压缩接合或热压接合到导电层142。凸点160代表可以在导电层142上形成的一个类型的互连结构。该互连结构还可以使用接合线、导电膏、柱凸点、微凸点或其他电互连。可以在凸点形成之前或之后或在去除载体150后执行激光标记。
用锯条或激光切割工具162通过密封剂154将半导体管芯124单个化为单独嵌入式晶片级球栅阵列（eWLB）或晶片级芯片规模封装（WLCSP）164。图5示出在单个化后的WLCSP 164。在一个实施例中，WLCSP 164具有3.0 x 2.6 x 0.7毫米、间距0.4mm的尺寸。半导体管芯124电连接到凸点160用于外部互连。密封剂154覆盖半导体管芯124的侧边以及有源表面130的部分140来保护半导体管芯的侧边和表面边缘并且增加制造产出，特别在表面安装半导体管芯时。密封剂154还保护半导体管芯124免于降级（由于暴露于光而引起）。WLCSP 164在单个化之前或之后经历电测试。
与图3a相似，图6a-6c图示具有例如硅、锗、砷化镓、磷化铟或碳化硅的基础衬底材料172用于结构支承的半导体晶片170的另一个实施例。多个半导体管芯或组件174在晶片170上形成，它们由非有源的管芯间晶片区域或如上文描述的锯道176分开。锯道176提供切割区域来将半导体晶片170单个化成单独半导体管芯174。在一个实施例中，半导体晶片170直径是200-300毫米（mm）。
图6a示出半导体晶片170的一部分的横截面视图。每个半导体管芯174具有背表面178和包含模拟或数字电路的有源表面180，所述模拟或数字电路实现为根据该芯片的电设计和功能在该芯片内形成并且电互连的有源装置、无源装置、导电层和介电层。例如，该电路可包括一个或多个晶体管、二极管和在有源表面180内形成的其他电路元件，来实现模拟电路或数字电路，例如DSP、ASIC、存储器或其他信号处理电路。半导体管芯174还可包含例如感应器、电容器和电阻器的IPD用于RF信号处理。
导电层182使用PVD、CVD、电解电镀、无电电镀过程或其他适合的金属沉积过程在有源表面180上形成。导电层182可以是Al、Cu、Sn、Ni、Au、Ag或其他适合的导电材料的一个或多个层。导电层182作为电连接到有源表面180上的电路的接触盘而操作。导电层182可以形成为并排设置在离半导体管芯174的边缘第一距离处的接触盘，如在图6a中示出的。备选地，导电层182可以形成为在多行中偏离的接触盘，使得第一行接触盘设置在离管芯的边缘第一距离处，并且与该第一行交替的第二行接触盘设置在离管芯的边缘第二距离处。
导电层184使用PVD、CVD、蒸发、电解电镀、无电电镀或其他适合的金属沉积过程在导电层182上形成。导电层184可以是Al、Cu、Sn、Ni、Au、Ag、W或其他适合的导电材料。导电层184是电连接到导电层182的UBM。UBM 184可以是具有粘附层、阻挡层和种子或润湿层的多金属堆叠。粘附层在导电层182上形成并且可以是Ti、TiN、TiW、Al或Cr。阻挡层在粘附层上形成并且可以是Ni、NiV、Pt、Pd、TiW或CrCu。阻挡层抑制Cu扩散到管芯的有源区内。种子层在阻挡层上形成并且可以是Cu、Ni、NiV、Au或Al。UBM 184提供到导电层182的低电阻互连，以及为了焊料润湿性提供对焊料扩散和种子层的阻挡。
在图6b中，第一绝缘或钝化层186使用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化而在半导体管芯174和导电层184上形成，即在形成UBM 184后发生钝化。绝缘层186包含SiO2、Si3N4、SiON、Ta2O5、Al2O3、HfO2、BCB、PI、PBO、聚合物或具有相似结构和绝缘特性的其他介电材料的一个或多个层。
导电层或RDL 188使用例如溅射、电解电镀和无电电镀的图案化和金属沉积过程而在第一绝缘层186上形成。导电层188可以Al、Cu、Sn、Ni、Au、Ag或其他适合的导电材料的一个或多个层。导电层188的一部分电连接到半导体管芯174的导电层182。导电层188的其他部分可以电共用或电隔离，这取决于半导体管芯174的设计和功能。
第二绝缘或钝化层186在导电层188和第一绝缘层186上形成。多个绝缘层186和导电层188可以在半导体管芯174的有源表面180上形成。可以执行表面检查来检测钝化或RDL缺陷。
绝缘层186的一部分使用激光器190通过LDA而去除来暴露导电层184以及沿半导体管芯174的表面边缘的有源表面180的部分192。即，沿半导体管芯174的表面边缘的有源表面180的部分192没有绝缘层186。备选地，绝缘层186的一部分通过图案化的光致抗蚀剂层的蚀刻过程而去除来暴露导电层182以及沿半导体管芯174的表面边缘的有源表面180的部分192。
在图6c中，使用锯条或激光切割工具194通过锯道176将半导体晶片170单个化为单独半导体管芯174。
图7a-7e与图1和2a-2c有关地图示将密封剂沉积在WLCSP中的半导体管芯的侧边以及有源表面的暴露部分上的另一个过程。图7a示出包含例如硅、聚合物、氧化铍、玻璃或其他适合的低成本刚性材料的牺牲基底材料用于结构支承的载体或临时衬底200的一部分的横截面视图。接口层或双面带202在载体200上形成作为临时粘附接合膜、蚀刻停止层或热释放层。载体200可以是具有多个半导体管芯174的容量的大圆或矩形板（大于300mm）。
来自图6c的半导体管芯174使用例如取和放操作而安装到载体200和接口层202（其中绝缘层186朝载体取向）。图7b示出安装到载体200的接口层202作为重组晶片203的半导体管芯174。半导体管芯174的有源表面180凭借接触接口层的绝缘层186而不接近或偏离接口层202，即，在接口层202与有源表面180的部分192之间存在间隔。
在图7c中，使用膏印刷、压缩模塑、传递模塑、液态密封剂模塑、真空叠层、旋涂或其他适合的涂抹器将密封剂或模塑化合物204沉积在半导体管芯174和载体200上。密封剂204可以是聚合复合材料，例如具有填充物的环氧树脂、具有填充物的环氧丙烯酸酯或具有合适的填充物的聚合物。密封剂204是非导电的并且在环境上保护半导体装置免受外部元件或污染物影响。特别地，密封剂204沿半导体管芯174的侧边设置并且设置在有源表面180与接口层202之间的间隔中并且从而覆盖半导体管芯174的侧边以及沿半导体管芯的表面边缘直至绝缘层186的有源表面180的暴露部分192。因此，密封剂204覆盖或接触半导体管芯174的至少五个表面，即，半导体管芯的四个侧表面和有源表面180的部分192。
在图7d中，载体200和接口层202通过化学蚀刻、机械去皮、CMP、机械研磨、热烘、UV光、激光扫描或湿法脱模而去除来暴露绝缘层186和导电层184。密封剂204的一部分使用激光器206通过LDA而去除。备选地，密封剂204的一部分通过图案化的光致抗蚀剂层的蚀刻过程而去除。沿半导体管芯124的表面边缘的有源表面180的部分192以及半导体管芯的侧边仍被密封剂204覆盖作为保护板，用于增加产出，特别当表面安装半导体管芯时。密封剂204还保护半导体管芯174免于降级（由于暴露于光而引起）。通过用等离子体、湿溶剂、一氧化铜或干法清洗中的一个或多个步骤来清洗绝缘层186和导电层184而制备半导体管芯174用于电测试。
在图7e中，导电凸点材料使用蒸发、电解电镀、无电电镀、落球或丝网印刷过程而沉积在导电层184上。在一个实施例中，用落球模板沉积凸点材料，即不需要掩模。凸点材料可以是具有可选的焊剂溶液的Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及其组合。例如，凸点材料可以是共晶Sn/Pb、高铅焊料或无铅焊料。凸点材料使用适合的附连或接合过程接合到导电层184。在一个实施例中，通过将材料加热到它的熔点以上来形成球或凸点210而使凸点材料软熔。在一些应用中，凸点210再次被软熔来改进到导电层184的电接触。凸点210还可以压缩接合或热压接合到导电层184。凸点210代表可以在导电层184上形成的一个类型的互连结构。该互连结构还可以使用接合线、导电膏、柱凸点、微凸点或其他电互连。可以在凸点形成之前或之后或在去除载体200后执行激光标记。
用锯条或激光切割工具212通过密封剂204将半导体管芯174单个化为单独eWLB或WLCSP 214。图8示出在单个化后的WLCSP 214。在一个实施例中，WLCSP 214具有3.0 x 2.6 x 0.7毫米、间距0.4mm的尺寸。半导体管芯174电连接到凸点210用于外部互连。密封剂204覆盖半导体管芯174的侧边以及有源表面180的部分192来保护半导体管芯174的侧边和表面边缘并且增加制造产出，特别在表面安装半导体管芯时。密封剂204还保护半导体管芯174免于降级（由于暴露于光而引起）。WLCSP 214在单个化之前或之后经历电测试。
图9a-9h与图1和2a-2c有关地图示将MUF材料沉积在WLCSP中的半导体管芯的侧边以及有源表面的暴露部分上的过程。图9a示出半导体管芯220（与图3a相似，来自半导体晶片），其具有背表面222和包含模拟或数字电路的有源表面224，所述模拟或数字电路实现为根据该管芯的电设计和功能在该管芯内形成并且电互连的有源装置、无源装置、导电层和介电层。例如，电路可包括一个或多个晶体管、二极管和在有源表面224内形成的其他电路元件来实现例如DSP、ASIC、存储器或其他信号处理电路的模拟电路或数字电路。半导体管芯220还可包含例如感应器、电容器和电阻器的IPD，用于RF信号处理。在一个实施例中，半导体管芯220是倒装芯片类型半导体管芯。
导电层226使用PVD、CVD、电解电镀、无电电镀过程或其他适合的金属沉积过程在有源表面224上形成。导电层226可以是Al、Cu、Sn、Ni、Au、Ag或其他适合的导电材料的一个或多个层。导电层226作为电连接到有源表面224上的电路的接触盘而操作。
导电层228使用溅射、电解电镀、无电电镀的图案化和金属沉积过程而在导电层226上形成。导电层228可以是Al、Cu、Sn、Ni、Au、Ag、W或其他适合的导电材料。导电层228是电连接到导电层226的UBM。UBM 228可以是具有粘附层、阻挡层和种子或润湿层的多金属堆叠。粘附层在导电层226上形成并且可以是Ti、TiN、TiW、Al或Cr。阻挡层在粘附层上形成并且可以是Ni、NiV、Pt、Pd、TiW或CrCu。阻挡层抑制Cu扩散到管芯的有源区域内。种子层在阻挡层上形成并且可以是Cu、Ni、NiV、Au或Al。UBM 228提供到导电层226的低电阻互连，以及为了焊料润湿性提供对焊料扩散和种子层的阻挡。
导电凸点材料使用蒸发、电解电镀、无电电镀、落球或丝网印刷过程而沉积在导电层228上。凸点材料可以是具有可选的焊剂溶液的Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及其组合。例如，凸点材料可以是共晶Sn/Pb、高铅焊料或无铅焊料。凸点材料使用适合的附连或接合过程接合到导电层228。在一个实施例中，通过将材料加热到它的熔点以上来形成球或凸点230而使凸点材料软熔。在一些应用中，凸点230再次被软熔来改进到导电层228的电接触。凸点230还可以压缩接合或热压接合到导电层228。凸点230代表可以在导电层228上形成的一个类型的互连结构。该互连结构还可以使用柱凸点、微凸点或其他电互连。
半导体管芯220使用例如取和放操作而安装到衬底232（其中凸点230朝衬底取向）。衬底232包括导电迹线234，用于垂直和横向互连通过衬底。图9b示出安装到衬底232作为重组晶片236的半导体管芯220，其中凸点230冶金和电接合到导电迹线234。半导体管芯220的有源表面224凭借凸点230而不接近或偏离衬底232，即，在有源表面224的部分238与衬底232之间存在间隔。衬底232可以是具有多个半导体管芯220的容量的大圆或矩形板（大于300 mm）。
在图9c中，使用膏印刷、压缩模塑、传递模塑、液态密封剂模塑、真空叠层、旋涂、模具底部填充或其他适合的施加过程将模具底部填充（MUF）材料240沉积在半导体管芯220和衬底232上。MUF材料240可以是聚合复合材料，例如具有填充物的环氧树脂、具有填充物的环氧丙烯酸酯或具有合适的填充物的聚合物。MUF材料240是非导电的并且在环境上保护半导体装置免受外部元件或污染物影响。特别地，MUF材料240沿半导体管芯220的侧边设置并且设置在有源表面224与衬底232之间的间隔中并且从而覆盖半导体管芯220的侧边以及沿半导体管芯的表面边缘的有源表面224的暴露部分238。
在图9d中，用锯条或激光切割工具239通过MUF材料240和衬底232将半导体管芯220单个化来将半导体管芯与衬底单元分开。
图9e示出包含例如硅、聚合物、氧化铍、玻璃或其他适合的低成本刚性材料的牺牲基底材料用于结构支承的载体或临时衬底242的一部分的横截面视图。接口层或双面带243在载体150上形成为临时粘附接合膜、蚀刻停止层或热释放层。载体242可以是具有多个半导体管芯220和衬底232单元的容量的大圆或矩形板（大于300mm）。
半导体管芯220和衬底232单元使用例如取和放操作而安装到载体242和接口层243（其中衬底朝载体取向）。图9f示出安装到载体242的接口层243的半导体管芯220和衬底232单元。
使用膏印刷、压缩模塑、传递模塑、液态密封剂模塑、真空叠层、旋涂或其他适合的涂抹器将密封剂或模塑化合物244沉积在MUF材料240、衬底232和载体242上。密封剂244可以是聚合复合材料，例如具有填充物的环氧树脂、具有填充物的环氧丙烯酸酯或具有合适的填充物的聚合物。密封剂244是非导电的并且在环境上保护半导体装置免受外部元件或污染物影响。
在图9g中，载体242和接口层243通过化学蚀刻、机械去皮、CMP、机械研磨、热烘、UV光、激光扫描或湿法脱模而去除来暴露衬底232和密封剂244。密封剂244的一部分使用激光器245通过LDA而去除。备选地，密封剂244的一部分通过图案化的光致抗蚀剂层的蚀刻过程而去除。
在图9h中，导电凸点材料使用蒸发、电解电镀、无电电镀、落球或丝网印刷过程而沉积在与半导体管芯220相对的衬底232的导电层234上。凸点材料可以是具有可选的焊剂溶液的Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及其组合。例如，凸点材料可以是共晶Sn/Pb、高铅焊料或无铅焊料。凸点材料使用适合的附连或接合过程接合到导电层234。在一个实施例中，通过将材料加热到它的熔点以上而使凸点材料软熔来形成球或凸点246。在一些应用中，凸点246再次被软熔来改进到导电层234的电接触。凸点246还可以压缩接合或热压接合到导电层234。凸点246代表可以在导电层234上形成的一个类型的互连结构。该互连结构还可以使用接合线、导电膏、柱凸点、微凸点或其他电互连。
可以在凸点形成之前或之后或在去除载体242后执行激光标记。组装件经历等离子体清洗和焊剂印刷。
用锯条或激光切割工具248通过密封剂244将半导体管芯220单个化为单独eWLB或WLCSP 250。图10示出在单个化后的WLCSP 250。在一个实施例中，WLCSP 250具有3.0 x 2.6 x 0.7毫米、间距0.4mm的尺寸。半导体管芯220电连接到衬底232和凸点246用于外部互连。MUF材料240覆盖半导体管芯220的侧边以及有源表面224的部分238来保护半导体管芯的侧边和表面边缘并且增加制造产出，特别在表面安装半导体管芯时。MUF材料240还保护半导体管芯220免于降级（由于暴露于光而引起）。WLCSP 250在单个化之前或之后经历电测试。
与图10相似，图11图示WLCSP 254的实施例，其中MUF材料240设置在半导体管芯220下方并且密封剂244覆盖半导体管芯的侧表面。
图12图示包括半导体管芯260（与图3a相似，来自半导体晶片）的实施例，其具有背表面262和包含模拟或数字电路的有源表面264，所述模拟或数字电路实现为根据该管芯的电设计和功能在该管芯内形成并且电互连的有源装置、无源装置、导电层和介电层。例如，电路可包括一个或多个晶体管、二极管和在有源表面264内形成的其他电路元件来实现例如DSP、ASIC、存储器或其他信号处理电路的模拟电路或数字电路。半导体管芯260还可包含例如感应器、电容器和电阻器的IPD，用于RF信号处理。在一个实施例中，半导体管芯260是接合线类型半导体管芯。
导电层266使用PVD、CVD、电解电镀、无电电镀过程或其他适合的金属沉积过程在有源表面264上形成。导电层266可以是Al、Cu、Sn、Ni、Au、Ag或其他适合的导电材料的一个或多个层。导电层266作为电连接到有源表面264上的电路的接触盘而操作。
与图9a-9b相似，半导体管芯260用例如环氧树脂的管芯附连粘附剂270而安装到衬底268。衬底268包括导电迹线272，用于垂直和横向互连通过衬底。接合线274在半导体管芯260的导电层266与衬底268上的导电迹线272之间形成。衬底268可以是具有多个半导体管芯260的容量的大圆或矩形板（大于300mm）。
与图9c相似，使用膏印刷、压缩模塑、传递模塑、液态密封剂模塑、真空叠层、旋涂或其他适合的涂抹器将密封剂或模塑化合物276沉积在半导体管芯260和衬底268上。密封剂276可以是聚合复合材料，例如具有填充物的环氧树脂、具有填充物的环氧丙烯酸酯或具有合适的填充物的聚合物。密封剂276是非导电的并且在环境上保护半导体装置免受外部元件或污染物影响。
与图9d相似，半导体管芯260通过密封剂276和衬底268而被单个化。与图9e相似，单个化的半导体管芯260和衬底268安装到载体。与图9f相似，使用膏印刷、压缩模塑、传递模塑、液态密封剂模塑、真空叠层、旋涂或其他适合的涂抹器将密封剂或模塑化合物278沉积在密封剂276和衬底268上。密封剂278可以是聚合复合材料，例如具有填充物的环氧树脂、具有填充物的环氧丙烯酸酯或具有合适的填充物的聚合物。密封剂278是非导电的并且在环境上保护半导体装置免受外部元件或污染物影响。去除载体。
导电凸点材料使用蒸发、电解电镀、无电电镀、落球或丝网印刷过程而沉积在与半导体管芯260相对的衬底268的导电层272上。凸点材料可以是具有可选的焊剂溶液的Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及其组合。例如，凸点材料可以是共晶Sn/Pb、高铅焊料或无铅焊料。凸点材料使用适合的附连或接合过程接合到导电层272。在一个实施例中，通过将材料加热到它的熔点以上而使凸点材料软熔来形成球或凸点280。在一些应用中，凸点280再次被软熔来改进到导电层272的电接触。凸点280还可以压缩接合或热压接合到导电层272。凸点280代表可以在导电层272上形成的一个类型的互连结构。该互连结构还可以使用接合线、导电膏、柱凸点、微凸点或其他电互连。
可以在凸点形成之前或之后或在去除载体后执行激光标记。组装件经历等离子体清洗和焊剂印刷。
通过密封剂244将半导体管芯260单个化为单独eWLB或WLCSP 282，其具有3.0 x 2.6 x 0.7毫米、间距0.4mm的尺寸。半导体管芯260电连接到衬底268和凸点280用于外部互连。密封剂276覆盖半导体管芯260的侧表面来保护半导体管芯的表面边缘并且增加制造产出，特别在表面安装半导体管芯时。
尽管已经详细地图示本发明的一个或多个实施例，技术人员将意识到可对那些实施例作出修改和调整而不偏离如在附上的权利要求中阐述的本发明的范围。

Claims (15)

1.一种制作半导体装置的方法，包括：
提供包括多个半导体管芯的半导体晶片；
在所述半导体晶片上形成绝缘层；
去除所述绝缘层的一部分以暴露所述半导体管芯的有源表面的一部分；
使所述半导体晶片单个化以将所述半导体管芯分开；以及
将密封剂沉积在所述半导体管芯上以覆盖所述半导体管芯的侧边以及所述半导体管芯的所述有源表面的暴露部分。
2.如权利要求1所述的方法，进一步包括在所述半导体管芯的所述有源表面上的接触盘上形成导电层。
3.如权利要求1所述的方法，进一步在所述绝缘层内形成导电层。
4.如权利要求1所述的方法，进一步包括通过激光直接烧蚀而去除所述绝缘层的所述部分。
5.一种制作半导体装置的方法，包括：
提供半导体管芯；
在所述半导体管芯上形成绝缘层；
去除所述绝缘层的一部分以暴露所述半导体管芯的表面的一部分；以及
将密封剂沉积在所述半导体管芯上以覆盖所述半导体管芯的侧边以及所述半导体管芯的有源表面的暴露部分。
6.如权利要求5所述方法，进一步包括：
提供载体；
将所述半导体管芯设置在所述载体上，其中所述半导体管芯的所述表面偏离所述载体；
将所述密封剂沉积在所述半导体管芯和载体上以覆盖所述半导体管芯的所述侧边以及所述半导体管芯的所述有源表面的所述暴露部分；以及
去除所述载体。
7.如权利要求5所述的方法，进一步包括在所述半导体管芯的所述表面上的接触盘上形成导电层。
8.如权利要求7所述的方法，进一步包括在所述导电层上形成互连结构。
9.如权利要求5所述的方法，进一步包括在所述绝缘层内形成导电层。
10.一种半导体装置，包括：
半导体管芯；
绝缘层，其在所述半导体管芯上形成，其中所述半导体管芯的表面的一部分没有所述绝缘层；以及
密封剂，其沉积在所述半导体管芯上以覆盖所述半导体管芯的侧边以及没有所述绝缘层的所述半导体管芯的所述表面的所述部分。
11.如权利要求10所述的半导体装置，进一步包括在所述绝缘层以及所述半导体管芯的所述表面上的接触盘上形成的导电层。
12.如权利要求10所述的半导体装置，进一步包括在所述半导体管芯的所述表面上的接触盘上形成的导电层。
13.如权利要求12所述的半导体装置，进一步包括在所述导电层上形成的互连结构。
14.如权利要求10所述的半导体装置，其中，所述密封剂接触所述半导体管芯的至少五个表面。
15.如权利要求10所述的半导体装置，进一步包括在所述绝缘层内形成的导电层。
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