CN102130101A - 围绕凸块形成区形成具有多层ubm的凸块结构的半导体器件和方法 - Google Patents

围绕凸块形成区形成具有多层ubm的凸块结构的半导体器件和方法 Download PDF

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CN102130101A
CN102130101A CN2010105870898A CN201010587089A CN102130101A CN 102130101 A CN102130101 A CN 102130101A CN 2010105870898 A CN2010105870898 A CN 2010105870898A CN 201010587089 A CN201010587089 A CN 201010587089A CN 102130101 A CN102130101 A CN 102130101A
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conductive layer
forms
projection
layer
insulating barrier
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CN102130101B (zh
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林耀剑
方建敏
陈康
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Changdian Integrated Circuit Shaoxing Co ltd
Stats Chippac Pte Ltd
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Stats Chippac Pte Ltd
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Abstract

一种具有在其有效表面上形成的第一导电层的半导体晶圆。在所述基片和所述第一导电层上形成第一绝缘层。在所述第一导电层和所述第一绝缘层上形成第二导电层。在所述第二导电层上围绕凸块形成区形成UBM层。所述UBM层可以是两层堆叠的金属层或三层堆叠的金属层。所述第二导电层被暴露在所述凸块形成区中。在所述UBM层和所述第二导电层上形成第二绝缘层。在所述凸块形成区和所述UBM层的一部分上去除所述第二绝缘层的一部分。在所述凸块形成区中的所述第二导电层上形成凸块。所述凸块接触所述UBM层以密封所述凸块和所述第二导电层之间的接触界面。

Description

围绕凸块形成区形成具有多层UBM的凸块结构的半导体器件和方法
技术领域
本发明一般涉及一种半导体器件，并且更具体地，涉及一种围绕凸块形成区在半导体晶圆上形成具有多层UBM的凸块结构的半导体器件和方法。
发明背景
半导体器件普遍地应用于现代电子产品中。半导体器件在电子元件的数量和密度上不同。分立半导体器件一般包含一种类型的电子元件，例如发光二级管(LED)、微弱信号晶体管、电阻器、电容器、电感器和功率金属氧化物半导体场效应晶体管(MOSFET)。集成半导体器件典型地包含几百至几百万个电子元件。集成半导体器件的示例包括微控制器、微处理器、电荷耦合器件(CCD)、太阳能电池和数字微镜器件(DMDs)。
半导体器件执行广范围的功能，诸如高速计算、发送和接收电磁信号、控制电子设备、将日光转换为电，以及为电视显示器产生视像投射。半导体器件被应用于娱乐、通信、能量变换、网络、计算机和消费品领域中。半导体器件也被应用于军事应用、航空、汽车、工业控制器和办公设备。
半导体器件利用半导体材料的电气特性。半导体材料的原子结构允许通过施加电场或基极电流或通过掺杂(doping)的工艺而使其导电性被操纵。掺杂(doping)将杂质引入到半导体材料中以操纵并控制所述半导体器件的导电性。
半导体器件包括有源(active)和无源(passive)电结构。有 源结构，包括双极和场效应晶体管，控制电流的流动。通过改变掺杂的程度以及施加电场或基极电流，该晶体管促进或限制电流的流动。无源结构，包括电阻器、电容器和电感器，产生执行各种电子功能所需的电压和电流之间的关系。无源和有源结构被电气连接以形成电路，该电路能使半导体器件执行高速计算和其他有用的功能。
通常使用两种复杂的制造工艺，即前端制造(front-end manufacturing)和后端制造(back-end manufacturing)来制造半导体器件，每种制造工艺均涉及可能的几百个步骤。前端制造涉及在半导体晶圆的表面上形成多个裸片(die)。每个裸片通常是相同的并包括通过电连接有源和无源元件而形成的电路。后端制造涉及从完成的晶圆分离(singulating)单个裸片并封装所述裸片以提供结构支撑和环境隔离。
半导体制造的一个目的是生产较小的半导体器件。较小的器件通常消耗较少的能量，具有较高的性能，并能被更有效率地生产。此外，较小的半导体器件具有较小的覆盖区(footprint)，这对于较小的最终产品而言是期望的。较小的裸片尺寸可以通过前端工艺的改进而实现，所述前端工艺的改进导致具有较小、较高密度的有源和无源元件的裸片。通过电气互连和封装材料的改进，后端工艺可以产生具有较小覆盖区的半导体器件封装。
图1显示了在半导体晶圆10上形成的常规凸块结构，其包含用于结构支撑的底部基片材料，诸如硅、锗、砷化镓、磷化铟、或碳化硅。多个半导体裸片被形成在半导体晶圆10上。每个半导体裸片具有包含模拟或数字电路的有效表面(active surface)12，所述模拟或数字电路被实现为在所述裸片内形成并根据所述裸片的电设计和功能而电气互连的有源器件、无源器件、传导层和介电层。在有效表面12上形成金属互连焊盘14。金属焊盘14被电连接到有效表面12上的电路。在有效表面12和金属焊盘14上形成钝化层(passivation layer)16。通过蚀刻工艺去除钝化层16的一部分以暴露金属焊盘14。 在金属焊盘14和钝化层16上形成导电层18。导电层18用作再分布层(RDL)以延伸金属焊盘14的水平互连。在导电层18和钝化层16上形成钝化层20。通过蚀刻工艺去除钝化层20的一部分以暴露导电层18。在钝化层20的去除的部分中的导电层18上形成凸块22。
凸块22和RDL18之间的接触界面常遭受阻碍(rejection)或失效，特别是在制造可靠性测试期间。钝化层20旨在保持凸块和RDL18之间的接触界面的密封。然而，如果钝化层20与凸块22分层，则湿气可以穿透所述钝化材料和凸块之间的空隙并引起凸块22和RDL18之间的接触界面周围的氧化。所述氧化弱化了所述接触界面。该器件会被后置可靠性检查拒绝，或者该器件会在现场出现故障。
发明内容
存在减少半导体器件上的凸块结构的故障的需求。因此，在一个实施例中，本发明是制造半导体器件的方法，包括如下步骤：提供基片；在所述基片上形成第一导电层；在所述基片和所述第一导电层上形成第一绝缘层；去除所述第一绝缘层的一部分以暴露所述第一导电层；在所述第一导电层和所述第一绝缘层上形成第二导电层；并在所述第二导电层上围绕凸块形成区形成UBM层。所述第二导电层被暴露在所述凸块形成区中。该方法进一步包括如下步骤：在所述UBM层和所述第二导电层上形成第二绝缘层；去除所述凸块形成区和所述UBM层的一部分上的所述第二绝缘层的一部分；以及在所述凸块形成区中的所述第二导电层上形成凸块。所述凸块接触所述UBM层以密封所述凸块和所述第二导电层之间的接触界面。
在另一实施例中，本发明是制造半导体器件的方法，包括如下步骤：提供基片；在所述基片上形成第一导电层；在所述基片上形成第一绝缘层；在所述第一导电层和所述第一绝缘层上形成第二导电层；以及在所述第二导电层上围绕互连形成区形成多层金属化图案。所述第二导电层在所述互连形成区中被暴露。该方法进一步包括在所述互 连形成区之外的所述第二导电层和所述多层金属化图案上形成第二绝缘层，以及在所述互连形成区中的所述第二导电层上形成互连结构。
在另一实施例中，本发明是制造半导体器件的方法，包括如下步骤：提供基片；在所述基片上形成第一导电层；在所述第一导电层上围绕互连形成区形成多层金属化图案；在所述互连形成区之外的所述第一导电层和所述多层金属化图案上形成第一绝缘层；以及在所述互连形成区中的所述第一导电层上形成互连。
在另一实施例中，本发明是半导体器件，包括半导体裸片和在所述半导体裸片上形成的第一导电层。在所述半导体裸片上形成第一绝缘层。在所述第一导电层和所述第一绝缘层上形成第二导电层。在所述第二导电层上围绕互连形成区形成多层金属化图案。在所述凸块形成区之外的所述第二导电层和所述多层金属化图案上形成的第二绝缘层。在所述互连形成区中的所述第二导电层上形成互连结构。
附图说明
图1示出了在半导体晶圆上形成的常规凸块结构；
图2示出了具有被安装到其表面的不同类型的封装(package)的PCB；
图3a-3c示出了被安装到PCB的代表性的半导体封装的进一步的细节；
图4a-4h示出了围绕凸块形成区形成具有两层UBM的凸块结构的工艺；
图5示出了具有围绕凸块的底部(base)形成的三层UBM的另一凸块结构；
图6示出了其中接触凸块的钝化层的另一凸块结构；
图7示出了具有围绕凸块的底部形成的连续的两层UBM的另一凸块结构。
具体实施方式
参考附图，在下面的说明中，以一个或多个实施例描述了本发明，其中同样的标号表示相同或类似的元件。虽然依据实现本发明目的的最佳模式描述了本发明，本领域技术人员将可以理解其旨在涵盖如由随附的权利要求和它们的等同物(如由随后的说明和附图所支持的)所定义的本发明的精神和范围内所包括的改变、修改和等同物。
通常使用两种复杂的制造工艺来制造半导体器件：前端制造(front-end manufacturing)和后端制造(back-end manufacturing)。前端制造涉及在半导体晶圆的表面上形成多个裸片。晶圆上的每个裸片包括有源和无源电子元件，所述电子元件被电连接以形成功能电路。诸如晶体管和二极管的有源电子元件具有控制电流的流动的能力。诸如电容器、电感器、电阻器和变压器的无源电子元件产生执行电路功能所需的电压和电流之间的关系。
通过包括掺杂、沉积、光刻(photolithography)、蚀刻和平面化(planarization)的一系列工艺步骤，在半导体晶圆的表面上形成无源和有源元件。通过诸如离子注入或热扩散技术，掺杂将杂质引入到半导体材料中。掺杂工艺修改有源器件中的半导体材料的导电性，将所述半导体材料转化为绝缘体、导体，或响应于电场或基极电流动态地改变半导体材料导电性。晶体管包括被布置为一旦施加电场或基极电流能使晶体管促进或限制电流的流动所须的变化掺杂的类型和程度的区域。
有源和无源元件由具有不同电特性的材料层形成。这些层可以通过部分由被沉积的材料类型所确定的各种沉积技术而被形成。例如，薄膜沉积可以涉及化学气相沉积(CVD)、物理气相沉积(PVD)、电解电镀和无电镀工艺。每层通常都被图案化以形成有源元件、无源元件或元件之间的电连接的部分。
可以使用光刻将这些层图案化，所述光刻涉及在要被图案化的层 上沉积光敏材料，例如光致抗蚀剂。利用光将图案从光掩膜转换为光致抗蚀剂。利用溶剂去除受到光照的光致抗蚀剂图案的一部分，暴露要被图案化的基层(underlying layer)的一部分。去除剩下的光致抗蚀剂，留下图案化层。可替换地，使用诸如无电镀和电解电镀的技术通过将材料直接沉积到先前沉积/蚀刻工艺形成的区域或空隙(void)而将一些类型的材料图案化。
在已有图案上沉积材料的薄膜会放大基图案并产生不均匀的平面。产生更小和更紧密封装的有源和无源元件需要均匀的平面。平面化可以被用于从晶圆的表面去除材料并产生均匀的平面。平面化涉及用抛光垫抛光晶圆的表面。在抛光期间将研磨材料和腐蚀性化学品加到晶圆的表面。结合的研磨材料的机械作用以及化学品的腐蚀作用去除任何不规则的外形，产生均匀的平面。
后端制造指将完成的晶圆切割或分离成单个裸片并随后封装所述裸片用于结构支撑和环境隔离。为了分离所述裸片，沿着被称为切割道(saw streets)或划线(scribe)的晶圆的非功能区刻划并断裂(broken)该晶圆。使用激光切割工具或锯条分离晶圆。在分离后，所述单个裸片被安装到包括引脚或接触盘的封装基片，所述引脚或接触盘用于与其他系统元件互连。半导体裸片上形成的接触盘随后被连接到所述封装内的接触盘上。可以使用焊料块、柱形凸块、导电浆料(paste)或丝焊进行电连接。在封装上沉积密封剂或其他模型材料以提供物理支撑和电绝缘。随后将完成的封装插入到电子系统中，并且使得半导体器件的功能性对于其他系统元件是可用的。
图2示出了具有芯片载体基片或印刷电路板(PCB)52的半导体器件50，所述芯片载体基片或印刷电路板(PCB)52芯片载体基片或印刷电路板(PCB)52，其中在其表面上安装有多个半导体封装。根据应用，电子器件50可以具有一种类型的半导体封装，或者具有多种类型的半导体封装。为了说明的目的，图2示出了不同类型的半导体封装。
电子器件50可以是使用半导体封装以执行一个或多个电子功能的独立的系统。可替换地，电子器件50可以是较大系统的子元件。例如，电子器件50可以是图形卡、网络接口卡或其它能被插入到计算机中的信号处理卡。半导体封装可以包括微处理器、存储器、专用集成电路(ASIC)、逻辑电路、模拟电路、RF电路、分立器件或其他半导体裸片或电子元件。
在图2中，PCB52提供总基片，用于被安装在PCB上的半导体封装的结构支撑和电互连。使用汽化、电解电镀、无电镀、丝网印刷或其他合适的金属沉积工艺在表面上或PCB 52的层内形成导电信号迹线(trace)54。信号迹线54提供半导体封装、安装的元件和其他外部系统元件中的每个之间的电通信。迹线54也提供电源和到每个半导体封装的地连接。
在一些实施例中，半导体器件具有两个封装级。第一级封装是用于将半导体裸片机械地和电气地附接到中间载体的技术。第二级封装涉及将所述中间载体机械地和电气地附接到PCB。在其他实施例中，半导体器件可以只具有第一级封装，其中所述裸片被机械地和电气地直接安装到所述PCB。
为了说明的目的，PCB 52上所示是若干种类型的第一级封装，包括丝焊封装56和倒装芯片(flip chip)58。此外，所示出的被安装到PCB 52上的是若干种类型的第二级封装，包括球阵列封装(BGA)60、凸点芯片载体(BCC)62、双列直插式封装(DIP)64、栅格阵列封装(LGA)66、多芯片组件(MCM)68、四侧无引脚扁平封装(QFN)70和四侧引脚扁平封装72。根据系统需求，用第一和第二级封装类型的任何组合配置的任何半导体封装的组合以及其他电子元件都可以被连接到PCB 52。在一些实施例中，电子器件50包括单个附接的半导体封装，而其他实施例调用多个互连的封装。通过在单个基片上结合一个或多个半导体封装，制造者可以将预制造元件合并到电子器件和系统中。因为半导体封装包括复杂的功能性，可以使用较便宜的 元件和流水线制造工艺制造电子器件。所述生成的器件更不容易出现故障，并且制造也较不昂贵，从而导致消费者的更低的花费。
图3a-3c显示了示例性的半导体封装。图3a示出了被安装到PCB52上的DIP 64的进一步细节，半导体裸片74包括包含模拟或数字电路的有源区，该模拟或数字电路被实现为在裸片中形成并根据所述裸片的电设计而被电互连的有源器件、无源器件、导电层和介电层。例如，所述电路可以包括一个或多个晶体管、二极管、电感器、电容器、电阻器和在半导体裸片74的所述有源区内形成的其他电路元件。接触盘76是一个或多个导电材料(诸如铝(Al)、铜(Cu)、锡(Sn)、镍(Ni)、金(Au)或银(Ag))层，并被电连接到在半导体裸片74中形成的电路元件上。在DIP 64的组装期间，使用金硅共晶层或诸如热环氧树脂的粘合材料将半导体裸片74安装到中间载体78。封装体包括诸如聚合体和陶瓷的绝缘封装材料。导线引线80和丝焊82提供半导体裸片74和PCB 52之间的电互连。密封剂84被沉积在封装上，用于通过避免湿气和微粒进入封装并污染裸片74或丝焊82而进行环境保护。
图3b示出了被安装到PCB 52上的BCC 62的进一步细节。使用底层填料(underfill)或环氧树脂粘合材料92将半导体裸片88安装到载体90上。丝焊94提供接触盘96和98之间的第一级封装互连。将模塑化合物或密封剂100沉积在半导体裸片88和丝焊94上以提供对所述器件的物理支撑和电绝缘。使用诸如电解电镀或无电镀的合适的金属沉积在PCB 52的表面上形成接触盘102以避免氧化。接触盘102被电连接到PCB 52中的一个或多个导电信号迹线54。在BCC 62的接触盘98和PCB 52的接触盘102之间形成凸块104。
在图3c中，用倒装芯片型的第一级封装面向下的将半导体裸片58安装到中间载体106。半导体裸片58的有源区108包含模拟或数字电路，所述模拟或数字电路被实现为根据所述裸片的电设计而被形成的有源器件、无源器件、导电层和介电层。例如，所述电路可以包 括一个或多个晶体管、二极管、电感器、电容器、电阻器和在有源区108中的其他电路元件。半导体裸片58通过凸块110而被电气地和机械地连接到载体106。
使用凸块112，用BGA型第二级封装将BGA 60电气地和机械地连接到PCB 52。半导体裸片58通过凸块110、信号线114和凸块112被电连接到PCB 52中的导电信号迹线54。在半导体裸片58和载体106上沉积模塑化合物或密封剂116以为所述器件提供物理支撑和电绝缘。所述倒装芯片半导体器件提供从半导体裸片58上的有源器件到PCB 52上的导电轨迹(conduction tracks)的短导电路径以便减少信号传播距离，降低电容，并提高整体电路性能。在另一实施例中，使用倒装芯片型第一级封装，半导体裸片58可以被机械地和电气地直接连接到PCB 52，而没有中间载体106。
相对于图2和图3a-3c，图4a-4h示出了围绕凸块形成区形成具有两层UBM的凸块结构的工艺。图4a显示了包含的底部基片材料(诸如硅、锗、砷化镓、磷化铟、或碳化硅)的半导体晶圆120，用于结构支撑。使用上述工艺在由切割道124分离的半导体晶圆120上形成多个半导体裸片122。每个半导体裸片或元件122具有包含模拟或数字电路的有效表面126，所述模拟或数字电路被实现为在所述裸片内形成并根据所述裸片的电设计和功能电互连的有源器件、无源器件、导电层和介电层。例如，该电路可以包括一个或多个晶体管、二极管和在有效表面126内形成的其他电路元件以实现模拟电路或数字电路，诸如数字信号处理器(DSP)、ASIC、存储器或其他信号处理电路。半导体裸片122也可以包括用于RF信号处理的集成无源器件(IPD)，诸如电感器、电容器和电阻器。
在图4b中，使用图案化和沉积工艺(诸如PVD、CVD、溅射、电解电镀和无电镀)在半导体晶圆120的有效面积126上形成导电层130a和130b。导电层130a和130b可以是一个或多个Al、Cu、Sn、Ni、Au、Ag或其他合适的导电材料的层。导电层130a和130b是被电 连接到有效表面126上的电路的金属互连盘。
使用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化，在导电层130和基片120的有效表面126上形成绝缘或钝化层132。该绝缘层132可以是一个或多个二氧化硅(SiO2)、氮化硅(Si3N4)、氧氮化硅(SiON)、五氧化钽(Ta2O5)、氧化铝(Al2O3)、光敏聚合物电介质(如聚酰亚胺、WPR、PBO、BCB)或具有类似绝缘和结构特性的其他材料的层。通过蚀刻工艺去除绝缘层132的一部分以暴露导电层130a和130b。
在图4c中，使用图案化和沉积工艺(诸如电解电镀和无电镀)在导电层130和绝缘层132上形成种晶层134。种晶层134可以是Ti/Cu、TiW/Cu、Ta/Cu、Cr/Cu、Ni、Ti(TiW、Cr、Al)/NiV(Cr、TaN)/Cu、钒化镍(NiV)、Au或Al。
在种晶层134上沉积光致抗蚀层136。通过暴露以及由蚀刻工艺去除，导电层130a和130b以及种晶层134上的光致抗蚀层136的一部分被图案化。使用沉积工艺(诸如PVD、CVD、溅射、电解电镀和无电镀)在光致抗蚀层136的被去除的部分中的种晶层134上形成导电层138。导电层138可以是一个或多个Al、Cu、Sn、Ni、Au、Ag或其他合适的导电材料的层。导电层138用作RDL以延伸互连盘130a和130b的互联性。导电层138在互连盘130a和130b之间可以是连续的或在互连盘之间是电绝缘的。在一个实施例中，导电层138在图案化的光致抗蚀层136中被选择性地镀Cu。种晶层134用作Cu导电层138的阻挡层和润湿层层。
在图4d中，光致抗蚀层136被去除。围绕凸块或被指定为以后形成互连凸块的互连形成区144在导电层138上形成导电层140。并在导电层140上形成导电层142。导电层140和142可以是使用图案化和沉积工艺(诸如PVD、CVD、溅射、电解电镀和无电镀)而被沉积的一个或多个合适的导电材料的层。导电层140和142形成多层金属化图案或包括阻挡层和粘合层的UBM。在一个实施例中，导电层140 是包含Ni、NiV、TiW、铜化铬(CrCu)、铂(Pt)或钯(Pd)的阻挡层。导电层142是包含Al、钛(Ti)、铬(Cr)或氮化钛(TiN)的粘合层。UBM 140-142提供了低电阻互连，以及Cu或焊料扩散进入有效表面126的阻挡。
图4e显示了具有凸块形成区144的UBM 140-142的顶视图。在一个实施例中，UBM 140-142被图案化并被沉积为完全围绕凸块形成区144的环形或相对于凸块形成区144的封闭结构。因此，凸块形成区144位于UBM 140-142的中心。可替换地，在区域144上沉积并随后从区域144蚀刻UBM 140-142以形成环形或封闭结构。在其他实施例中，UBM 140-142部分地围绕区域144形成。
在图4f中，利用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化在导电层138和UBM 140-142以及基片120上形成绝缘或钝化层146。该绝缘层146可以是一个或多个SiO2、Si3N4、SiON、Ta2O5、Al2O3或具有类似绝缘和结构特性的其他材料的层。通过蚀刻工艺去除绝缘层146的一部分以暴露区域144中的导电层138和围绕区域144的边缘的UBM 140-142的一部分。图4g显示了覆盖一部分UBM 140-142的绝缘层146的顶视图。没有被绝缘层146覆盖的UBM 140-142的剩余部分形成完全围绕凸块形成区144的环形。随后固化该绝缘层146。
在图4h中，使用汽化、电解电镀、无电镀、滴球(ball drop)或丝网印刷工艺在区域144上沉积导电凸块材料。所述凸块材料可以是具有可选的焊剂溶液(flux solution)的Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及其组合。例如，所述凸块材料可以是共晶Sn/Pb，高铅焊料或无铅焊料。使用合适的附接或焊接工艺将该凸块材料焊接到导电层138和UBM 140-142。在一个实施例中，通过将所述材料加热超过其熔点而重熔(reflow)该凸块材料以形成球体或凸块148。在一些应用中，凸块148被第二次重熔以改进到导电层138和UBM140-142的电接触。该凸块也可以被压接到导电层138和UBM 140-142。凸块148代表可以在导电层138和UBM 140-142上形成的一种类型的 互连结构。所述互连结构也可以使用柱形凸块、微凸块、导电柱或其他电互连。
有效表面126上的电路通过互连盘130a和130b、RDL138和凸块148而被电连接到外部器件。尽管绝缘层146可以或不可以接触凸块148，凸块148接触UBM 140-142。在任何情况下，绝缘层146的分层不再是可靠性问题，因为围绕凸块148的UBM 140-142的封闭结构保持凸块148和导电层138之间的接触界面的密封。导电层140是阻挡层以阻碍Cu扩散，并且导电层142是粘合层以形成对凸块148的湿气紧密密封。UBM 140-142通过避免湿气穿透到凸块148和导电层138之间(这样会引起所述接触界面的氧化和弱化)的接触界面而提高了可靠性。UBM 140-142减少了该器件的检查拒绝(inspection rejection)或故障。
在另一实施例中，继续上至图4c所述的结构，光致抗蚀层136被去除并围绕凸块或被指定为以后形成互连凸块的互连形成区144在导电层138上形成导电层150，如图5所示。在导电层150上形成导电层152，并在导电层152上形成导电层154。导电层150-154可以是使用图案化和沉积工艺(诸如PVD、CVD、溅射、电解电镀和无电镀)而被沉积的一个或多个合适的导电材料的层。导电层150-154形成多层金属化图案或包括在粘合层之间的阻挡层的UBM。在一个实施例中，导电层154是包含Al、Ti、Cr、TiN或TiW的粘合层；导电层152是包含Ni、NiV、TiW、CrCu、NiV、Pt或Pd的阻挡层；以及导电层150是包含Al、Ti、Cr、TiN或TiW的粘合层。UBM 150-154的顶视图类似于图4e。UBM 150-154提供低电阻互连，以及对Cu或焊料扩散进入有效表面126的阻挡。
使用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化在导电层138和UBM 150-154上形成绝缘或钝化层156。该绝缘层156可以是一个或多个SiO2、Si3N4、SiON、Ta2O5、Al2O3或具有类似绝缘和结构特性的其他材料的层。类似于图4g，通过蚀刻工艺去除绝缘层156的一 部分以暴露区域144中的导电层138和UBM 150-154的一部分。绝缘层156覆盖UBM 150-154的一部分。没有被绝缘层156覆盖的UBM150-154的剩余部分形成完全围绕凸块形成区144的环形。随后该绝缘层156被固化。
使用汽化、电解电镀、无电镀、滴球(ball drop)或丝网印刷工艺在区域144上沉积导电凸块材料。所述凸块材料可以是具有可选的焊剂溶液的Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及其组合。例如，所述凸块材料可以是共晶Sn/Pb，高铅焊料或无铅焊料。使用合适的附接或焊接工艺将该凸块材料焊接到导电层138和UBM 150-154。在一个实施例中，通过将所述材料加热超过其熔点而重熔(reflow)该凸块材料以形成球体或凸块158。在一些应用中，凸块158被第二次重熔以改进到导电层138和UBM 150-154的电接触。所述凸块也可以被压接到导电层138和UBM 150-154。凸块158代表可以在导电层138和UBM 150-154上形成的一种类型的互连结构。所述互连结构也可以使用柱形凸块、微凸块、导电柱或其他电互连。
有效表面126上的电路通过互联盘130a和130b、RDL138和凸块158被电连接到外部器件。尽管绝缘层156可以或不可以接触凸块158，凸块158接触UBM 150-154。在任何情况下，绝缘层156的分层不再是可靠性问题，因为围绕凸块158的UBM 150-154的封闭结构保持凸块158和导电层138之间的接触界面的密封。UBM 150-154通过避免湿气穿透到凸块158和导电层138之间(这样会引起所述接触界面的氧化和弱化)的接触界面而提高了可靠性。UBM 150-154减少了该器件的检查拒绝或故障。
在另一实施例中，继续上至图4c所述的结构，光致抗蚀层136被去除并围绕被指定为以后形成互连凸块的中央凸块形成区144在导电层138上形成导电层160，如图6所示。并在导电层160上形成导电层162。导电层160-162可以是使用图案化和沉积工艺(诸如PVD、CVD、溅射、电解电镀和无电镀)而被沉积的一个或多个合适的导电 材料的层。导电层160-162形成多层金属化图案或包括在粘合层之间的阻挡层的UBM。在一个实施例中，导电层162是包含Al、Ti、Cr、TiN或TiW的粘合层，以及导电层160是包含Ni、NiV、TiW、CrCu、NiV、Pt或Pd的阻挡层。UBM 160-162提供了低电阻互连，以及对Cu或焊料扩散进入有效表面126的阻挡。
在一个实施例中，UBM 160-162被图案化并被沉积为完全围绕凸块形成区144的环形或相对于凸块形成区144的封闭结构。因此，凸块形成区144位于UBM 160-162的中心。可替换地，在区域144上沉积并随后从区域144蚀刻UBM 160-162以形成所述环形或封闭结构。
使用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化在导电层138和UBM 160-162以及基片120上形成绝缘或钝化层164。该绝缘层164可以是一个或多个SiO2、Si3N4、SiON、Ta2O5、Al2O3或具有类似绝缘和结构特性的其他材料的层。通过蚀刻工艺去除绝缘层164的一部分以暴露区域144中的导电层138和UBM 160-162的一部分。随后固化该绝缘层164。
使用汽化、电解电镀、无电镀、滴球(ball drop)或丝网印刷工艺在区域144上沉积导电凸块材料。所述凸块材料可以是具有可选的焊剂溶液的Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及其组合。例如，所述凸块材料可以是共晶Sn/Pb，高铅焊料或无铅焊料。使用合适的附接或焊接工艺将该凸块材料焊接到导电层138和UBM 160-162。在一个实施例中，通过将所述材料加热超过其熔点以重熔(reflow)该凸块材料，以形成球体或凸块166。在一些应用中，凸块166被第二次重熔以改进到导电层138和UBM 160-162的电接触。所述凸块也可以被压接到导电层138和UBM 160-162。凸块166代表可以在导电层138和UBM 160-162上形成的一种类型的互连结构。所述互连结构也可以使用柱形凸块、微凸块、导电柱或其他电互连。
有效表面126上的电路通过互联盘130a和130b、RDL138和凸块158被电连接到外部器件。所述绝缘层164接触凸块166。然而，绝 缘层164的分层仍然不再是可靠性问题，因为UBM 160-162保持凸块166和导电层138之间的接触界面的密封。UBM 160-162通过避免湿气穿透到凸块166和导电层138之间(这样会引起所述接触界面的氧化和弱化)的接触界面提高了可靠性。UBM 160-162减少了该器件的拒绝或故障。
在另一实施例中，继续上至图4c所述的结构，光致抗蚀层136被去除并在导电层138上形成导电层170，如图7所示。导电层170覆盖了导电层138，除了被指定为以后形成互连凸块的中央凸块形成区144之外。在导电层170上形成导电层172。导电层170和172可以是使用图案化和沉积工艺(诸如PVD、CVD、溅射、电解电镀和无电镀)而被沉积的一个或多个合适的导电材料的层。导电层170-172形成多层金属化图案或包括阻挡层和粘合层的UBM。在一个实施例中，导电层170是包含Ni、NiV、TiW、CrCu、NiV、Pt或Pd的阻挡层。导电层172是包含Al、Ti、Cr、TiN或TiW的粘合层。UBM 170-172提供了低电阻互连，以及对Cu或焊料扩散进入有效表面126的阻挡。
使用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化在导电层138和UBM 170-172以及基片120上形成绝缘或钝化层174。该绝缘层174可以是一个或多个SiO2、Si3N4、SiON、Ta2O5、Al2O3或具有类似绝缘和结构特性的其他材料的层。通过蚀刻工艺去除绝缘层174的一部分以暴露区域144中的导电层138和UBM 170-172的一部分。即，所述绝缘层164覆盖UBM 170-172的一部分。没有被绝缘层164覆盖的UBM 170-172的剩余部分形成完全围绕凸块形成区144的环形。随后该绝缘层174被固化。
使用汽化、电解电镀、无电镀、滴球(ball drop)或丝网印刷工艺在区域144上沉积导电凸块材料。所述凸块材料可以是具有可选的焊剂溶液的Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及其组合。例如，所述凸块材料可以是共晶Sn/Pb，高铅焊料或无铅焊料。使用合适的附接或焊接工艺将该凸块材料焊接到导电层138和UBM 170-172。 在一个实施例中，通过将所述材料加热超过其熔点而重熔(reflow)该凸块材料，以形成球体或凸块176。在一些应用中，凸块176被第二次重熔以改进到导电层138和UBM 170-172的电接触。所述凸块也可以被压接到导电层138和UBM 170-172。凸块176代表可以在导电层138和UBM 170-172上形成的一种类型的互连结构。所述互连结构也可以使用柱形凸块、微凸块、导电柱或其他电互连。
有效表面126上的电路通过互联盘130a和130b、RDL138和凸块176被电连接到外部器件。尽管绝缘层174可以或不可以接触凸块176，凸块176接触UBM 170-172。在任何情况下，绝缘层174的分层不再是可靠性问题，因为UBM 170-172保持凸块176和导电层138之间的接触界面的密封。UBM 170-172通过避免湿气穿透到凸块176和导电层138之间(这样会引起所述接触界面的氧化和弱化)的接触界面提高了可靠性。UBM 170-172减少了该器件的检查拒绝或故障。
虽然已详细描述了本发明的一个或多个实施例，但本领域技术人员应当理解：可以进行对这些实施例的修改和改进，而不脱离如在随后的权利要求中所提出的本发明的范围。

Claims (25)

1.一种制造半导体器件的方法，所述方法包括：
提供基片；
在所述基片上形成第一导电层；
在所述基片和所述第一导电层上形成第一绝缘层；
去除所述第一绝缘层的一部分以暴露所述第一导电层；
在所述第一导电层和所述第一绝缘层上形成第二导电层；
在所述第二导电层上围绕凸块形成区形成凸块下金属化(UBM)层，所述第二导电层被暴露在所述凸块形成区中；
在所述UBM层和所述第二导电层上形成第二绝缘层；
去除所述凸块形成区和所述UBM层的一部分上的所述第二绝缘层的一部分；以及
在所述凸块形成区中的所述第二导电层上形成凸块，所述凸块接触所述UBM层以密封所述凸块和所述第二导电层之间的接触界面。
2.根据权利要求1所述的方法，其特征在于，其中形成所述UBM层包括：
在所述第二导电层上形成第三导电层；以及
在所述第三导电层上形成第四导电层，所述第四导电层与所述凸块接触。
3.根据权利要求2所述的方法，其特征在于，其中所述第四导电层包括从由铝、钛、铬、氮化钛和钛钨组成的组中选择的材料。
4.根据权利要求1所述的方法，其特征在于，其中形成所述UBM层包括：
在所述第二导电层上形成第三导电层；
在所述第三导电层上形成第四导电层；
在所述第四导电层上形成第五导电层，所述第五导电层与所述凸块接触。
5.根据权利要求1所述的方法，其特征在于，其中所述第二绝缘层接触所述凸块。
6.根据权利要求1所述的方法，其特征在于，其中所述UBM层覆盖所述凸块形成区外的所述第二导电层。
7.根据权利要求1所述的方法，其特征在于，所述方法进一步包括在形成所述第二导电层之前在所述第一导电层和所述第一绝缘层上形成种晶层。
8.一种制造半导体器件的方法，所述方法包括：
提供基片；
在所述基片上形成第一导电层；
在所述基片上形成第一绝缘层；
在所述第一导电层和所述第一绝缘层上形成第二导电层；
在所述第二导电层上围绕互连形成区形成多层金属化图案，所述第二导电层被暴露在所述互连形成区中；
在所述互连形成区之外的所述多层金属化图案和所述第二导电层上形成第二绝缘层；
在所述互连形成区中的所述第二导电层上形成互连结构。
9.根据权利要求8所述的方法，其特征在于，其中形成所述多层金属化图案包括：
在所述第二导电层上形成第三导电层；以及
在所述第三导电层上形成第四导电层，所述第四导电层与所述互连结构接触。
10.根据权利要求9所述的方法，其特征在于，其中所述第四导电层包括从由铝、钛、铬、氮化钛和钛钨组成的组中选择的材料。
11.根据权利要求8所述的方法，其特征在于，其中形成所述多层金属化图案包括：
在所述第二导电层上形成第三导电层；
在所述第三导电层上形成第四导电层；以及
在所述第四导电层上形成第五导电层，所述第五导电层与所述互连接触。
12.根据权利要求8所述的方法，其特征在于，其中所述互连结构包括凸块。
13.根据权利要求8所述的方法，其特征在于，其中所述多层金属化图案覆盖所述互连形成区之外的所述第二导电层。
14.根据权利要求8所述的方法，其特征在于，所述方法进一步包括在形成所述第二导电层之前在所述第一导电层和所述第一绝缘层上形成种晶层。
15.一种制造半导体器件的方法，所述方法包括：
提供基片；
在所述基片上形成第一导电层；
在所述第一导电层上围绕互连形成区形成多层金属化图案；
在所述互连形成区之外的所述多层金属化图案和所述第一导电层上形成第一绝缘层；
在所述互连形成区中的所述第一导电层上形成互连。
16.根据权利要求15所述的方法，其特征在于，所述方法进一步包括：
在形成所述第一导电层之前在所述基片上形成第二导电层；
在所述基片上形成第一绝缘层；以及
在所述第一导电层和所述第一绝缘层上形成种晶层。
17.根据权利要求15所述的方法，其特征在于，其中形成所述多层金属化图案包括：
在所述第一导电层上形成第二导电层；以及
在所述第二导电层上形成第三导电层，所述第三导电层与所述互连接触。
18.根据权利要求15所述的方法，其特征在于，其中形成所述多层金属化图案包括：
在所述第一导电层上形成第二导电层；
在所述第二导电层上形成第三导电层；以及
在所述第三导电层上形成第四导电层，所述第四导电层与所述互连接触。。
19.根据权利要求15所述的方法，其特征在于，其中所述互连包括凸块。
20.一种半导体器件，包括：
半导体裸片；
在所述半导体裸片上形成的第一导电层；
在所述半导体裸片上形成的第一绝缘层；
在所述第一导电层和所述第一绝缘层上形成的第二导电层；
在所述第二导电层上围绕互连形成区形成的多层金属化图案；
在所述凸块形成区之外的所述多层金属化图案和所述第二导电层上形成的第二绝缘层；以及
在所述互连形成区中的所述第二导电层上形成的互连结构。
21.根据权利要求20所述的半导体器件，其特征在于，所述半导体器件进一步包括：
在所述第二导电层上形成的第三导电层；以及
在所述第三导电层上形成的第四导电层，所述第四导电层与所述互连结构接触。
22.根据权利要求20所述的半导体器件，其特征在于，所述半导体器件进一步包括：
在所述第二导电层上形成的第三导电层；
在所述第三导电层上形成的第四导电层；以及
在所述第四导电层上形成的第五导电层，所述第五导电层与所述互连结构接触。
23.根据权利要求20所述的半导体器件，其特征在于，其中所述互连结构包括凸块。
24.根据权利要求20所述的半导体器件，其特征在于，其中所述多层金属化图案覆盖所述互连形成区之外的所述第二导电层。
25.根据权利要求20所述的半导体器件，其特征在于，所述半导体器件进一步包括在形成所述第二导电层之前在所述第一导电层和所述第一绝缘层上形成的种晶层。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108831870A (zh) * 2014-09-15 2018-11-16 台湾积体电路制造股份有限公司 具有ubm的封装件和形成方法
US10700026B2 (en) 2014-09-15 2020-06-30 Taiwan Semiconductor Manufacturing Company, Ltd. Package with UBM and methods of forming

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9543262B1 (en) * 2009-08-18 2017-01-10 Cypress Semiconductor Corporation Self aligned bump passivation
US8653542B2 (en) * 2011-01-13 2014-02-18 Tsmc Solid State Lighting Ltd. Micro-interconnects for light-emitting diodes
TWI490994B (zh) * 2012-09-03 2015-07-01 矽品精密工業股份有限公司 半導體封裝件中之連接結構
US9496195B2 (en) 2012-10-02 2016-11-15 STATS ChipPAC Pte. Ltd. Semiconductor device and method of depositing encapsulant along sides and surface edge of semiconductor die in embedded WLCSP
US9620413B2 (en) 2012-10-02 2017-04-11 STATS ChipPAC Pte. Ltd. Semiconductor device and method of using a standardized carrier in semiconductor packaging
US9704824B2 (en) 2013-01-03 2017-07-11 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming embedded wafer level chip scale packages
US9721862B2 (en) 2013-01-03 2017-08-01 STATS ChipPAC Pte. Ltd. Semiconductor device and method of using a standardized carrier to form embedded wafer level chip scale packages
US9478498B2 (en) * 2013-08-05 2016-10-25 Taiwan Semiconductor Manufacturing Company, Ltd. Through package via (TPV)
CN103658899B (zh) * 2013-12-04 2016-04-13 哈尔滨工业大学深圳研究生院 一种单一取向Cu6Sn5金属间化合物微互连焊点结构的制备及应用方法
US9704769B2 (en) 2014-02-27 2017-07-11 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming encapsulated wafer level chip scale package (EWLCSP)
US9466659B2 (en) * 2014-07-09 2016-10-11 Globalfoundries Inc. Fabrication of multilayer circuit elements
TWI585870B (zh) * 2015-05-20 2017-06-01 精材科技股份有限公司 晶片封裝體及其製造方法
KR20210086198A (ko) * 2019-12-31 2021-07-08 삼성전자주식회사 반도체 패키지
KR20220029232A (ko) 2020-09-01 2022-03-08 삼성전자주식회사 반도체 패키지 및 이를 포함하는 반도체 장치

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5894170A (en) * 1996-08-29 1999-04-13 Nec Corporation Wiring layer in semiconductor device
US6191489B1 (en) * 1999-02-19 2001-02-20 Micronas Gmbh Micromechanical layer stack arrangement particularly for flip chip or similar connections
US20030111731A1 (en) * 2001-12-13 2003-06-19 Nec Electronics Corporation Semiconductor device and method for producing the same
US20070184578A1 (en) * 2006-02-07 2007-08-09 Yaojian Lin Solder bump confinement system for an integrated circuit package

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5444022A (en) * 1993-12-29 1995-08-22 Intel Corporation Method of fabricating an interconnection structure for an integrated circuit
JP3842548B2 (ja) * 2000-12-12 2006-11-08 富士通株式会社 半導体装置の製造方法及び半導体装置
US6596619B1 (en) * 2002-05-17 2003-07-22 Taiwan Semiconductor Manufacturing Company Method for fabricating an under bump metallization structure
TW546805B (en) * 2002-07-18 2003-08-11 Advanced Semiconductor Eng Bumping process
DE10238816B4 (de) * 2002-08-23 2008-01-10 Qimonda Ag Verfahren zur Herstellung von Anschlussbereichen einer integrierten Schaltung und integrierte Schaltung mit Anschlussbereichen
TW578217B (en) * 2002-10-25 2004-03-01 Advanced Semiconductor Eng Under-bump-metallurgy layer
US6878633B2 (en) * 2002-12-23 2005-04-12 Freescale Semiconductor, Inc. Flip-chip structure and method for high quality inductors and transformers
US7043830B2 (en) * 2003-02-20 2006-05-16 Micron Technology, Inc. Method of forming conductive bumps
CN1284207C (zh) * 2003-06-03 2006-11-08 香港科技大学 一种用于半导体封装的焊球的制备方法
US7144759B1 (en) * 2004-04-02 2006-12-05 Celerity Research Pte. Ltd. Technology partitioning for advanced flip-chip packaging
TWI251284B (en) * 2004-11-12 2006-03-11 Advanced Semiconductor Eng Redistribution layer and circuit structure thereof
US20070029669A1 (en) * 2005-08-05 2007-02-08 Frank Stepniak Integrated circuit with low-stress under-bump metallurgy

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5894170A (en) * 1996-08-29 1999-04-13 Nec Corporation Wiring layer in semiconductor device
US6191489B1 (en) * 1999-02-19 2001-02-20 Micronas Gmbh Micromechanical layer stack arrangement particularly for flip chip or similar connections
US20030111731A1 (en) * 2001-12-13 2003-06-19 Nec Electronics Corporation Semiconductor device and method for producing the same
US20070184578A1 (en) * 2006-02-07 2007-08-09 Yaojian Lin Solder bump confinement system for an integrated circuit package

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108831870A (zh) * 2014-09-15 2018-11-16 台湾积体电路制造股份有限公司 具有ubm的封装件和形成方法
US10700026B2 (en) 2014-09-15 2020-06-30 Taiwan Semiconductor Manufacturing Company, Ltd. Package with UBM and methods of forming
US11164832B2 (en) 2014-09-15 2021-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package with UBM and methods of forming

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