TWI518811B - 半導體裝置及以多層凸塊底層金屬形成凸塊結構於凸塊形成區周圍之方法 - Google Patents

半導體裝置及以多層凸塊底層金屬形成凸塊結構於凸塊形成區周圍之方法 Download PDF

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TWI518811B
TWI518811B TW099135409A TW99135409A TWI518811B TW I518811 B TWI518811 B TW I518811B TW 099135409 A TW099135409 A TW 099135409A TW 99135409 A TW99135409 A TW 99135409A TW I518811 B TWI518811 B TW I518811B
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conductor layer
layer
forming
bump
over
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TW099135409A
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TW201125052A (en
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林耀劍
陳康
方建敏
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史達晶片有限公司
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Description

半導體裝置及以多層凸塊底層金屬形成凸塊結構於凸塊形成區周圍之方法
本發明大體上和半導體裝置有關，且更明確地說，和半導體裝置及在凸塊形成區周圍形成凸塊結構於一具有多層凸塊底層金屬之半導體晶圓上方之方法有關。
在現代的電子產品中經常會發現半導體裝置。半導體裝置會有不同數量與密度的電組件。離散式半導體裝置通常含有一種類型的電組件，舉例來說，發光二極體(Light Emitting Diode，LED)、小訊號電晶體、電阻器、電容器、電感器以及功率金屬氧化物半導體場效電晶體(Metal Oxide Semiconductor Field Effect Transistor，MOSFET)。積體式半導體裝置通常含有數百個至數百萬個電組件。積體式半導體裝置的範例包含微控制器、微處理器、電荷耦合裝置(Charged-Coupled Device，CCD)、太陽能電池以及數位微鏡裝置(Digital Micro-mirror Device，DMD)。
半導體裝置會實施各式各樣的功能，例如，高速計算、傳送與接收電磁訊號、控制電子裝置、將太陽光轉換成電能以及產生電視顯示器的視覺投影。在娛樂領域、通訊領域、電力轉換領域、網路領域、電腦領域以及消費性產品領域中皆會發現半導體裝置。在軍事應用、航空、自動車、工業控制器以及辦公室設備中同樣會發現半導體裝置。
半導體裝置會利用半導體材料的電氣特性。半導體材料的原子結構會使得可藉由施加電場或基礎電流或是經由摻雜處理來操縱其導電性。摻雜會將雜質引入至該半導體材料之中，以便操縱及控制該半導體裝置的傳導性。
一半導體裝置會含有主動式電氣結構與被動式電氣結構。主動式結構(其包含雙極電晶體與場效電晶體)會控制電流的流動。藉由改變摻雜程度以及施加電場或基礎電流，該電晶體便會提高或限制電流的流動。被動式結構(其包含電阻器、電容器以及電感器)會創造用以實施各式各樣電氣功能所需要的電壓和電流之間的關係。該等被動式結構與主動式結構會被電連接以形成讓該半導體裝置實施高速計算及其它實用功能的電路。
半導體裝置通常會使用兩種複雜的製程來製造，也就是，前端製造以及後端製造，每一者皆可能涉及數百道步驟。前端製造涉及在一半導體晶圓的表面上形成複數個晶粒。每一個晶粒通常相同並且含有藉由電連接主動式組件和被動式組件而形成的電路。後端製造涉及從已完成的晶圓中切割個別的晶粒並且封裝該晶粒，用以提供結構性支撐及環境隔離。
半導體製造的其中一個目標便係生產較小的半導體裝置。較小的裝置通常會消耗較少電力，具有較高效能，並且能夠更有效地生產。此外，較小的半導體裝置還具有較小的覆蓋面積，這係較小的末端產品所需要的。藉由改善前端製程可以達成較小的晶粒尺寸，從而導致具有較小以及較高密度之主動式組件和被動式組件的晶粒。後端製程可以藉由改善電互連材料及封裝材料而導致具有較小覆蓋面積的半導體裝置封裝。
圖1所示的係一被形成在半導體晶圓10上方的一習知凸塊結構，該半導體晶圓含有一基礎基板材料，例如，矽、鍺、砷化鎵、磷化銦或是碳化矽，用以達到結構性支撐的目的。複數個半導體晶粒會被形成在半導體晶圓10之上。每一個半導體晶粒皆具有一含有類比電路或數位電路的主動表面12，該等類比電路或數位電路會被施行為被形成在該晶粒裡面的主動式裝置、被動式裝置、導體層以及介電層，並且會根據該晶粒的電氣設計與功能來進行電互連。多個金屬互連觸墊14會被形成在主動表面12的上方。金屬觸墊14會被電連接至主動表面12上的電路系統。一鈍化層16會被形成在主動表面12與金屬觸墊14的上方。一部分的鈍化層16會藉由蝕刻製程被移除，以便露出金屬觸墊14。一導電層18會被形成在金屬觸墊14與鈍化層16的上方。導體層18的操作如同一重新分配層(RDL)，用以延伸金屬觸墊14的水平互連。一鈍化層20會被形成在導體層18與鈍化層16的上方。一部分的鈍化層20會藉由蝕刻製程被移除，以便露出導體層18。多個凸塊22會被形成在鈍化層20之已移除部分中的導體層18的上方。
凸塊22與重新分配層18之間的接觸介面很容易遭到剔除或失效，尤其是在製造可靠度測試期間。鈍化層20的用意在於保持凸塊22與重新分配層18之間的接觸介面的密封效果。然而，倘若鈍化層20脫離凸塊22的話，濕氣便會經由該鈍化材料與凸塊之間的間隔而滲入並且導致凸塊22與重新分配層18之間的接觸介面周圍發生氧化。該氧化會弱化該接觸介面。該裝置會因後端可靠度檢測而被剔除，或者該裝置可能會在使用現場失效。
本發明需要降低半導體裝置上凸塊結構的失效。據此，於其中一實施例中，本發明係一種製造半導體裝置的方法，其包括下面步驟：提供一基板；在該基板的上方形成一第一導體層；在該基板與第一導體層的上方形成一第一絕緣層；移除該第一絕緣層的一部分，以便露出該第一導體層；在該第一導體層與第一絕緣層的上方形成一第二導體層；以及在該第二導體層上方的一凸塊形成區周圍形成一凸塊底層金屬層。該第二導體層會裸露在該凸塊形成區之中。該方法還進一步包含下面步驟：在該凸塊底層金屬層與第二導體層的上方形成一第二絕緣層；移除該凸塊形成區上方的一部分第二絕緣層及一部分凸塊底層金屬層；以及在該凸塊形成區中該第二導體層的上方形成一凸塊。該凸塊會接觸該凸塊底層金屬層，以便密封該凸塊與第二導體層之間的接觸介面。
於另一實施例中，本發明係一種製造半導體裝置的方法，其包括下面步驟：提供一基板；在該基板的上方形成一第一導體層；在該基板的上方形成一第一絕緣層；在該第一導體層與第一絕緣層的上方形成一第二導體層；以及在該第二導體層上方的一互連形成區周圍形成一多層金屬圖樣。該第二導體層會裸露在該互連形成區之中。該方法還進一步包含下面步驟：在該互連形成區外面的該多層金屬圖樣與第二導體層的上方形成一第二絕緣層；以及在該互連形成區中該第二導體層的上方形成一互連結構。
於另一實施例中，本發明係一種製造半導體裝置的方法，其包括下面步驟：提供一基板；在該基板的上方形成一第一導體層；在該第一導體層上方的一互連形成區周圍形成一多層金屬圖樣；在該互連形成區外面的該多層金屬圖樣與第一導體層的上方形成一第一絕緣層；以及在該互連形成區中該第一導體層的上方形成一互連。
於另一實施例中，本發明係一種半導體裝置，其包括一半導體晶粒以及被形成在該半導體晶粒上方的第一導體層。一第一絕緣層會被形成在該半導體晶粒的上方。一第二導體層會被形成在該第一導體層與第一絕緣層的上方。一多層金屬圖樣會被形成在該第二導體層上方的一互連形成區周圍。一第二絕緣層會被形成在該凸塊形成區外面的該多層金屬圖樣與第二導體層的上方。一互連結構會被形成在該互連形成區中的該第二導體層的上方。
下面的說明書中會參考圖式於一或多個實施例中來說明本發明，於該等圖式中，相同的符號代表相同或雷同的元件。雖然本文會以達成本發明目的的最佳模式來說明本發明；不過，熟習本技術的人士便會明白，本發明希望涵蓋受到下面揭示內容及圖式支持的隨附申請專利範圍及它們的等效範圍所定義的本發明的精神與範疇內可能併入的替代例、修正例以及等效例。
半導體裝置通常會使用兩種複雜的製程來製造：前端製造和後端製造。前端製造涉及在一半導體晶圓的表面上形成複數個晶粒。該晶圓上的每一個晶粒皆含有主動式電組件和被動式電組件，它們會被電連接而形成功能性電路。主動式電組件(例如電晶體與二極體)能夠控制電流的流動。被動式電組件(例如電容器、電感器、電阻器以及變壓器)會創造用以實施電路功能所需要的電壓和電流之間的關係。
被動式組件和主動式組件會藉由一連串的製程步驟被形成在該半導體晶圓的表面上方，該等製程步驟包含：摻雜、沉積、光微影術、蝕刻以及平坦化。摻雜會藉由下面的技術將雜質引入至半導體材料之中，例如：離子植入或是熱擴散。摻雜製程會修正主動式裝置中半導體材料的導電性，將該半導體材料轉換成絕緣體、導體，或是響應於電場或基礎電流來動態改變半導體材料傳導性。電晶體含有不同類型和不同摻雜程度的多個區域，它們會在必要時被排列成用以在施加一電場或基礎電流時讓該電晶體會提高或限制電流的流動。
主動式組件和被動式組件係由具有不同電氣特性的多層材料構成。該等層能夠藉由各式各樣的沉積技術來形成，其部分取決於要被沉積的材料的類型。舉例來說，薄膜沉積可能包含：化學氣相沉積(Chemical Vapor Deposition，CVD)製程、物理氣相沉積(Physical Vapor Deposition，PVD)製程、電解質電鍍製程以及無電極電鍍製程。每一層通常都會被圖樣化，以便形成主動式組件的一部分、被動式組件的一部分或是組件之間的電連接線的一部分。
該等層能夠利用光微影術來圖樣化，其涉及在要被圖樣化的層的上方沉積光敏材料，舉例來說，光阻。一圖樣會利用光從一光罩處被轉印至該光阻。該光阻圖樣中受到光作用的部分會利用溶劑移除，從而露出下方層之中要被圖樣化的部分。該光阻中的剩餘部分會被移除，從而留下一已圖樣化層。或者，某些類型的材料會利用無電極電鍍以及電解質電鍍之類的技術，藉由將該材料直接沉積至先前沉積及/或蝕刻製程所形成的區域或空隙(void)之中而被圖樣化。
在一既有圖樣的上方沉積一薄膜材料可能會擴大下方圖樣並且產生一不均勻平坦的表面。生產較小且更密集封裝的主動式組件和被動式組件需要用到均勻平坦的表面。平坦化作用可用來從晶圓的表面處移除材料，並且產生均勻平坦的表面。平坦化作用涉及利用一研磨墊來研磨晶圓的表面。有磨蝕作用的材料以及腐蝕性的化學藥劑會在研磨期間被加到晶圓的表面。化學藥劑的磨蝕性作用及腐蝕性作用所組成的組合式機械作用會移除任何不規律的拓樸形狀，從而產生均勻平坦的表面。
後端製造係指將已完成的晶圓裁切或切割成個別晶粒，並且接著封裝該晶粒，以達結構性支撐及環境隔離的效果。為切割晶粒，晶圓會沿著該晶圓中被稱為切割道(saw street)或切割線(scribe)的非功能性區域形成刻痕並且折斷。該晶圓會利用雷射裁切工具或鋸片來進行切割。經過切割之後，個別晶粒便會被鑲嵌至包含接針或接觸觸墊的封裝基板，以便和其它系統組件進行互連。被形成在該半導體晶粒上方的接觸觸墊接著會被連接至該封裝裡面的接觸觸墊。該等電連接線可利用焊料凸塊、短柱凸塊、導電膏或是焊線來製成。一囊封劑或是其它模造材料會被沉積在該封裝的上方，用以提供物理性支撐和電隔離。接著，該已完成的封裝便會被插入一電氣系統之中並且讓其它系統組件可取用該半導體裝置的功能。
圖2圖解一電子裝置50，其具有一晶片載體基板或是印刷電路板(Printed Circuit Board，PCB)52，在其表面上鑲嵌著複數個半導體封裝。電子裝置50可能具有某一類型的半導體封裝或是多種類型的半導體封裝，端視應用而定。為達解釋目的，圖2中顯示不同類型的半導體封裝。
電子裝置50可能係一單機型系統，其會使用該等半導體封裝來實施一或多項電氣功能。或者，電子裝置50亦可能係一較大型系統中的一子組件。舉例來說，電子裝置50可能係一圖形卡、一網路介面卡或是能夠被插入在一電腦之中的其它訊號處理卡。該半導體封裝可能包含：微處理器、記憶體、特定應用積體電路(Application Specific Integrated Circuits，ASIC)、邏輯電路、類比電路、射頻電路、離散式裝置或是其它半導體晶粒或電組件。
在圖2中，印刷電路板52提供一通用基板，用以結構性支撐及電互連被鑲嵌在該印刷電路板之上的半導體封裝。多條導體訊號線路54會利用下面製程被形成在印刷電路板52的一表面上方或是多層裡面：蒸發製程、電解質電鍍製程、無電極電鍍製程、網印製程或是其它合宜的金屬沉積製程。訊號線路54會在該等半導體封裝、被鑲嵌的組件以及其它外部系統組件中的每一者之間提供電通訊。線路54還會提供連接至每一個該等半導體封裝的電力連接線及接地連接線。
於某些實施例中，一半導體裝置會有兩個封裝層。第一層封裝係一種用於以機械方式及電氣方式將該半導體晶粒附接至一中間載板的技術。第二層封裝則涉及以機械方式及電氣方式將該中間載板附接至該印刷電路板。於其它實施例中，一半導體裝置可能僅有該第一層封裝，其中，該晶粒會以機械方式及電氣方式直接被鑲嵌至該印刷電路板。
為達解釋目的，圖中在印刷電路板52之上顯示數種類型的第一層封裝，其包含焊線封裝56以及覆晶58。除此之外，圖中還顯示被鑲嵌在印刷電路板52之上的數種類型第二層封裝，其包含：球柵陣列(Ball Grid Array，BGA)60；凸塊晶片載板(Bump Chip Carrier，BCC)62；雙直列封裝(Dual In-line Package，DIP)64；平台格柵陣列(Land Grid Array，LGA)66；多晶片模組(Multi-Chip Module，MCM)68；方形扁平無導線封裝(Quad Flat Non-leaded package，QFN)70；以及方形扁平封裝72。端視系統需求而定，被配置成具有第一層封裝樣式和第二層封裝樣式之任何組合以及其它電子組件的各種半導體封裝的任何組合皆能夠被連接至印刷電路板52。於某些實施例中，電子裝置50包含單一附接半導體封裝；而其它實施例則要求多個互連封裝。藉由在單一基板上方組合一或多個半導體封裝，製造商便能夠將事先製成的組件併入電子裝置和系統之中。因為該等半導體封裝包含精密的功能，所以，電子裝置能夠使用較便宜的組件及有效率的製程來製造。所產生的裝置比較不可能失效而且製造價格較低廉，從而會降低消費者的成本。
圖3a至3c所示的係示範性半導體封裝。圖3a所示的係被鑲嵌在印刷電路板52之上的雙直列封裝64的進一步細節。半導體晶粒74包含一含有類比電路或數位電路的主動區，該等類比電路或數位電路會被施行為被形成在該晶粒裡面的主動式裝置、被動式裝置、導體層以及介電層，並且會根據該晶粒的電氣設計來進行電互連。舉例來說，該電路可能包含被形成在半導體晶粒74之主動區裡面的一或多個電晶體、二極體、電感器、電容器、電阻器以及其它電路元件。接觸觸墊76係由一或多層的導體材料(例如鋁(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)或是銀(Ag))製成，並且會被電連接至形成在半導體晶粒74裡面的電路元件。在雙直列封裝64的組裝期間，半導體晶粒74會利用一金-矽共熔合金層或是膠黏材料(例如熱環氧樹脂)被黏著至一中間載板78。封裝主體包含一絕緣封裝材料，例如聚合物或是陶瓷。導體導線80以及焊線82會在半導體晶粒74與印刷電路板52之間提供電互連。囊封劑84會被沉積在該封裝的上方，藉由防止濕氣和粒子進入該封裝並污染晶粒74或焊線82而達到環境保護的目的。
圖3b所示的係被鑲嵌在印刷電路板52之上的凸塊晶片載板62的進一步細節。半導體晶粒88會利用底層填充材料或環氧樹脂膠黏材料92被鑲嵌在載板90的上方。焊線94會在接觸觸墊96與98之間提供第一層封裝互連。模造化合物或囊封劑100會被沉積在半導體晶粒88和焊線94的上方，用以為該裝置提供物理性支撐以及電隔離效果。多個接觸觸墊102會利用合宜的金屬沉積製程(例如電解質電鍍或無電極電鍍)被形成在印刷電路板52的一表面上方用以防止氧化。接觸觸墊102會被電連接至印刷電路板52中的一或多條導體訊號線路54。多個凸塊104會被形成在凸塊晶片載板62的接觸觸墊98和印刷電路板52的接觸觸墊102之間。
在圖3c中，半導體晶粒58會利用一覆晶樣式的第一層封裝以面朝下的方式被鑲嵌至中間載板106。半導體晶粒58的主動區108含有類比電路或數位電路，該等類比電路或數位電路會被施行為根據該晶粒的電氣設計所形成的主動式裝置、被動式裝置、導體層以及介電層。舉例來說，該電路可能包含被形成在主動區108裡面的一或多個電晶體、二極體、電感器、電容器、電阻器以及其它電路元件。半導體晶粒58會經由多個凸塊110以電氣方式及機械方式被連接至載板106。
球柵陣列60會利用多個凸塊112，以球柵陣列樣式的第二層封裝被電氣性及機械性連接至印刷電路板52。半導體晶粒58會經由凸塊110、訊號線114以及凸塊112被電連接至印刷電路板52中的導體訊號線路54。一模造化合物或囊封劑116會被沉積在半導體晶粒58和載板106的上方，用以為該裝置提供物理性支撐以及電隔離效果。該覆晶半導體裝置會提供一條從半導體晶粒58上的主動式裝置至印刷電路板52上的傳導軌的短電傳導路徑，以便縮短訊號傳播距離、降低電容、並且改善整體電路效能。於另一實施例中，該半導體晶粒58會利用覆晶樣式的第一層封裝以機械方式及電氣方式直接被連接至印刷電路板52，而沒有中間載板106。
圖4a至4h所示的係，配合圖2及3a至3c，用以在一凸塊形成區周圍形成一具有雙層凸塊底層金屬之凸塊結構的製程。圖4a所示的係一半導體晶圓120，其含有一基礎基板材料，例如，矽、鍺、砷化鎵、磷化銦或是碳化矽，用以達到結構性支撐的目的。複數個半導體晶粒122會被形成在半導體晶圓120上，藉由如上面所述的切割道124來分離。每一個半導體晶粒或組件122都具有一主動表面126，該主動表面126含有類比電路或數位電路，該等類比電路或數位電路會被施行為被形成在該晶粒裡面的主動式裝置、被動式裝置、導體層以及介電層，並且會根據該晶粒的電氣設計與功能來進行電互連。舉例來說，該電路可能包含被形成在主動表面126裡面的一或多個電晶體、二極體以及其它電路元件，用以施行類比電路或數位電路，例如，數位訊號處理器(Digital Signal Processor，DSP)、特定應用積體電路、記憶體或是其它訊號處理電路。半導體晶粒122可能還含有用於射頻訊號處理的整合被動元件(IPD)，例如，電感器、電容器以及電阻器。
在圖4b中，一導電層130a與130b會使用圖樣化與沉積製程(例如物理氣相沉積、化學氣相沉積、濺鍍、電解質電鍍以及無電極電鍍)被形成在半導體晶圓120的主動表面126的上方。導體層130a與130b可能係由下面所製成的一或多層：Al、Cu、Sn、Ni、Au、Ag或是其它合宜的導電材料。導體層130a與130b為金屬互連觸墊，它們會被電連接至主動表面126上的電路系統。
一絕緣層或鈍化層132會利用下面方法被形成在基板120的主動表面126與導體層130的上方：物理氣相沉積、化學氣相沉積、印刷、旋塗、噴塗、燒結或是熱氧化。該絕緣層132可能係由下面所製成的一或多層：二氧化矽(SiO2)；氮化矽(Si3N4)；氮氧化矽(SiON)；五氧化二鉭(Ta2O5)；三氧化二鋁(Al2O3)；光敏高分子介電質(舉例來說，聚亞醯胺、WPR、聚苯并噁唑纖維(PBO)、環苯丁烯(BCB))；或是具有雷同絕緣特性及結構性特性的其它材料。一部分的絕緣層132會藉由蝕刻製程被移除，用以露出導體層130a與130b。
在圖4c中，一晶種層134會使用圖樣化與沉積製程(例如電解質電鍍以及無電極電鍍)被形成在導體層130與絕緣層132的上方。晶種層134可能係Ti/Cu、TiW/Cu、Ta/Cu、Cr/Cu、Ni、Ti(TiW、Cr、Al)/NiV(Cr、TaN)/Cu、釩化鎳(NiV)、Au或是Al。
一光阻層136會被沉積在晶種層134之上。導體層130a與130b及晶種層134上方的一部分光阻層136會藉由曝光被圖樣化並且藉由蝕刻製程被移除。一導電層138會利用沉積製程(例如，物理氣相沉積、化學氣相沉積、濺鍍、電解質電鍍以及無電極電鍍)被形成在光阻層136之已移除部分中的晶種層134的上方。導體層138可能係由下面所製成的一或多層：Al、Cu、Sn、Ni、Au、Ag或是其它合宜的導電材料。導體層138的操作如同一重新分配層，用以延伸互連觸墊130a與130b的互連能力。導體層138在互連觸墊130a與130b之間可能為連續，或者在該等互連觸墊之間可能為電隔離。於其中一實施例中，導體層138會在已圖樣化的光阻層136中選擇性地鍍銅。晶種層134的操作如同Cu導體層138的屏障層與濕潤層。
在圖4d中，光阻層136會被移除。一導電層140會在被指定於稍後用於形成互連凸塊的凸塊或互連形成區144周圍被形成在導體層138的上方。一導電層142會被形成在導體層140的上方。導體層140與142可能係利用圖樣化與沉積製程(例如，物理氣相沉積、化學氣相沉積、濺鍍、電解質電鍍以及無電極電鍍)所沉積的一或多層合宜的導電材料。導體層140與142會構成一多層金屬圖樣或凸塊底層金屬，其包含一屏障層與膠黏層。於其中一實施例中，導體層140係含有Ni、NiV、TiW、銅化鉻(CrCu)、鉑(Pt)或是鈀(Pd)的屏障層。導體層142係含有Al、鈦(Ti)、鉻(Cr)或是氮化鈦(TiN)的膠黏層。凸塊底層金屬140至142提供一低電阻性的互連，並且阻止Cu或焊料擴散至主動表面126之中。
圖4e所示的係具有凸塊形成區144的凸塊底層金屬140至142的俯視圖。於其中一實施例中，凸塊底層金屬140至142會被圖樣化與沉積為一完全包圍凸塊形成區144的環體，或是一以凸塊形成區144的中心的封閉結構。因此，凸塊形成區144係凸塊底層金屬140至142的中心。或者，凸塊底層金屬140至142會被沉積在區域144的上方並且接著會從區域144處被蝕刻，用以形成該環體或封閉結構。於其它實施例中，凸塊底層金屬140至142則會被形成部分包圍區域144。
在圖4f中，一絕緣層或鈍化層146會利用下面方法被形成在導體層138及凸塊底層金屬140至142及基板120的上方：物理氣相沉積、化學氣相沉積、印刷、旋塗、噴塗、燒結或是熱氧化。該絕緣層146可能係由下面所製成的一或多層：SiO2；Si3N4；SiON；Ta2O5；Al2O3；或是具有雷同絕緣特性及結構性特性的其它材料。一部分的絕緣層146會藉由蝕刻製程被移除，用以露出區域144中的導體層138以及位於區域144周圍周圍的一部分凸塊底層金屬140至142。圖4g所示的係覆蓋一部分凸塊底層金屬140至142的絕緣層146的俯視圖。凸塊底層金屬140至142中未被絕緣層146覆蓋的部分會構成該完全包圍凸塊形成區144的環體。接著，該絕緣層146便會被固化。
在圖4h中，一導電凸塊材料會利用蒸發製程、電解質電鍍製程、無電極電鍍製程、丸滴製程或是網印製程被沉積在區域144的上方。該凸塊材料可能係Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料以及它們的組合，其會有一非必要的助熔溶液。舉例來說，該凸塊材料可能是Sn/Pb共熔合金、高鉛焊料或是無鉛焊料。該凸塊材料會利用合宜的附著或焊接製程被焊接至導體層138以及凸塊底層金屬140至142。於其中一實施例中，該凸塊材料會藉由將該材料加熱至其熔點以上而被回焊，用以形成球狀的丸體或凸塊148。於某些應用中，凸塊148會被二次回焊，以便改善和導體層138以及凸塊底層金屬140至142的電接觸效果。該等凸塊也能夠被壓縮焊接至導體層138以及凸塊底層金屬140至142。凸塊148代表能夠被形成在導體層138以及凸塊底層金屬140至142上方的其中一種類型的互連結構。該互連結構亦能夠使用短柱凸塊、微凸塊、導體柱或是其它電互連。
主動表面126上的電路系統會經由互連觸墊130a與130b、重新分配層138以及凸塊148被電連接至外部裝置。凸塊148會接觸凸塊底層金屬140至142；不過，絕緣層146則可能會或可能不會接觸凸塊148。於任何情況中，因為凸塊148周圍的凸塊底層金屬140至142的封閉結構會保持密封凸塊148與導體層138之間的接觸介面的關係，絕緣層146的脫層便不再會是可靠度問題。導體層140為屏障層，用以防止Cu擴散；而導體層142則係膠黏層，用以形成凸塊148的濕氣防堵密封層。凸塊底層金屬140至142會藉由防止濕氣滲入凸塊148與導體層138之間的接觸介面而提高可靠度，濕氣滲入可能會造成該接觸介面的氧化與弱化。凸塊底層金屬140至142會降低裝置的檢測剔除或是失效。
於另一實施例中，接續上面圖4c所述的結構，光阻層136會被移除並且一導電層150會在被指定於稍後用於形成互連凸塊的凸塊或互連形成區144周圍被形成在導體層138的上方，如圖5中所示。一導電層152會被形成在導體層150的上方，而且一導電層154會被形成在導體層152的上方。導體層150至154可能係利用圖樣化與沉積製程(例如，物理氣相沉積、化學氣相沉積、濺鍍、電解質電鍍以及無電極電鍍)所沉積的一或多層合宜的導電材料。導體層150至154會構成一多層金屬圖樣或凸塊底層金屬，其包含一介於膠黏層之間的屏障層。於其中一實施例中，導體層154係一含有Al、Ti、Cr、TiN或是TiW的膠黏層；導體層152係一含有Ni、NiV、TiW、CrCu、NiV、Pt或是Pd的屏障層；以及導體層152係一含有Al、Ti、Cr、TiN或是TiW的膠黏層。凸塊底層金屬150至154的俯視圖和圖4e雷同。凸塊底層金屬150至154提供一低電阻性的互連，並且阻止Cu或焊料擴散至主動表面126之中。
一絕緣層或鈍化層156會利用下面方法被形成在導體層138及凸塊底層金屬150至154的上方：物理氣相沉積、化學氣相沉積、印刷、旋塗、噴塗、燒結或是熱氧化。該絕緣層156可能係由下面所製成的一或多層：SiO2；Si3N4；SiON；Ta2O5；Al2O3；或是具有雷同絕緣特性及結構性特性的其它材料。一部分的絕緣層156會藉由蝕刻製程被移除，用以露出區域144中的導體層138以及一部分的凸塊底層金屬150至154。絕緣層156會覆蓋一部分的凸塊底層金屬150至154。凸塊底層金屬150至154中未被絕緣層156覆蓋的部分會構成該完全包圍凸塊形成區144的環體。接著，該絕緣層156便會被固化。
一導電凸塊材料會利用蒸發製程、電解質電鍍製程、無電極電鍍製程、丸滴製程或是網印製程被沉積在區域144的上方。該凸塊材料可能係Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料以及它們的組合，其會有一非必要的助熔溶液。舉例來說，該凸塊材料可能是Sn/Pb共熔合金、高鉛焊料或是無鉛焊料。該凸塊材料會利用合宜的附著或焊接製程被焊接至導體層138以及凸塊底層金屬150至154。於其中一實施例中，該凸塊材料會藉由將該材料加熱至其熔點以上而被回焊，用以形成球狀的丸體或凸塊158。於某些應用中，凸塊158會被二次回焊，以便改善和導體層138以及凸塊底層金屬150至154的電接觸效果。該等凸塊也能夠被壓縮焊接至導體層138以及凸塊底層金屬150至154。凸塊158代表能夠被形成在導體層138以及凸塊底層金屬150至154上方的其中一種類型的互連結構。該互連結構亦能夠使用短柱凸塊、微凸塊、導體柱或是其它電互連。
主動表面126上的電路系統會經由互連觸墊130a與130b、重新分配層138以及凸塊158被電連接至外部裝置。凸塊158會接觸凸塊底層金屬150至154；不過，絕緣層156則可能會或可能不會接觸凸塊158。於任何情況中，因為凸塊158周圍的凸塊底層金屬150至154的封閉結構會保持密封凸塊158與導體層138之間的接觸介面的關係，絕緣層156的脫層便不再會是可靠度問題。凸塊底層金屬154至154會藉由防止濕氣滲入凸塊158與導體層138之間的接觸介面而提高可靠度，濕氣滲入可能會造成該接觸介面的氧化與弱化。凸塊底層金屬150至154會降低裝置的檢測剔除或是失效。
於另一實施例中，接續上面圖4c所述的結構，光阻層136會被移除並且一導電層160會在被指定於稍後用於形成互連凸塊的中央凸塊形成區144周圍被形成在導體層138的上方，如圖6中所示。一導電層162會被形成在導體層160的上方。導體層160至162可能係利用圖樣化與沉積製程(例如，物理氣相沉積、化學氣相沉積、濺鍍、電解質電鍍以及無電極電鍍)所沉積的一或多層合宜的導電材料。導體層160至162會構成一多層金屬圖樣或凸塊底層金屬，其包含一介於膠黏層之間的屏障層。於其中一實施例中，導體層162係一含有Al、Ti、Cr、TiN或是TiW的膠黏層；而導體層160則係一含有Ni、NiV、TiW、CrCu、NiV、Pt或是Pd的屏障層。凸塊底層金屬150至154的俯視圖和圖4e雷同。凸塊底層金屬160至162提供一低電阻性的互連，並且阻止Cu或焊料擴散至主動表面126之中。
於其中一實施例中，凸塊底層金屬160至162會被圖樣化與沉積為一完全包圍凸塊形成區144的環體，或是一以凸塊形成區144的中心的封閉結構。因此，凸塊形成區144係凸塊底層金屬160至162的中心。或者，凸塊底層金屬160至162會被沉積在區域144的上方並且接著會從區域144處被蝕刻，用以形成該環體或封閉結構。
一絕緣層或鈍化層164會利用下面方法被形成在導體層138及凸塊底層金屬160至162及基板120的上方：物理氣相沉積、化學氣相沉積、印刷、旋塗、噴塗、燒結或是熱氧化。該絕緣層164可能係由下面所製成的一或多層：SiO2；Si3N4；SiON；Ta2O5；Al2O3；或是具有雷同絕緣特性及結構性特性的其它材料。一部分的絕緣層164會藉由蝕刻製程被移除，用以露出區域144中的導體層138以及一部分的凸塊底層金屬160至162。接著，該絕緣層164便會被固化。
一導電凸塊材料會利用蒸發製程、電解質電鍍製程、無電極電鍍製程、丸滴製程或是網印製程被沉積在區域144的上方。該凸塊材料可能係Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料以及它們的組合，其會有一非必要的助熔溶液。舉例來說，該凸塊材料可能是Sn/Pb共熔合金、高鉛焊料或是無鉛焊料。該凸塊材料會利用合宜的附著或焊接製程被焊接至導體層138以及凸塊底層金屬160至162。於其中一實施例中，該凸塊材料會藉由將該材料加熱至其熔點以上而被回焊，用以形成球狀的丸體或凸塊166。於某些應用中，凸塊166會被二次回焊，以便改善和導體層138以及凸塊底層金屬160至162的電接觸效果。該等凸塊也能夠被壓縮焊接至導體層138以及凸塊底層金屬160至162。凸塊166代表能夠被形成在導體層138以及凸塊底層金屬160至162上方的其中一種類型的互連結構。該互連結構亦能夠使用短柱凸塊、微凸塊、導體柱或是其它電互連。
主動表面126上的電路系統會經由互連觸墊130a與130b、重新分配層138以及凸塊166被電連接至外部裝置。絕緣層164會接觸凸塊166。然而，因為凸塊底層金屬160至162會保持密封凸塊166與導體層138之間的接觸介面的關係，絕緣層164的脫層仍然不再會是可靠度問題。凸塊底層金屬160至162會藉由防止濕氣滲入凸塊166與導體層138之間的接觸介面而提高可靠度，濕氣滲入可能會造成該接觸介面的氧化與弱化。凸塊底層金屬160至162會降低裝置的檢測剔除或是失效。
於另一實施例中，接續上面圖4c所述的結構，光阻層136會被移除並且一導電層170會被形成在導體層138的上方，如圖7中所示。導體層170會覆蓋導體層138，除了中央凸塊形成區144(其會被指定於稍後用於形成互連凸塊)之外。一導電層172會被形成在導體層170的上方。導體層170與172可能係利用圖樣化與沉積製程(例如，物理氣相沉積、化學氣相沉積、濺鍍、電解質電鍍以及無電極電鍍)所沉積的一或多層合宜的導電材料。導體層170至172會構成一多層金屬圖樣或凸塊底層金屬，其包含一屏障層與膠黏層。於其中一實施例中，導體層170係含有Ni、NiV、TiW、CrCu、NiV、Pt或是Pd的屏障層。導體層172係含有Al、Ti、Cr、TiN或是TiW的膠黏層。凸塊底層金屬170至172提供一低電阻性的互連，並且阻止Cu或焊料擴散至主動表面126之中。
一絕緣層或鈍化層174會利用下面方法被形成在導體層138及凸塊底層金屬170至172及基板120的上方：物理氣相沉積、化學氣相沉積、印刷、旋塗、噴塗、燒結或是熱氧化。該絕緣層174可能係由下面所製成的一或多層：SiO2；Si3N4；SiON；Ta2O5；Al2O3；或是具有雷同絕緣特性及結構性特性的其它材料。一部分的絕緣層174會藉由蝕刻製程被移除，用以露出區域144中的導體層138以及一部分的凸塊底層金屬170至172。也就是，該絕緣層174會覆蓋一部分的凸塊底層金屬170至172。凸塊底層金屬170至172中未被絕緣層174覆蓋的部分會構成該完全包圍凸塊形成區144的環體。接著，該絕緣層174便會被固化。
一導電凸塊材料會利用蒸發製程、電解質電鍍製程、無電極電鍍製程、丸滴製程或是網印製程被沉積在區域144的上方。該凸塊材料可能係Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料以及它們的組合，其會有一非必要的助熔溶液。舉例來說，該凸塊材料可能是Sn/Pb共熔合金、高鉛焊料或是無鉛焊料。該凸塊材料會利用合宜的附著或焊接製程被焊接至導體層138以及凸塊底層金屬170至172。於其中一實施例中，該凸塊材料會藉由將該材料加熱至其熔點以上而被回焊，用以形成球狀的丸體或凸塊176。於某些應用中，凸塊176會被二次回焊，以便改善和導體層138以及凸塊底層金屬170至172的電接觸效果。該等凸塊也能夠被壓縮焊接至導體層138以及凸塊底層金屬170至172。凸塊176代表能夠被形成在導體層138以及凸塊底層金屬170至172上方的其中一種類型的互連結構。該互連結構亦能夠使用短柱凸塊、微凸塊、導體柱或是其它電互連。
主動表面126上的電路系統會經由互連觸墊130a與130b、重新分配層138以及凸塊176被電連接至外部裝置。凸塊176會接觸凸塊底層金屬170至172；不過，絕緣層174則可能會或可能不會接觸凸塊176。於任何情況中，因為凸塊底層金屬170至172會保持密封凸塊176與導體層138之間的接觸介面的關係，絕緣層174的脫層便不再會是可靠度問題。凸塊底層金屬170至172會藉由防止濕氣滲入凸塊176與導體層138之間的接觸介面而提高可靠度，濕氣滲入可能會造成該接觸介面的氧化與弱化。凸塊底層金屬170至172會降低裝置的檢測剔除或是失效。
雖然本文已經詳細解釋過本發明的一或多個實施例；不過，熟練的技術人士便會明白，可以對該些實施例進行修正與改變，其並不會脫離後面申請專利範圍中所提出的本發明的範疇。
10．．．半導體晶圓
12．．．主動表面
14．．．金屬觸墊
16．．．鈍化層
18．．．導電層
20．．．鈍化層
22．．．凸塊
50．．．電子裝置
52．．．印刷電路板(PCB)
54．．．線路
56．．．焊線封裝
58．．．半導體晶粒
60．．．球柵陣列(BGA)
62．．．凸塊晶片載板(BCC)
64．．．雙直列封裝(DIP)
66．．．平台格柵陣列(LGA)
68．．．多晶片模組(MCM)
70．．．方形扁平無導線封裝(QFN)
72．．．方形扁平封裝
74．．．半導體晶粒
76．．．接觸觸墊
78．．．中間載板
80．．．導體導線
82．．．焊線
84．．．囊封劑
88．．．半導體晶粒
90．．．載板
92．．．膠黏材料
94．．．焊線
96．．．接觸觸墊
98．．．接觸觸墊
100．．．模造化合物或囊封劑
102．．．接觸觸墊
104．．．凸塊
106．．．中間載板
108．．．主動區
110．．．凸塊
112．．．凸塊
114．．．訊號線
116．．．模造化合物或囊封劑
120．．．半導體晶圓
122．．．半導體晶粒
124．．．切割道
126．．．主動表面
130．．．導體層
130a-b．．．導電層
132．．．絕緣層或鈍化層
134．．．晶種層
136．．．光阻層
138．．．導電層
140．．．導電層
142．．．導電層
144．．．凸塊或互連形成區
146．．．絕緣層或鈍化層
148．．．球狀的丸體或凸塊
150．．．導體層
152．．．導電層
154．．．導電層
156．．．絕緣層或鈍化層
158．．．球狀的丸體或凸塊
160．．．導電層
162．．．導電層
164．．．絕緣層或鈍化層
166．．．球狀的丸體或凸塊
170．．．導電層
172．．．導電層
174．．．絕緣層或鈍化層
176．．．球狀的丸體或凸塊
圖1所示的係一被形成在半導體晶圓上方的習知凸塊結構；
圖2所示的係一印刷電路板，在其表面上鑲嵌著不同類型的封裝；
圖3a至3c所示的係被鑲嵌至該印刷電路板的代表性半導體封裝的進一步細節；
圖4a至4h所示的係用以在一凸塊形成區周圍形成一具有雙層凸塊底層金屬之凸塊結構的製程；
圖5所示的係被形成在該凸塊之基底周圍之具有三層凸塊底層金屬的另一凸塊結構；
圖6所示的係鈍化層會接觸該凸塊的另一凸塊結構；以及
圖7所示的係被形成在該凸塊之基底周圍之具有連續雙層凸塊底層金屬的另一凸塊結構。
120．．．半導體晶圓
126．．．主動表面
130a-b．．．導電層
132．．．絕緣層或鈍化層
134．．．晶種層
138．．．導電層
150．．．導體層
152．．．導電層
154．．．導電層
156．．．絕緣層或鈍化層
158．．．球狀的丸體或凸塊

Claims (15)

  1. 一種製造半導體裝置的方法，其包括：提供一基板；在該基板的上方形成一第一導體層；在該基板的上方形成一第一絕緣層；在該第一導體層與第一絕緣層的上方形成一第二導體層；在該第二導體層上方的一互連形成區周圍形成一多層金屬圖樣，而該第二導體層的一部份會裸露在該互連形成區之中；在形成該多層金屬圖樣之後，在該多層金屬圖樣的上方形成一第二絕緣層並且接觸在該互連形成區中的第二導體層的被裸露部分；以及在該互連形成區中的該被裸露部分的該第二導體層的上方形成一互連結構。
  2. 如申請專利範圍第1項的方法，其中，形成該多層金屬圖樣包含：在該第二導體層的上方形成一第三導體層；以及在該第三導體層的上方形成一第四導體層。
  3. 如申請專利範圍第2項的方法，其中，該第四導體層包含一選擇自由下面所組成之群組中的材料：鋁、鈦、鉻、氮化鈦以及鎢化鈦。
  4. 如申請專利範圍第1項的方法，其中，形成該多層金屬圖樣包含： 在該第二導體層的上方形成一第三導體層；在該第三導體層的上方形成一第四導體層；以及在該第四導體層的上方形成一第五導體層。
  5. 如申請專利範圍第1項的方法，其進一步包含在形成該第二導體層之前先在該第一導體層與第一絕緣層的上方形成一晶種層。
  6. 一種製造半導體裝置的方法，其包括：提供一基板；在該基板的上方形成一第一導體層；在該第一導體層上方的一互連形成區周圍形成一多層金屬圖樣，其裸露該第一導體層的一部分；在該多層金屬圖樣的上方以及在該多層金屬圖樣外面的第一導體層的上方形成一第一絕緣層；以及在該互連形成區中該第一導體層的被裸露部分的上方形成一互連結構。
  7. 如申請專利範圍第6項的方法，其進一步包含：在形成該第一導體層之前先在該基板的上方形成一第二導體層；在該基板的上方形成一第二絕緣層；以及在該第二導體層與第二絕緣層的上方形成一晶種層。
  8. 如申請專利範圍第6項的方法，其中，形成該多層金屬圖樣包含：在該第一導體層的上方形成一第二導體層；以及在該第二導體層的上方形成一第三導體層並且接觸該 互連結構。
  9. 如申請專利範圍第6項的方法，其中，形成該多層金屬圖樣包含：在該第一導體層的上方形成一第二導體層；在該第二導體層的上方形成一第三導體層；以及在該第三導體層的上方形成一第四導體層並且接觸該互連結構。
  10. 如申請專利範圍第6項的方法，進一步包含形成該多層金屬圖樣覆蓋該互連形成區外面的第一導體層。
  11. 一種半導體裝置，其包括：一半導體晶粒；一第一導體層，其會被形成在該半導體晶粒的上方；一第一絕緣層，其會被形成在該半導體晶粒的上方；一第二導體層，其會被形成在該第一導體層與第一絕緣層的上方；一多層金屬圖樣，其會被形成在該第二導體層上方的一互連形成區周圍，其裸露該第二導體層的一部分；以及一第二絕緣層，其會被形成在該多層金屬圖樣的上方以及在該多層金屬圖樣外面的該第二導體層的上方。
  12. 如申請專利範圍第11項的裝置，其中該多層金屬圖樣包含：一被形成在該第二導體層上方的第三導體層；以及一被形成在該第三導體層上方的第四導體層。
  13. 如申請專利範圍第11項的裝置，其中該多層金屬圖 樣包含：一被形成在該第二導體層上方的第三導體層；一被形成在該第三導體層上方的第四導體層；以及一被形成在該第四導體層上方的第五導體層。
  14. 如申請專利範圍第11項的裝置，其進一步包含一互連結構被形成在該互連形成區中之該第二導體層的上方。
  15. 如申請專利範圍第11項的裝置，其中，該多層金屬圖樣會覆蓋該互連形成區外面的該第二導體層。
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