CN102347272B - 形成rdl的方法和半导体器件 - Google Patents

形成rdl的方法和半导体器件 Download PDF

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CN102347272B
CN102347272B CN201110264951.6A CN201110264951A CN102347272B CN 102347272 B CN102347272 B CN 102347272B CN 201110264951 A CN201110264951 A CN 201110264951A CN 102347272 B CN102347272 B CN 102347272B
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conductive layer
width
axle
insulating barrier
semiconductor element
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CN102347272A (zh
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林耀剑
冯霞
方建敏
陈康
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Stats Chippac Pte Ltd
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Stats Chippac Pte Ltd
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Abstract

本发明涉及一种形成RDL的方法和半导体器件。一种半导体器件具有半导体管芯和形成在该半导体管芯表面上的第一导电层。第一绝缘层形成在半导体管芯的该表面上。第二绝缘层形成在第一绝缘层和第一导电层上。开口形成在第一绝缘层上的第二绝缘层中。第二导电层形成在第一导电层和第二绝缘层上的开口中。沿着第一轴，第二导电层具有小于第一导电层的宽度的宽度。沿着与第一轴垂直的第二轴，第二导电层具有大于第一导电层的宽度的宽度。第三绝缘层形成在第二导电层和第一绝缘层上。

Description

形成RDL的方法和半导体器件
国内优先权声明
本申请要求于2010年7月26日提交的第61/367807号临时申请的优先权，且依照35U.S.C.§120要求上述申请的优先权。
技术领域
本发明一般涉及半导体器件，并且更具体地涉及在接触焊盘上形成重分布层(RDL)的方法和半导体器件，其中RDL沿第一轴比接触焊盘宽，而沿与第一轴垂直的第二轴比接触焊盘窄。
背景技术
常常在现代电子产品中发现半导体器件。半导体器件在电部件的数目和密度方面变化。分立的半导体器件一般包含一种类型的电部件，例如发光二极管(LED)、小信号晶体管、电阻器、电容器、电感器、功率金属氧化物半导体场效应晶体管(MOSFET)。集成半导体器件典型地包含几百个到数以百万的电部件。集成半导体器件的示例包括微控制器、微处理器、电荷耦合器件(CCD)、太阳能电池以及数字微镜器件(DMD)。
半导体器件执行各种的功能，诸如信号处理、高速计算、发射和接收电磁信号、控制电子器件、将太阳光转变为电力以及产生用于电视显示的视觉投影。在娱乐、通信、功率转换、网络、计算机以及消费产品的领域中发现半导体器件。还在军事应用、航空、汽车、工业控制器和办公设备中发现半导体器件。
半导体器件利用半导体材料的电属性。半导体材料的原子结构允许通过施加电场或基电流(base current)或通过掺杂工艺而操纵其导电性。掺杂向半导体材料引入杂质以操纵和控制半导体器件的导电性。
半导体器件包含有源和无源电结构。包括双极和场效应晶体管的有源结构控制电流的流动。通过改变掺杂水平和施加电场或基电流，晶体管要么促进要么限制电流的流动。包括电阻器、电容器和电感器的无源结构创建为执行各种电功能所必须的电压和电流之间的关系。无源和有源结构电连接以形成电路，这使得半导体器件能够执行高速计算和其他有用功能。
半导体器件一般使用两个复杂的制造工艺来制造，即，前端制造和和后端制造，每一个可能涉及成百个步骤。前端制造涉及在半导体晶片的表面上形成多个管芯。每个半导体管芯典型地是相同的且包含通过电连接有源和无源部件而形成的电路。后端制造涉及从完成的晶片分割(singulate)各个半导体管芯且封装管芯以提供结构支撑和环境隔离。此处使用的术语“半导体管芯”指代该词的单数和复数形式二者，且相应地，可指代单半导体器件和多半导体器件二者。
半导体制造的一个目的是生产较小的半导体器件。较小的器件典型地消耗较少的功率、具有较高的性能且可以更高效地生产。另外，较小的半导体器件具有较小的占位面积，这对于较小的终端产品而言是希望的。较小的半导体管芯尺寸可以通过前端工艺中的改进来获得，该前端工艺中的改进导致半导体管芯具有较小、较高密度的有源和无源部件。后端工艺可以通过电互联和封装材料中的改进而导致具有较小占位面积的半导体器件封装。
图1a示例了一种传统的半导体器件10，其具有以扇入或扇出晶片级芯片规模封装(WLCSP)的半导体管芯或晶片12。半导体管芯12具有有源表面14和形成在该有源表面上的接触焊盘16。绝缘或钝化层18以晶片级形成在有源表面14和接触焊盘16上。绝缘层18的一部分通过蚀刻工艺被去除以露出接触焊盘16。绝缘或钝化层20以晶片级形成在绝缘层18和该露出的接触焊盘16上。绝缘层20的一部分通过蚀刻工艺被去除以露出接触焊盘16。典型地，在绝缘层18中的开口为20微米(μm)以获得与接触焊盘16的良好的电特性。导电层22形成在该露出的接触焊盘16和绝缘层20上。导电层22操作为电连接至接触焊盘16的再分布层(RDL)。导电层22延伸越过在绝缘层20中的开口以横向地再分布该电互连至接触焊盘16。绝缘或钝化层24形成在绝缘层20和导电层22上。绝缘层24的一部分通过蚀刻工艺去除以露出用于电互连的导电层22。
图1b示出半导体器件10的平面示图，沿着图1a的1b-1b线截取，关注接触焊盘区域26。在绝缘层20中露出接触焊盘16以用于导电层22的沉积的开口28的宽度以及在导电层22和接触焊盘16之间的接触表面的宽度W16-22为20μm。邻近的导电层22之间的宽度为10μm。20μm的开口宽度W16-22是用于导电层22和接触焊盘16之间的良好电接触所必须的。但是，由于绝缘层20在接触焊盘16上的、完全地围绕该接触焊盘的重叠，要求接触焊盘16的一定的宽度和节距以维持导电层22和接触焊盘16之间的互连表面面积。在一实施例中，接触焊盘16的宽度是45μm，且接触焊盘的节距是50μm。对于绝缘层20在导电层16上、围绕开口28的10μm的重叠，宽度W20-20为20+10+10＝40μm。由于为了良好的接触特性所需要的宽度W20-20(开口28的宽度加上重叠宽度)，50μm的接触焊盘节距成为工艺限制。如果开口28的宽度W16-22进一步减小，那么导电层22和接触焊盘16之间的接触特性变弱。
发明内容
需要在接触焊盘上形成具有高对准容差的RDL。因此，在一个实施例中，本发明是一种制作半导体器件的方法，包括步骤：提供半导体管芯；在该半导体管芯表面上形成第一导电层；在该半导体管芯的该表面上形成第一绝缘层；在第一绝缘层和第一导电层上形成第二绝缘层；以及在第一导电层上的第二绝缘层中形成开口。该开口在第一导电层的第一和第二相对边缘上延伸超过该第一导电层，而第二绝缘层相对于第一导电层的第三和第四相对边缘覆盖该第一导电层，该第一导电层的第三和第四相对边缘与第一导电层的第一和第二相对边缘垂直。该方面进一步包括在第一和第二绝缘层上以及在第二绝缘层中的开口内的第一导电层部分上形成第二导电层；以及在第二导电层和第一和第二绝缘层上形成第三绝缘层。
在另一个实施例中，本发明是一种制作半导体器件的方法，包括步骤：提供半导体管芯；在该半导体管芯表面上形成第一导电层；在第一导电层和该半导体管芯表面上形成第一绝缘层；形成沿着第一轴具有小于第一导电层的宽度的宽度的第二导电层，以及在第二导电层和第一绝缘层上形成第二绝缘层。该第二导电层沿着与第一轴垂直的第二轴具有大于第一导电层的宽度的宽度。
在另一个实施例中，本发明是一种制作半导体器件的方法，包括步骤：提供半导体管芯；在该半导体管芯表面上形成第一导电层；在该半导体管芯的该表面上形成第一绝缘层；以及在第一导电层上形成第二导电层，沿着第一轴，第二导电层宽于第一导电层，并且沿着与第一轴垂直的第二轴，第二导电层窄于第一导电层。
在另一个实施例中，本发明是一种半导体器件，包括：半导体管芯以及形成在该半导体管芯表面上的第一导电层。第一绝缘层形成在该半导体管芯的该表面上。第二导电层形成在第一导电层上，沿着第一轴，第二导电层宽于第一导电层，并且在与第一轴垂直的第二轴上，第二导电层窄于第一导电层。第二绝缘层形成在第二导电层和第一绝缘层上。
附图说明
图1a-1b示出安装至基板、具有电桥缺陷的传统半导体管芯；
图2说明印刷电路板(PCB)，具有各种类型的安装至其表面的封装体；
图3a-3c说明该代表性的安装至该PCB的半导体封装的进一步的细节；
图4a-4o说明在接触焊盘上形成具有高的对准容限的RDL的工艺；
图5a-5c说明具有形成在该接触焊盘上的RDL的半导体管芯；以及
图6a-6f示出形成在接触焊盘上的RDL的替换实施例。
具体实施方式
在下面的描述中，参考图以一个或更多实施例描述本发明，在这些图中相似的标号代表相同或类似的元件。尽管就用于实现本发明目的的最佳模式描述本发明，但是本领域技术人员应当理解，其旨在覆盖可以包括在如下面的公开和图支持的所附权利要求及其等价物限定的本发明的精神和范围内的备选、修改和等价物。
半导体器件一般使用两个复杂制造工艺来制造：前端制造和后端制造。前端制造涉及在半导体晶片的表面上形成多个管芯。晶片上的每个管芯包含有源和无源电部件，它们电连接以形成功能电路。诸如晶体管和二极管的有源电部件具有控制电流流动的能力。诸如电容器、电感器、电阻器和变压器的无源电部件创建为执行电路功能所必须的电压和电流之间的关系。
通过包括掺杂、沉积、光刻、蚀刻和平坦化的一系列工艺步骤在半导体晶片的表面上形成无源和有源部件。掺杂通过诸如离子注入或热扩散的技术将杂质引入到半导体材料中。掺杂工艺修改了有源器件中半导体材料的导电性，将半导体材料转变为绝缘体、导体，或者响应于电场或基电流而动态地改变半导体材料的导电性。晶体管包含不同类型和掺杂程度的区域，其按照需要被布置为使得当施加电场或基电流时晶体管能够促进或限制电流的流动。
通过具有不同电属性的材料层形成有源和无源部件。层可以通过部分由被沉积的材料类型确定的各种沉积技术来形成。例如，薄膜沉积可能涉及化学汽相沉积(CVD)、物理汽相沉积(PVD)、电解电镀和化学电镀工艺。每一层一般被图案化以形成有源部件、无源部件或部件之间的电连接的部分。
可以使用光刻对层进行图案化，光刻涉及例如光刻胶的光敏材料在待被图案化的层上的沉积。使用光，图案从光掩模转移到光刻胶。在一实施例中，受光影响的光刻胶图案的部分使用溶剂来去除，露出待被图案化的底层的部分。在另一实施例中，未受光影响的光刻胶图案的部分即负性光刻胶使用溶剂来去除，露出待被图案化的底层的部分。去除该光刻胶的剩下部分，留下图案化的层。备选地，一些类型的材料通过使用诸如化学电镀和电解电镀这样的技术来直接向原先沉积/蚀刻工艺形成的区域或空位沉积材料而被图案化。
在现有图案上沉积材料的薄膜可以放大底层图案且形成不均匀的平坦表面。需要均匀的平坦表面来生产更小且更致密堆叠的有源和无源部件。平坦化可以用于从晶片的表面去除材料且产生均匀的平坦表面。平坦化涉及使用抛光垫对晶片的表面进行抛光。研磨材料和腐蚀化学物在抛光期间被添加到晶片的表面。组合的研磨物的机械行为和化学物的腐蚀行为去除任何不规则拓扑，导致均匀的平坦表面。
后端制造指将完成的晶片切割或分割为各个管芯且然后封装管芯以用于结构支撑和环境隔离。为了分割半导体管芯，晶片沿着称为划片线或划线的晶片的非功能区域被划片且折断。使用激光切割工具或锯条来分割晶片。在分割之后，各个半导体管芯被安装到封装基板，该封装基板包括引脚或接触焊盘以用于与其他系统部件互连。在半导体管芯上形成的接触焊盘然后连接到封装内的接触焊盘。电连接可以使用焊料凸块、柱形凸块、导电胶或引线接合来制成。密封剂或其他成型材料沉积在封装上以提供物理支撑和电隔离。完成的封装然后被插入到电系统中且使得半导体器件的功能性对于其他系统部件可用。
图2说明具有芯片载体基板或印刷电路板(PCB)52的电子器件50，该芯片载体基板或印刷电路板(PCB)52具有安装在其表面上的多个半导体封装。取决于应用，电子器件50可以具有一种类型的半导体封装或多种类型的半导体封装。为了说明性目的，在图2中示出了不同类型的半导体封装。
电子器件50可以是使用半导体封装以执行一个或更多电功能的独立系统。备选地，电子器件50可以是较大系统的子部件。例如，电子器件50可以是蜂窝电话、个人数字助理(PDA)、数码摄像机(DVC)或其他电子通信器件的一部分。备选地，电子器件50可以是图形卡、网络接口卡或可以被插入到计算机中的其他信号处理卡。半导体封装可以包括微处理器、存储器、专用集成电路(ASIC)、逻辑电路、模拟电路、RF电路、分立器件或其他半导体管芯或电部件。微型化和重量减小对于这些产品被市场接受是至关重要的。半导体器件之间的距离必须减小以实现更高的密度。
在图2中，PCB 52提供用于安装到PCB上的半导体封装的结构支撑和电互连的一般性基板。使用蒸发、电解电镀、化学电镀、丝网印刷或者其他合适的金属沉积工艺，导电信号迹线54在PCB 52的表面上或其层内形成。信号迹线54提供半导体封装、安装的部件以及其他外部系统部件中的每一个之间的电通信。迹线54还向半导体封装中的每一个提供功率和接地连接。
在一些实施例中，半导体器件具有两个封装级别。第一级封装是用于机械和电附连半导体管芯到中间载体的技术。第二级封装涉及机械和电附连中间载体到PCB。在其他实施例中，半导体器件可以仅具有第一级封装，其中管芯被直接机械和电地安装到PCB。
为了说明目的，在PCB 52上示出包括接合引线封装56和倒装芯片58的若干类型的第一级封装。另外，示出在PCB 52上安装的若干类型的第二级封装，包括球栅阵列(BGA)60、凸块芯片载体(BCC)62、双列直插式封装(DIP)64、岸面栅格阵列(LGA)66、多芯片模块(MCM)68、四方扁平无引脚封装(QFN)70以及方形扁平封装72。取决于系统需求，使用第一和第二级封装类型的任何组合配置的半导体封装以及其他电子部件的任何组合可以连接到PCB 52。在一些实施例中，电子器件50包括单一附连的半导体封装，而其他实施例需要多个互连封装。通过在单个基板上组合一个或更多半导体封装，制造商可以将预制部件结合到电子器件和系统中。因为半导体封装包括复杂的功能性，可以使用较廉价的部件和流水线制造工艺来制造电子器件。所得到的器件较不倾向于发生故障且对于制造而言较不昂贵，导致针对消费者的较少的成本。
图3a-3c示出示例性半导体封装。图3a说明安装在PCB 52上的DIP64的进一步细节。半导体管芯74包括有源区域，该有源区域包含实现为根据管芯的电设计而在管芯内形成且电互连的有源器件、无源器件、导电层以及电介质层的模拟或数字电路。例如，电路可以包括一个或更多晶体管、二极管、电感器、电容器、电阻器以及在半导体管芯74的有源区域内形成的其他电路元件。接触焊盘76是诸如铝(Al)、铜(Cu)、锡(Sn)、镍(Ni)、金(Au)或银(Ag)的一层或多层导电材料，且电连接到半导体管芯74内形成的电路元件。在DIP 64的组装期间，半导体管芯74使用金-硅共熔层或者诸如热环氧物或环氧树脂的粘合剂材料而安装到中间载体78。封装体包括诸如聚合物或陶瓷的绝缘封装材料。导线80和接合引线82提供半导体管芯74和PCB 52之间的电互连。密封剂84沉积在封装上，以通过防止湿气和颗粒进入封装且污染半导体管芯74或接合引线82而进行环境保护。
图3b说明安装在PCB 52上的BCC 62的进一步细节。半导体管芯88使用底层填料或者环氧树脂粘合剂材料92而安装在载体90上。接合引线94提供接触焊盘96和98之间的第一级封装互连。模塑料或密封剂100沉积在半导体管芯88和接合引线94上，从而为器件提供物理支撑和电隔离。接触焊盘102使用诸如电解电镀或化学电镀之类的合适的金属沉积工艺而在PCB 52的表面上形成以防止氧化。接触焊盘102电连接到PCB 52中的一个或更多导电信号迹线54。凸块104在BCC 62的接触焊盘98和PCB 52的接触焊盘102之间形成。
在图3c中，使用倒装芯片类型第一级封装将半导体管芯58面朝下地安装到中间载体106。半导体管芯58的有源区域108包含实现为根据管芯的电设计而形成的有源器件、无源器件、导电层以及电介质层的模拟或数字电路。例如，电路可以包括一个或更多晶体管、二极管、电感器、电容器、电阻器以及有源区域108内的其他电路元件。半导体管芯58通过凸块110电和机械连接到载体106。
使用利用凸块112的BGA类型第二级封装，BGA 60电且机械连接到PCB 52。半导体管芯58通过凸块110、信号线114和凸块112电连接到PCB 52中的导电迹线54。模塑料或密封剂116被沉积在半导体管芯58和载体106上以为器件提供物理支撑和电隔离。倒装芯片半导体器件提供从半导体管芯58上的有源器件到PCB 52上的导电迹线的短导电路径以便减小信号传播距离、降低电容且改善整体电路性能。在另一实施例中，半导体管芯58可以使用倒装芯片类型第一级封装来直接机械和电地连接到PCB 52而不使用中间载体106。
图4a-4o关于图2和3a-3c说明一种在接触焊盘上形成具有高的对准容限的RDL的工艺。图4a示出具有用于结构支撑的基底基板材料122的半导体晶片120，该基底基板材料诸如是硅、锗、砷化镓、磷化铟或者碳化硅。如上所述，在晶片120上形成通过非有源的、管芯间晶片区域或划片线126分离的多个半导体管芯或组件124。划片线126提供切割区域以将半导体晶片120分割为单个半导体管芯124。
图4b示出半导体晶片120的一部分的剖面图。每个半导体管芯124具有背面128和有源表面130，该有源表面包含实现为在管芯内形成的且根据管芯的电设计和功能而电互连的有源器件、无源器件、导电层以及电介质层的模拟或数字电路。例如，电路可以包括一个或更多个晶体管、二极管以及在有源表面130内形成的其他电路元件以实现诸如数字信号处理(DSP)、ASIC、存储器或其他信号处理电路之类的模拟电路或数字电路。半导体管芯124还可以包含诸如电感器、电容器和电阻器的集成无源器件(IPD)以用于RF信号处理。在一个实施例中，半导体管芯124是倒装芯片类型的管芯。
使用PVD、CVD、电解电镀、化学电镀工艺或其他合适的金属沉积工艺而在有源表面130上形成导电层132。导电层132可以是Al、Cu、Sn、Ni、Au、Ag或其他合适的导电材料中的一层或更多层。导电层132操作为电连接到有源表面130上的电路的接触焊盘。接触焊盘132可以距离半导体管芯124的边缘第一距离并排设置。备选地，接触焊盘132可在多排中偏移，以使第一排接触焊盘132以距离该管芯的边缘第一距离设置，且与第一排交替的第二排接触焊盘以距离该管芯边缘第二距离设置。导电层132可以是矩形、圆形、椭圆形或多边形。
在图4c中，使用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化而在有源表面130和导电层132上形成绝缘或钝化层134。绝缘层134包含二氧化硅(SiO2)、氮化硅(Si3N4)、氮氧化硅(SiON)、五氧化二钽(Ta2O5)、氧化铝(Al2O3)、苯并环丁烯(BCB)、聚酰亚胺(PI)、聚苯并噁唑(PBO)、合适的电介质材料或具有类似绝缘和结构属性的其他材料中的一层或更多层。利用通过光刻胶层(未示出)的蚀刻工艺去除绝缘层134的一部分以形成开口133并露出导电层132。在一个实施例中，绝缘层134中的开口133为八角形，如图4d所示。
图4d示出沿着方向轴135和与轴135垂直的方向轴136的导电层132和绝缘层134的平面图。图4e-4o是就在轴135方向沿着基板120的表面120a以及在轴136方向沿着表面120b截取的视图来描述的。
在图4d中，使用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化而在绝缘层134和露出的导电层132上形成绝缘或钝化层137。该绝缘层137包括SiO2、Si3N4、SiON、Ta2O5、Al2O3、BCB、PI、PBO、合适的电介质材料或其它具有类似的绝缘的和结构的属性的材料的一层或更多层。利用通过光刻胶层的蚀刻工艺去除绝缘层137的一部分以形成开口138并且相对于绝缘层137露出导电层132的一部分，如图4f中在轴135方向上沿表面120a所示。图4g示出了在轴136方向上沿表面120b的开口138。
在一实施例中，通过使得被辐射的DFR材料经受显影剂而去除绝缘层137的一部分，该显影剂选择性地溶解该DFR材料的未被辐射部分以在置于导电层132上的绝缘层137中形成图案化的开口138，同时使得该光刻胶材料被辐射部分保持完整。
备选地，如图4h中所示在轴136方向上沿着表面120b，在需要更精细互连尺寸的应用中，可以使用激光器139以激光直接烧蚀(LDA)去除部分绝缘层137来形成图案化的开口138。
图4i示出了绝缘层134的平面图，通过绝缘层137而形成图案化开口138以露出出部分导电层132。特别地，绝缘层137中的图案化开口138在轴136方向上延伸超过导体层132的相对的边缘132a和132b，而在与轴136的方向垂直的轴135方向上，绝缘层137则覆盖在导体层132的相对边缘132c和132d上。在轴135方向上图案化开口138的宽度小于导体层132的宽度，在轴136方向上图案化开口的宽度大于导体层132的宽度。
在图4j中，在轴135方向上沿着表面120a，利用图案化和诸如印刷、PVD、CVD、溅射、电解电镀和化学电镀的金属沉积工艺，在图案化开口138内在露出的导电层132上形成导电层142。图4k示出了在轴136方向上沿着表面120b，形成在图案化的开口内在露出的导电层132和绝缘层134和137上的导电层142。导电层142可以共性地施加以遵循绝缘层134和137以及导电层132的轮廓。导电层142用作电连接到导电层132的RDL。导电层142在平行于有源表面130的方向延伸，在轴136方向超过绝缘层137中的图案化开口138，从而横向重新分布电互连到导体层132。
在图41中，在轴135方向沿着表面120a，利用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化，在绝缘层137和导电层142上形成绝缘或钝化层144。图4m示出了在轴136方向沿着表面120b形成在绝缘层137和导电层142上的绝缘层144。绝缘层144包括SiO2、Si3N4、SiON、Ta2O5、Al2O3、BCB、PI、PBO、合适的电介质材料或其他具有类似绝缘和结构属性的材料的一层或多层。在轴136方向沿着表面120b，利用通过光刻胶层的蚀刻工艺去除部分绝缘层144以露出导电层132的占位面积(footprint)之外的部分导电层142，用于形成电互连。
在图4n中，使用蒸发、电解电镀、化学电镀、球滴或丝网印刷工艺，在轴136的方向上沿表面120b在露出的导电层142上沉积导电凸块材料。凸块材料可以是具有可选助焊剂溶液的Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及其组合。例如，凸块材料可以是共熔Sn/Pb、高铅焊料或无铅焊料。凸块材料使用合适的附连或接合工艺而接合到导电层142。在一个实施例中，凸块材料通过加热材料到其熔点之上而进行回流以形成凸块146。在一些应用中，凸块146被二次回流以改善与导电层142的电接触。凸块146还被压缩接合到导电层142。凸块下金属化(UBM)层可以形成在凸块146和导电层142之间。凸块146代表一种可形成在导电层142上的互连结构的类型。互连结构还可使用立柱凸块、微凸块或其它电互连。
图4n和图4o示出了利用锯条或激光切割工具148通过划片线126分割成各个半导体管芯124的晶片120。图5a示出在分割后在轴135方向沿着表面120a的半导体管芯124。图5b示出在分割后在轴136方向沿着表面120b的半导体管芯124。半导体管芯124通过导电层132和142电连接到凸块146。图案化的开口138使得部分导电层132相对于绝缘层137露出。导电层142形成在绝缘层134和137以及露出的导电层132上。由于绝缘层137在轴135方向覆盖导电层132，在轴135方向导电层142的宽度小于导电层132的宽度。在轴136方向导电层142延伸超过导电层132的相对的边缘132a-132b。由于在轴136方向绝缘层137没有覆盖导电层132，在导电层142的边缘142a和142b之间导电层142在整个导电层132上延伸。
图5c示出了放大的导电层132和142以及绝缘层134的平面图。在一个实施例中，导电层132的宽度W132为40μm，导电层132的节距W132-132为45μm。更一般的，导电层132的节距可以在30到50μm的范围内。在轴136方向，绝缘层137中的图案化开口138延伸超过导电层132的相对边缘132a和132b，而在与轴136方向垂直的轴135方向，绝缘层137覆盖导电层132的相对的边缘132c和132d。在轴136的方向，导电层142的宽度W142c大于导电层132的宽度W132e。在一个实施例中，导电层142的宽度W142c为70μm，导电层132的宽度W132e为40μm。导电层142覆盖绝缘层134，并延伸超过导电层132的边缘132a达W132a-142a和W132b-142b，即导电层132双侧覆盖区。也就是说，W132a-142a是导电层132的边缘132a和导电层142的边缘142a之间的导电层142的宽度，且W132b-142b是导电层132的边缘132b和导电层142的边缘14212之间的导电层142的宽度。在一个实施例中，W132a-142a和W132b-142b为10-20μm，例如15μm。
另外，在轴135方向导电层142的宽度W142d小于导电层132的宽度。在一个实施例中，导电层142的宽度W142d为10μm，导电层132的宽度W132f为40μm。W132c-142e是导电层132的边缘132c和导电层142的边缘142e之间的导电层132的宽度，且W132d-142f是导电层132的边缘132d和导电层142的边缘142f之间的导电层132的宽度。在一个实施例中，W132c-142e和W132d-142f为10-20μm，例如为15μm。为了良好的电特性例如低接触电阻，导电层132和导电层142之间的接触界面的宽度W132e至少为40μm。接触界面面积至少为40×10＝400μm2。更一般的，导电层132和导电层142之间的接触界面的宽度可以在20-40μm的范围内。相邻的导电层142之间的宽度W142-142至少为35μm。通过增加开口138的尺寸在双侧覆盖区使得导电层132相对于绝缘层137完全露出，对于导电层142获得高的对准容差，而不牺牲接触界面W132e×W142d。
图6a-6f示出了绝缘层137和导电层132和142的替换实施例。图案化的开口138的形状决定了导电层142的形状，包括矩形、椭圆形、圆角和多边形。图6a示出了用于图案化开口138和导电层142的、在轴136方向延长的椭圆形。图6b示出了用于图案化开口138和导电层142的、具有圆角的常规矩形形状。图6c示出了用于图案化开口138和导电层142的、在轴136方向延长的常规多边形形状。图6d示出了用于图案化开口138和导电层142的另一种在轴136方向延长的常规多边形形状。图6e示出了用于图案化开口138和导电层142的、在轴136方向具有延伸部的常规矩形形状。图6f示出了用于图案化开口138和导电层142的具有圆端部的常规矩形形状。
在每种情况下，在轴136方向绝缘层137中的图案化开口138都延伸超过导电层132的相对的边缘132a和132b，而在与轴136方向垂直的轴135方向，绝缘层137都覆盖导电层132的相对的边缘132c和132d。在轴136方向导电层142的宽度W142c大于导电层132的宽度W132e。在一个实施例中，导电层142的宽度W142c为70μm而导电层132的宽度W132e为40μm。导电层142覆盖绝缘层134并延伸超过导电层132的边缘132a达W132a-142a和W132b-142b，即导电层132的双侧覆盖区。也就是说，W132a-142a是导电层132的边缘132a和导电层142的边缘142a之间的导电层142的宽度，且W132b-142b是导电层132的边缘132b和导电层142的边缘142b之间的导电层142的宽度。在一个实施例中，W132a-142a和W132b-142b为10-20μm，例如15mu。
此外，在轴135方向导电层142的宽度小于导电层132的宽度。在一个实施例中，导电层142的宽度W142d为10μm，且导电层132的宽度W132f为40μm。W132c-142e是导电层132的边缘132c和导电层142的边缘142e之间的导电层132的宽度，且W132d-142f是导电层132的边缘132d和导电层142的边缘142f之间的导电层132的宽度。在一个实施例中，W132c-142e和W132d-142f为10-20μm，例如为15μm。为了良好的电特性例如低接触电阻，导电层132和导电层142之间的接触界面的宽度W132e至少为40μm。接触界面面积至少为40×10＝400μm2。更一般的，导电层132和导电层142之间的接触界面的宽度可以在20-40μm的范围内。相邻的导电层142之间的宽度至少为35μm。通过增加开口138的尺寸，在双侧覆盖区使得导电层132相对于绝缘层137完全露出，对于导电层142获得高的对准容差，而不牺牲接触界面W132e×W142d。
虽然详细地说明了本发明的一个或更多的实施例，本领域技术人员可理解，在不脱离下述权利要求所阐述的本发明的范围的情况下，可做出那些实施例的修正和调整。

Claims (13)

1.一种制作半导体器件的方法，包括：
提供半导体管芯；
在该半导体管芯的表面上形成第一导电层；
在第一导电层上形成包括第一开口的第一绝缘层；
在第一导电层和第一绝缘层上形成第二绝缘层；
在第二绝缘层中形成第二开口，该第二开口在第一导电层的第一和第二相对边缘上延伸，而第二绝缘层覆盖该第一导电层的第三和第四相对边缘，该第一导电层的第三和第四相对边缘与第一导电层的第一和第二相对边缘垂直；
在所述第二开口内形成与所述第一导电层接触的第二导电层，该第二导电层包括沿第一轴的小于第一导电层的宽度的宽度，以及沿与第一轴垂直的第二轴的大于第一导电层的宽度的宽度。
2.权利要求1的方法，其中：沿着第一轴，第一导电层的宽度比第二导电层的宽度大10-20μm。
3.权利要求1的方法，其中：第一导电层和第二导电层之间的接触界面的宽度在20-40μm范围内。
4.权利要求1的方法，其中：第一导电层的节距在30-50μm范围内。
5.一种制作半导体器件的方法，包括：
提供半导体管芯；
在该半导体管芯表面上形成第一导电层；
在该半导体管芯上形成第一绝缘层；
在第一绝缘层中形成开口，该开口沿第一轴比该第一导电层更宽并且沿与该第一轴垂直的第二轴比该第一导电层窄；以及
在第一导电层上的该开口内形成第二导电层，沿着第一轴，第二导电层宽于第一导电层，并且沿着与第一轴垂直的第二轴，第二导电层窄于第一导电层。
6.权利要求5的方法，进一步包括：
在形成第一绝缘层之前在半导体管芯的表面上形成第二绝缘层，以及
在第二导电层和第一绝缘层上形成第三绝缘层。
7.权利要求5的方法，其中：沿着第一轴，第二导电层的宽度比第一导电层的宽度大10-20μm。
8.权利要求5的方法，其中：沿着第二轴，第二导电层的宽度比第一导电层的宽度小10-20μm。
9.一种半导体器件，包括：
半导体管芯；
形成在该半导体管芯的表面上的第一导电层；
形成在该半导体管芯的该表面上的第一绝缘层；以及
在第一导电层上形成的第二导电层，沿着第一轴，第二导电层宽于第一导电层，并且沿与第一轴垂直的第二轴，第二导电层窄于第一导电层。
10.权利要求9的半导体器件，其中：沿着第一轴，第二导电层的宽度比第一导电层的宽度大10-20μm。
11.权利要求9的半导体器件，其中：沿着第二轴，第二导电层的宽度比第一导电层的宽度小10-20μm。
12.权利要求9的半导体器件，其中：第一导电层和第二导电层之间的接触界面的宽度在20-40μm的范围内。
13.权利要求9的半导体器件，其中：第一导电层的节距在30-50μm的范围内。
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