CN101989558A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
CN101989558A
CN101989558A CN2010102438900A CN201010243890A CN101989558A CN 101989558 A CN101989558 A CN 101989558A CN 2010102438900 A CN2010102438900 A CN 2010102438900A CN 201010243890 A CN201010243890 A CN 201010243890A CN 101989558 A CN101989558 A CN 101989558A
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semiconductor device
semiconductor element
semiconductor
substrate
tsv
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CN2010102438900A
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CN101989558B (zh
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R·A·帕盖拉
关协和
D·A·梅里洛
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Stats Chippac Pte Ltd
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Stats Chippac Pte Ltd
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Abstract

本发明涉及半导体器件及其制造方法。一种具有衬底的半导体器件，所述衬底具有通过衬底的第一表面和第二表面形成的空腔。通过第一半导体管芯形成导电TSV，所述第一半导体管芯被安装在所述空腔中。第一半导体管芯可以在所述空腔上延伸。密封剂被沉积在第一半导体管芯的第一表面和衬底上。从第一半导体管芯的第一表面除去所述密封剂的一部分以暴露所述导电TSV。第二半导体管芯被安装到第一半导体管芯的第一表面。第二半导体管芯电连接到所述导电TSV。在第一半导体管芯和第二半导体管芯之间设置插入物。第三半导体管芯被安装在第一半导体管芯的第二表面上。热沉被形成在第三半导体管芯的表面上。

Description

半导体器件及其制造方法
技术领域
本发明总体上涉及半导体器件，并且更具体地说涉及半导体器件和在衬底的空腔中安装具有TSV的半导体部件用于FI-POP的电互连的方法。
背景技术
在现代电子产品中通常会发现有半导体器件。半导体器件在电部件的数量和密度上有变化。分立的半导体器件一般包括一种电部件，例如发光二极管(LED)、小信号晶体管、电阻器、电容器、电感器、以及功率金属氧化物半导体场效应晶体管(MOSFET)。集成半导体器件通常包括数百到数百万的电部件。集成半导体器件的实例包括微控制器、微处理器、电荷耦合器件(CCD)、太阳能电池、以及数字微镜器件(DMD)。
半导体器件执行多种功能，例如高速计算、发射和接收电磁信号、控制电子器件、将日光转换成电、以及为电视显示器生成可视投影。在娱乐、通信、功率转换、网络、计算机、以及消费品领域中有半导体器件的存在。在军事应用、航空、汽车、工业控制器、以及办公设备中也有半导体器件的存在。
半导体器件利用半导体材料的电特性。半导体材料的原子结构允许通过施加电场或基极电流(base current)或者通过掺杂工艺来操纵(manipulated)它的导电性。掺杂把杂质引入半导体材料中以操纵和控制半导体器件的导电性。
半导体器件包括有源和无源电结构。有源结构(包括双极和场效应晶体管)控制电流的流动。通过改变掺杂水平并且施加电场或基极电流，晶体管促进或限制电流的流动。无源结构(包括电阻器、电容器、和电感器)产生执行多种电功能所必需的电压和电流之间的关系。无源和有源结构被电连接以形成电路，所述电路能够使半导体器件执行高速计算和其它有用的功能。
通常利用两个复杂的制造工艺来制造半导体器件，即前端制造和后端制造，每个可能包括数百个步骤。前端制造包括在半导体晶片的表面上形成多个管芯。每个管芯通常相同并且包括通过电连接有源和无源部件形成的电路。后端制造包括从已完成的晶片单体化(singulating)单个管芯并且封装管芯以提供结构支撑和环境隔离。
半导体制造的一个目标是制造更小的半导体器件。更小的半导体器件通常消耗更少功率、具有更高的性能、并且能够被更有效地制造。另外，更小的半导体器件具有更小的占地面积(footprint)，其对于更小的最终产品而言是期望的。通过改善导致产生具有更小、更高密度的有源和无源部件的管芯的前端工艺可以实现更小的管芯尺寸。通过改善电互连和封装材料，后端工艺可以产生具有更小占地面积的半导体器件封装。
在许多应用中，期望一个在另一个之上地堆叠多个半导体管芯以形成堆叠半导体封装。然而，堆叠半导体管芯也增加了半导体封装的总尺寸和厚度。例如，在包括三个或更多个堆叠管芯的封装中，所述封装需要几个衬底以便于在每一个半导体管芯之间形成电互连。在常规封装中，例如，当形成扇入型层叠封装(Fi-PoP)的封装时经常需要三个衬底以在顶部、中间、和底部管芯之间形成必要的连接。即使使用一个衬底，安装到衬底相对侧的管芯也会增加封装厚度和加长传播路径，这降低了电性能。
发明内容
在Fi-PoP布置中存在电互连堆叠的半导体管芯的需要。因此，在一个实施例中，本发明是包括以下步骤的制造半导体器件的方法：提供具有第一表面和第二表面的衬底，形成通过衬底的第一表面和第二表面的空腔，形成通过第一半导体管芯的通路，利用导电材料填充所述通路以形成导电通路，在所述空腔中安装第一半导体管芯，在第一半导体管芯的第一表面和衬底上沉积密封剂，从第一半导体管芯的第一表面除去密封剂的一部分以暴露所述导电通路，以及将第二半导体管芯安装到第一半导体管芯的第一表面。第二半导体管芯电连接到所述导电通路。所述方法进一步包括在与第一半导体管芯的第一表面相对的第一半导体管芯的第二表面上安装第三半导体管芯的步骤。
在另一个实施例中，本发明是包括以下步骤的制造半导体器件的方法：提供具有第一表面和第二表面的衬底，形成通过衬底的第一表面和第二表面的空腔，以及在所述空腔中安装第一半导体部件。所述第一半导体部件具有导电TSV。所述方法进一步包括以下步骤：在第一半导体部件的第一表面和衬底上沉积密封剂，从第一半导体部件的第一表面除去密封剂的一部分以暴露所述导电TSV，以及将第二半导体部件安装到第一半导体部件的第一表面。第二半导体部件电连接到所述导电TSV。
在另一个实施例中，本发明是包括以下步骤的制造半导体器件的方法：提供具有第一表面和第二表面的衬底，形成通过衬底的第一表面和第二表面的空腔，以及在所述空腔上安装第一半导体部件。所述第一半导体部件具有导电TSV。所述方法进一步包括以下步骤：在第一半导体部件的第一表面上安装第二半导体部件，在衬底和第二半导体部件上沉积密封剂，以及在与第一半导体部件的第一表面相对的第一半导体部件的第二表面上安装第三半导体部件。
在另一个实施例中，本发明是包括衬底的半导体器件，所述衬底具有通过衬底的第一表面和第二表面形成的空腔。第一半导体部件安装在所述空腔中。第一半导体部件具有导电TSV。第二半导体部件安装在第一半导体部件的第一表面上。在衬底和第二半导体部件上沉积密封剂。第三半导体部件安装在与第一半导体部件的第一表面相对的第一半导体部件的第二表面上。
附图说明
图1示出具有安装到其表面的不同类型的封装的PCB；
图2a-2c示出安装到所述PCB的典型半导体封装的更多细节；
图3a-3h示出利用被安装在衬底的空腔中的具有TSV的半导体管芯形成Fi-PoP；
图4示出通过衬底空腔中的TSV管芯互连的堆叠管芯；
图5示出利用设置在衬底空腔中的TSV插入物(interposer)互连的堆叠管芯；
图6示出利用衬底空腔中的嵌入式凸块(bump)和TSV互连的堆叠管芯；
图7示出利用被膜中芯片(wire-in-film)材料覆盖的结合线和TSV互连的堆叠管芯；
图8示出利用安装在衬底空腔上的TSV管芯互连的堆叠管芯；
图9示出利用延伸到衬底空腔之外的TSV管芯互连的堆叠管芯；
图10示出利用设置在衬底空腔外部的TSV管芯互连的堆叠管芯；以及
图11示出具有堆叠管芯和热沉的Fi-PoP。
具体实施方式
一般利用两个复杂的制造工艺制造半导体器件：前端制造和后端制造。前端制造包括在半导体晶片的表面上形成多个管芯。晶片上的每个管芯包括有源和无源电部件，所述有源和无源电部件被电连接以形成功能电路。有源电部件，例如晶体管和二极管，具有控制电流的流动的能力。无源电部件，例如电容器、电感器、电阻器、和变压器，产生执行电路功能所必需的电压和电流之间的关系。
通过包括掺杂、沉积、光刻、刻蚀、和平面化的一系列工艺步骤在半导体晶片的表面上形成无源和有源部件。掺杂通过例如离子注入或热扩散的技术将杂质引入到半导体材料中。所述掺杂工艺改变有源器件中的半导体材料的导电性，将半导体材料转变成绝缘体、导体，或响应于电场或基极电流动态改变半导体材料导电性。晶体管包括有变化的掺杂类型和程度的区域，所述区域根据需要被设置为使晶体管能够在施加电场或基极电流时促进或限制电流的流动。
通过具有不同电特性的材料的层形成有源和无源部件。所述层可以通过部分地由被沉积的材料的类型决定的多种沉积技术形成。例如，薄膜沉积可以包括化学汽相沉积(CVD)、物理汽相沉积(PVD)、电解电镀、以及无电电镀(electroless plating)工艺。每个层通常被图案化以形成有源部件、无源部件、或部件之间的电连接的各部分。
可以利用光刻图案化所述层，所述光刻包括在将被图案化的层上沉积光敏材料，例如光致抗蚀剂。利用光将图案从光掩模转移到光致抗蚀剂。利用溶剂将经受光的光致抗蚀剂图案部分除去，暴露将被图案化的下层的各部分。光致抗蚀剂的剩余物被除去，留下被图案化的层。可替换地，利用例如无电电镀或电解电镀的技术通过直接将材料沉积到通过先前的沉积/刻蚀工艺形成的区域或空隙中来图案化一些类型的材料。
在现有图案上沉积材料的薄膜可能会放大下面的图案并且引起不均匀的平面。需要均匀的平面来制造更小和更密集包装的有源和无源部件。可以利用平面化从晶片的表面除去材料和制造均匀平面。平面化包括利用抛光垫抛光晶片的表面。在抛光期间，磨料和腐蚀性化学品被添加到晶片的表面。组合的磨料机械作用和化学品腐蚀作用除去了任何不规则的表面形貌(topography)，产生均匀的平面。
后端制造指的是将已完成的晶片切割或单体化成单个管芯，并且然后封装管芯用于结构支撑和环境隔离。为单体化管芯，沿被叫做划片街区(saw street)或划线的晶片非功能区域刻划和断开所述晶片。利用激光切割工具或锯条来单体化晶片。在单体化之后，单个管芯被安装到封装衬底，所述封装衬底包括用来与其它系统部件互连的引脚或接触焊盘。形成在半导体管芯上的接触焊盘然后被连接到封装内的接触焊盘。可以利用焊料凸块、柱形凸块(stud bump)、导电胶、或线结合(wirebond)来制作电连接。密封剂或其它成型材料被沉积到封装上以提供物理支撑和电隔离。已完成的封装然后被插入电系统中并且半导体器件的功能可以用到其它系统部件。
图1示出具有芯片载体衬底或印刷电路板(PCB)52的电子器件50，所述芯片载体衬底或印刷电路板(PCB)52具有多个安装在它的表面上的半导体封装。电子器件50可以具有一种半导体封装、或多种半导体封装，这取决于应用。为了说明的目的，在图1中示出不同类型的半导体封装。
电子器件50可以是利用半导体封装来执行一个或多个电功能的独立系统。可替换地，电子器件50可以是更大系统的子部件。例如，电子器件50可以是能被插入计算机中的图形卡、网络接口卡、或其它信号处理卡。半导体封装可以包括微处理器、存储器、专用集成电路(ASIC)、逻辑电路、模拟电路、RF电路、分立器件、或其它半导体管芯或电部件。
在图1中，PCB 52提供普通的衬底用于安装在PCB上的半导体封装的结构支撑和电互连。利用蒸发、电解电镀、无电电镀、丝网印刷、或其它合适的金属沉积工艺将导电信号迹线(trace)54形成在PCB 52的表面上或各层内。信号迹线54提供半导体封装、安装的部件、以及其它外部系统部件中的每一个之间的电通信。迹线54也将电源和地连接提供给半导体封装中的每一个。
在一些实施例中，半导体器件可以具有两个封装级。第一级封装是用来将半导体管芯以机械和电的方式附着到中间载体的技术。第二级封装包括将所述中间载体以机械和电的方式附着到PCB。在其它实施例中，半导体器件可以仅具有第一级封装，其中管芯被以机械和电的方式直接安装到PCB。
为了说明的目的，几种第一级封装，包括线结合封装56和倒装芯片58，被示出在PCB 52上。另外，几种第二级封装，包括球栅阵列(BGA)60、凸块芯片载体(BCC)62、双列直插式封装(DIP)64、岸面栅格阵列(land grid array，LGA)66、多芯片模块(MCM)68、四侧无引脚扁平封装(quad flat non-leaded package，QFN)70、以及四侧扁平封装72被示出安装在PCB 52上。根据系统要求，利用第一和第二级封装形式的任何组合配置的半导体封装的任何组合、以及其它电子部件，可以被连接到PCB 52。在一些实施例中，电子器件50包括单个附着的半导体封装，虽然其它实施例要求多互连封装。通过在单个衬底上组合一个或多个半导体封装，制造商可以将预先制作的部件并入电子器件和系统中。因为所述半导体封装包括复杂功能，所以可以利用更便宜的部件和流水线制造工艺来制造电子器件。所得到的器件较少可能失效并且制造起来花费较少，对用户而言导致更低的成本。
图2a-2c示出示范性半导体封装。图2a示出安装在PCB 52上的DIP 64的更多细节。半导体管芯74包括包含模拟或数字电路的有源区，所述模拟或数字电路被实现为根据管芯的电设计形成在管芯内并且被电互连的有源器件、无源器件、导电层、和介电层。例如，电路可以包括一个或多个晶体管、二极管、电感器、电容器、电阻器、以及形成在半导体管芯74的有源区内的其它电路元件。接触焊盘76是导电材料(例如铝(AL)、铜(Cu)、锡(Sn)、镍(Ni)、金(Au)、或银(Ag))的一个或多个层，并且电连接到形成在半导体管芯74内的电路元件。在DIP 64的组装期间，利用金硅共晶层或粘附材料(例如热的环氧树脂)将半导体管芯74安装到中间载体78。封装体包括绝缘封装材料，例如聚合物或陶瓷。导体引线80和线结合82在半导体管芯74和PCB 52之间提供电互连。密封剂84被沉积在封装上用于通过防止湿气与粒子进入所述封装以及污染管芯74或线结合82来进行环境保护。
图2b示出安装在PCB 52上的BCC 62的更多细节。半导体管芯88利用底层填料(underfill)或环氧树脂粘附材料92被安装到载体90上。线结合94在接触焊盘96和98之间提供第一级包装(packing)互连。模塑料或密封剂100被沉积在半导体管芯88和线结合94上以为所述器件提供物理支撑和电隔离。接触焊盘102利用电解电镀或无电电镀这样合适的金属沉积形成在PCB 52的表面上以防止氧化。接触焊盘102电连接到PCB 52中的一个或多个导电信号迹线54。凸块104被形成在BCC 62的接触焊盘98与PCB 52的接触焊盘102之间。
在图2c中，利用倒装芯片型第一级封装将半导体管芯58面朝下地安装到中间载体106。半导体管芯58的有源区108包含模拟或数字电路，所述模拟或数字电路被实现为根据管芯的电设计形成的有源器件、无源器件、导电层、和介电层。例如，该电路可以包括一个或多个晶体管、二极管、电感器、电容器、电阻器、以及在有源区108内的其它电路元件。半导体管芯58通过凸块110被电连接和机械连接到载体106。
BGA 60利用凸块112电连接和机械连接到具有BGA型第二级封装的PCB 52。半导体管芯58通过凸块110、信号线114、以及凸块112电连接到导电信号迹线54。模塑料或密封剂116被沉积在半导体管芯58和载体106上以为所述器件提供物理支撑和电隔离。倒装芯片半导体器件提供从半导体管芯58上的有源器件到PCB 52上的导电轨迹的短导电路径以便减小信号传播距离、降低电容、并且改善总的电路性能。在另一个实施例中，半导体管芯58可以在没有中间载体106的情况下利用倒装芯片型第一级封装被以机械和电的方式直接连接到PCB 52。
相对于图1和2a-2c，图3a-3h示出利用安装在衬底的空腔中的具有TSV的半导体管芯形成Fi-PoP的工艺。图3a示出包含基底衬底材料122(例如硅、锗、砷化镓、磷化铟、或碳化硅)用于结构支撑的半导体晶片120。在衬底材料122的第一表面上形成绝缘或钝化层124。同样地，在与衬底材料122的第一表面相对的衬底材料122的第二表面上形成绝缘或钝化层126。绝缘层124和126包括二氧化硅(SiO2)、氮化硅(Si3N4)、氮氧化硅(SiON)、五氧化二钽(Ta2O5)、氧化铝(Al2O3)、或具有类似绝缘和结构特性的其它材料的一个或多个层。利用PVD、CVD、印刷、旋涂、喷涂、烧结、或热氧化来形成绝缘层124和126。如所示地除去绝缘层124和126的一部分。
在图3b中，利用PVD、CVD、溅射、电解电镀、无电电镀工艺或其它合适的金属沉积工艺使用图案化将导电层128形成在绝缘层124的已除去部分中并且将导电层130形成在绝缘层126的已除去部分中。导电层128和130可以是Al、Cu、Sn、Ni、Au、Ag、或其它合适的导电材料的一个或多个层。导电层128的一部分和导电层130的一部分可以根据半导体器件的设计和功能是电共有的(electricallycommon)或被电隔离。
在图3c中，利用激光切割工具或锯条通过绝缘层124和126以及衬底材料122形成空腔或开口136。空腔136可以是矩形、圆形、或其它合适的形状因数。
在图3d中，半导体管芯或部件138被设置在空腔136中并且利用带基(backing tape)140来固定。半导体管芯138包括包含模拟或数字电路的有源表面142，所述模拟或数字电路被实现为根据管芯的电设计和功能形成在管芯内并且电互连的有源器件、无源器件、导电层、和介电层。例如，该电路可以包括一个或多个晶体管、二极管、和形成在有源表面142内的其它电路元件以实现基带模拟电路或数字电路，例如数字信号处理器(DSP)、ASIC、存储器、或其它信号处理电路。半导体管芯138也可以包括IPD，例如电感器、电容器、和电阻器，用于RF信号处理。典型的RF系统需要在一个或多个半导体封装中的多个IPD以执行必要的电功能。可以在空腔136中设置具有直通有机通路(through organic via，TOV)的半导体管芯。在另一个实施例中，半导体管芯或部件138是设置在空腔136中的具有TSV的插入物。
利用激光钻孔或刻蚀工艺，例如深反应离子刻蚀(DRIE)，通过半导体管芯或插入物138形成多个通路。使用PVD、CVD、电解电镀、无电电镀工艺、或其它合适的金属沉积工艺，利用Al、Cu、Sn、Ni、Au、Ag、钛(Ti)、W、多晶硅、或其它合适的导电材料来填充所述通路，以形成导电直通硅通路(TSV)144。TSV 144可以在将半导体管芯138安装在空腔136中之前形成在半导体管芯138中。TSV 144可以根据管芯的设计与衬底120和有源表面142上的可选重分布层(RDL)145电互连。
在图3e中，结合线146被形成在导电层128和TSV 144之间。利用浆料印刷(paste printing)、压缩模塑、传递模塑、液体密封剂模塑、真空层压、或其它合适的施加器(applicator)将密封剂或模塑料148沉积在半导体管芯138和绝缘层124上。密封剂148可以是聚合物复合材料，例如具有填充物的环氧树脂、具有填充物的环氧丙烯酸酯、或具有合适填充物的聚合物。密封剂148不导电并且在环境上保护半导体管芯免受外部元件和污染物的影响。密封剂148的一部分通过刻蚀工艺被除去以暴露有源表面142和TSV 144。在图3f中带基140被除去。
在图3g中，器件被倒转并且利用凸块152将半导体管芯或部件150安装到与有源表面142相对的TSV 144。半导体管芯150包括包含模拟或数字电路的有源表面154，所述模拟或数字电路被实现为根据管芯的电设计和功能形成在管芯内并且电互连的有源器件、无源器件、导电层、和介电层。例如，该电路可以包括一个或多个晶体管、二极管、和形成在有源表面154内的其它电路元件以实现基带模拟电路或数字电路，例如DSP、ASIC、存储器、或其它信号处理电路。半导体管芯150也可以包括IPD，例如电感器、电容器、和电阻器，用于RF信号处理。典型的RF系统需要在一个或多个半导体封装中的多个IPD以执行必要的电功能。底层填料材料156，例如环氧树脂，被沉积在半导体管芯150之下。在另一个实施例中，半导体部件150可以是安装到TSV 144的分立半导体器件。
利用蒸发、电解电镀、无电电镀、球滴(ball drop)、或丝网印刷工艺将导电凸块材料沉积到导电层130上。所述凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料、及其组合，连同可选的焊剂溶液一起。例如，所述凸块材料可以是共晶Sn/Pb、高铅焊料、或无铅焊料。利用合适的附着或结合工艺将所述凸块材料结合到导电层130。在一个实施例中，通过将所述材料加热到它的熔点以上，所述凸块材料回流以形成球形球或凸块158。在一些应用中，凸块158二次回流以改善到导电层130的电接触。所述凸块也可以被压缩结合到导电层130。凸块158表示一种可以形成在导电层130上的互连结构。所述互连结构也可以使用结合线、柱形凸块、微凸块、或其它电互连。
在图3h中，器件被再次倒转，并且利用凸块164将在倒装芯片布置中具有向下取向的接触焊盘162的半导体管芯或部件160安装到TSV 144。半导体管芯160被安装在密封剂148的已除去部分中以减小器件厚度。半导体管芯160包括包含模拟或数字电路的有源表面166，所述模拟或数字电路被实现为根据管芯的电设计和功能形成在管芯内并且电互连的有源器件、无源器件、导电层、和介电层。例如，该电路可以包括一个或多个晶体管、二极管、和形成在有源表面166内的其它电路元件以实现基带模拟电路或数字电路，例如DSP、ASIC、存储器、或其它信号处理电路。半导体管芯160也可以包括IPD，例如电感器、电容器、和电阻器，用于RF信号处理。典型的RF系统需要在一个或多个半导体封装中的多个IPD以执行必要的电功能。在另一个实施例中，半导体部件160可以是安装到TSV 144的分立半导体器件。
图4示出具有半导体管芯、IPD、或设置在衬底120的空腔136中的具有TSV或TOV的插入物的Fi-PoP 168。所述TSV或TOV电互连半导体部件150和160。通过放置半导体管芯、IPD、或在空腔136中的具有TSV或TOV的插入物，Fi-PoP 168的高度可以被减小。另外，将半导体管芯160安装在密封剂148的已除去部分中也减小Fi-PoP 168的厚度。通过穿过半导体管芯的TSV或TOV、IPD、或设置在空腔136中的插入物的直接连接，半导体部件150和160之间的信号传播被减小。
图5示出包括图3a-3f中描述的特征的Fi-PoP结构170。另外，通过凸块176将层叠或引线框插入物172电连接到TSV 144。结合线146通过插入物172电连接到TSV 144。在倒装芯片布置中具有向下取向的接触焊盘的半导体管芯或部件178利用凸块182被安装到插入物172。半导体管芯178包括包含模拟或数字电路的有源表面184，所述模拟或数字电路被实现为根据管芯的电设计和功能形成在管芯内并且电互连的有源器件、无源器件、导电层、和介电层。例如，该电路可以包括一个或多个晶体管、二极管、和形成在有源表面184内的其它电路元件以实现基带模拟电路或数字电路，例如DSP、ASIC、存储器、或其它信号处理电路。半导体管芯178也可以包括IPD，例如电感器、电容器、和电阻器，用于RF信号处理。典型的RF系统需要在一个或多个半导体封装中的多个IPD以执行必要的电功能。在另一个实施例中，半导体部件178可以是安装到插入物172的分立半导体器件。在图3g-3h中描述的特征的其余部分被添加到Fi-PoP结构170。
图6示出包括图3a-3f中描述的特征的Fi-PoP结构190。另外，嵌入式凸块192被电连接到TSV 144或结合线146。利用浆料印刷、压缩模塑、传递模塑、液体密封剂模塑、真空层压、或其它合适的施加器将密封剂或模塑料193沉积在半导体管芯138和绝缘层124上。可替换地，为了更细的节距互连，可以形成嵌入式导电柱或模制通路，而不是嵌入式凸块。密封剂193可以是聚合物复合材料，例如具有填充物的环氧树脂、具有填充物的环氧丙烯酸酯、或具有合适填充物的聚合物。密封剂193不导电并且在环境上保护半导体管芯免受外部元件和污染物的影响。
图7示出包括类似于图3a-3f的特征的Fi-PoP结构200。另外，堤坝(dam)材料或膜上线(wire-on-film(WIF))密封剂材料202被沉积在半导体管芯138上，其消除了对暴露管芯的专用模盒或专门的密封工艺的需要。在图3g-3h中描述的特征的其余部分被添加到Fi-PoP结构200。
图8示出包括图3a-3f中描述的特征的Fi-PoP结构210。另外，半导体管芯或部件212被安装到半导体管芯138上并且利用凸块218被电连接到TSV 144和导电层128。半导体管芯212包括包含模拟或数字电路的有源表面214，所述模拟或数字电路被实现为根据管芯的电设计和功能形成在管芯内并且电互连的有源器件、无源器件、导电层、和介电层。例如，该电路可以包括一个或多个晶体管、二极管、和形成在有源表面214内的其它电路元件以实现基带模拟电路或数字电路，例如DSP、ASIC、存储器、或其它信号处理电路。半导体管芯212也可以包括IPD，例如电感器、电容器、和电阻器，用于RF信号处理。典型的RF系统需要在一个或多个半导体封装中的多个IPD以执行必要的电功能。在另一个实施例中，半导体管芯或部件212可以是安装到半导体管芯138上的具有TSV的插入物。
利用激光钻孔或刻蚀工艺(例如DRIE)通过半导体管芯或插入物212形成多个通路。使用PVD、CVD、电解电镀、无电电镀工艺、或其它合适的金属沉积工艺，利用Al、Cu、Sn、Ni、Au、Ag、Ti、W、多晶硅、或其它合适的导电材料来填充所述通路以形成导电TSV216。TSV 216可以在安装到空腔136上之前形成在半导体管芯212中。TSV 216可以根据管芯的设计与有源表面214上的可选RDL 219电互连。
结合线220被形成在导电层128和TSV 216之间。利用浆料印刷、压缩模塑、传递模塑、液体密封剂模塑、真空层压、或其它合适的施加器将密封剂或模塑料222沉积在半导体管芯212和绝缘层124上。密封剂222可以是聚合物复合材料，例如具有填充物的环氧树脂、具有填充物的环氧丙烯酸酯、或具有合适填充物的聚合物。密封剂222不导电并且在环境上保护半导体管芯免受外部元件和污染物的影响。密封剂222的一部分通过刻蚀工艺被除去以暴露有源表面214和TSV216。
利用凸块226将半导体管芯或部件224安装到与有源表面142相对的TSV 144。半导体管芯224包括包含模拟或数字电路的有源表面228，所述模拟或数字电路被实现为根据管芯的电设计和功能形成在管芯内并且电互连的有源器件、无源器件、导电层、和介电层。例如，该电路可以包括一个或多个晶体管、二极管、和形成在有源表面228内的其它电路元件以实现基带模拟电路或数字电路，例如DSP、ASIC、存储器、或其它信号处理电路。半导体管芯224也可以包括IPD，例如电感器、电容器、和电阻器，用于RF信号处理。典型的RF系统需要在一个或多个半导体封装中的多个IPD以执行必要的电功能。底层填料材料230，例如环氧树脂，被沉积在半导体管芯224下。在另一个实施例中，半导体部件224可以是安装到TSV 144的分立半导体器件。
利用蒸发、电解电镀、无电电镀、球滴、或丝网印刷工艺将导电凸块材料沉积到导电层130上。所述凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料、及其组合，连同可选的焊剂溶液一起。例如，所述凸块材料可以是共晶Sn/Pb、高铅焊料、或无铅焊料。利用合适的附着或结合工艺将所述凸块材料结合到导电层130。在一个实施例中，通过将所述材料加热到它的熔点以上，所述凸块材料回流以形成球形球或凸块232。在一些应用中，凸块232二次回流以改善到导电层130的电接触。所述凸块也可以被压缩结合到导电层130。凸块232表示一种可以形成在导电层130上的互连结构。所述互连结构也可以使用结合线、柱形凸块、微凸块、或其它电互连。
图9示出包括图3a-3f中描述的特征的Fi-PoP结构240。另外，半导体管芯或部件242被设置成部分在空腔136中并且部分在空腔136外。半导体管芯242进一步包括突出于空腔136外部的衬底120之上的凹口或凹进243。半导体管芯242包括包含模拟或数字电路的有源表面244，所述模拟或数字电路被实现为根据管芯的电设计和功能形成在管芯内并且电互连的有源器件、无源器件、导电层、和介电层。例如，该电路可以包括一个或多个晶体管、二极管、和形成在有源表面244内的其它电路元件以实现基带模拟电路或数字电路，例如DSP、ASIC、存储器、或其它信号处理电路。半导体管芯242也可以包括IPD，例如电感器、电容器、和电阻器，用于RF信号处理。典型的RF系统需要在一个或多个半导体封装中的多个IPD以执行必要的电功能。在另一个实施例中，半导体管芯或部件242是被设置成部分在空腔136中并且部分在空腔136外的具有TSV的插入物。
利用激光钻孔或刻蚀工艺(例如DRIE)通过半导体管芯或插入物242形成多个通路。使用PVD、CVD、电解电镀、无电电镀工艺、或其它合适的金属沉积工艺，利用Al、Cu、Sn、Ni、Au、Ag、Ti、W、多晶硅、或其它合适的导电材料来填充所述通路以形成导电TSV246。TSV 246可以在将半导体管芯242安装到空腔136中之前形成在半导体管芯242中。TSV 246可以根据管芯的设计与衬底120和有源表面244上的可选RDL 245电互连。凹口243中的TSV 246利用凸块248电连接到导电层128。
结合线250被形成在导电层128和TSV 246之间。利用浆料印刷、压缩模塑、传递模塑、液体密封剂模塑、真空层压、或其它合适的施加器将密封剂或模塑料252沉积在半导体管芯242和绝缘层124上。密封剂252可以是聚合物复合材料，例如具有填充物的环氧树脂、具有填充物的环氧丙烯酸酯、或具有合适填充物的聚合物。密封剂252不导电并且在环境上保护半导体管芯免受外部元件和污染物的影响。密封剂252的一部分通过刻蚀工艺被除去以暴露有源表面244和TSV246。
利用凸块256将半导体管芯或部件254安装到与有源表面244相对的TSV 246。半导体管芯254包括包含模拟或数字电路的有源表面258，所述模拟或数字电路被实现为根据管芯的电设计和功能形成在管芯内并且电互连的有源器件、无源器件、导电层、和介电层。例如，该电路可以包括一个或多个晶体管、二极管、和形成在有源表面258内的其它电路元件以实现基带模拟电路或数字电路，例如DSP、ASIC、存储器、或其它信号处理电路。半导体管芯254也可以包括IPD，例如电感器、电容器、和电阻器，用于RF信号处理。典型的RF系统需要在一个或多个半导体封装中的多个IPD以执行必要的电功能。底层填料材料260，例如环氧树脂，被沉积在半导体管芯254下。在另一个实施例中，半导体部件254可以是安装到TSV 246的分立半导体器件。
利用蒸发、电解电镀、无电电镀、球滴、或丝网印刷工艺将导电凸块材料沉积到导电层130上。所述凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料、及其组合，连同可选的焊剂溶液一起。例如，所述凸块材料可以是共晶Sn/Pb、高铅焊料、或无铅焊料。利用合适的附着或结合工艺将所述凸块材料结合到导电层130。在一个实施例中，通过将所述材料加热到它的熔点以上，所述凸块材料回流以形成球形球或凸块262。在一些应用中，凸块262二次回流以改善到导电层130的电接触。所述凸块也可以被压缩结合到导电层130。凸块262表示一种可以形成在导电层130上的互连结构。所述互连结构也可以使用结合线、柱形凸块、微凸块、或其它电互连。
在倒装芯片布置中具有向下取向的接触焊盘的半导体管芯或部件264利用凸块266被安装到TSV 246。半导体管芯264包括包含模拟或数字电路的有源表面266，所述模拟或数字电路被实现为根据管芯的电设计和功能形成在管芯内并且电互连的有源器件、无源器件、导电层、和介电层。例如，该电路可以包括一个或多个晶体管、二极管、和形成在有源表面266内的其它电路元件以实现基带模拟电路或数字电路，例如DSP、ASIC、存储器、或其它信号处理电路。半导体管芯264也可以包括IPD，例如电感器、电容器、和电阻器，用于RF信号处理。典型的RF系统需要在一个或多个半导体封装中的多个IPD以执行必要的电功能。在另一个实施例中，半导体部件264可以是安装到TSV 246的分立半导体器件。
图10示出包括图3a-3c中描述的特征和安装在空腔136上的半导体管芯或部件274的Fi-PoP结构270。半导体管芯274包括包含模拟或数字电路的有源表面278，所述模拟或数字电路被实现为根据管芯的电设计和功能形成在管芯内并且电互连的有源器件、无源器件、导电层、和介电层。例如，该电路可以包括一个或多个晶体管、二极管、和形成在有源表面278内的其它电路元件以实现基带模拟电路或数字电路，例如DSP、ASIC、存储器、或其它信号处理电路。半导体管芯274也可以包括IPD，例如电感器、电容器、和电阻器，用于RF信号处理。典型的RF系统需要在一个或多个半导体封装中的多个IPD以执行必要的电功能。在另一个实施例中，半导体管芯或部件274是安装在空腔136上的具有TSV的插入物。
利用激光钻孔或刻蚀工艺(例如DRIE)通过半导体管芯或插入物274形成多个通路。使用PVD、CVD、电解电镀、无电电镀工艺、或其它合适的金属沉积工艺，利用Al、Cu、Sn、Ni、Au、Ag、Ti、W、多晶硅、或其它合适的导电材料来填充所述通路以形成导电TSV280。TSV 280可以在安装半导体管芯274之前形成在半导体管芯274中。TSV 280可以根据管芯的设计与有源表面278上的可选RDL 281电互连。
结合线282被形成在导电层128和有源表面278之间。利用浆料印刷、压缩模塑、传递模塑、液体密封剂模塑、真空层压、或其它合适的施加器将密封剂或模塑料284沉积在半导体管芯274和绝缘层124上。密封剂284可以是聚合物复合材料，例如具有填充物的环氧树脂、具有填充物的环氧丙烯酸酯、或具有合适填充物的聚合物。密封剂284不导电并且在环境上保护半导体管芯免受外部元件和污染物的影响。密封剂284的一部分通过刻蚀工艺被除去以暴露有源表面278和TSV 280。
利用凸块288将半导体管芯或部件286安装到与有源表面278相对的TSV 280。半导体管芯286包括包含模拟或数字电路的有源表面290，所述模拟或数字电路被实现为根据管芯的电设计和功能形成在管芯内并且电互连的有源器件、无源器件、导电层、和介电层。例如，该电路可以包括一个或多个晶体管、二极管、和形成在有源表面290内的其它电路元件以实现基带模拟电路或数字电路，例如DSP、ASIC、存储器、或其它信号处理电路。半导体管芯286也可以包括IPD，例如电感器、电容器、和电阻器，用于RF信号处理。典型的RF系统需要在一个或多个半导体封装中的多个IPD以执行必要的电功能。底层填料材料292，例如环氧树脂，被沉积在半导体管芯286下。在另一个实施例中，半导体部件286可以是安装到TSV 280的分立半导体器件。
利用蒸发、电解电镀、无电电镀、球滴、或丝网印刷工艺将导电凸块材料沉积到导电层130上。所述凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料、及其组合，连同可选的焊剂溶液一起。例如，所述凸块材料可以是共晶Sn/Pb、高铅焊料、或无铅焊料。利用合适的附着或结合工艺将所述凸块材料结合到导电层130。在一个实施例中，通过将所述材料加热到它的熔点以上，所述凸块材料回流以形成球形球或凸块294。在一些应用中，凸块294二次回流以改善到导电层130的电接触。所述凸块也可以被压缩结合到导电层130。凸块294表示一种可以形成在导电层130上的互连结构。所述互连结构也可以使用结合线、柱形凸块、微凸块、或其它电互连。
在倒装芯片布置中具有向下取向的接触焊盘的半导体管芯或部件296利用凸块298被安装到TSV 280。半导体管芯296包括包含模拟或数字电路的有源表面300，所述模拟或数字电路被实现为根据管芯的电设计和功能形成在管芯内并且电互连的有源器件、无源器件、导电层、和介电层。例如，该电路可以包括一个或多个晶体管、二极管、和形成在有源表面300内的其它电路元件以实现基带模拟电路或数字电路，例如DSP、ASIC、存储器、或其它信号处理电路。半导体管芯296也可以包括IPD，例如电感器、电容器、和电阻器，用于RF信号处理。典型的RF系统需要在一个或多个半导体封装中的多个IPD以执行必要的电功能。在另一个实施例中，半导体部件296可以是安装到TSV 280的分立半导体器件。
图11示出被安装到PCB 312的包括图3a-3g中描述的特征的Fi-PoP结构310。热沉314被放置在半导体管芯的后表面之间。热沉314可以是Al、Cu、或具有高热导率的另外的材料，以为半导体管芯150提供热耗散。
虽然已经详细说明本发明的一个或多个实施例，但是本领域技术人员将理解的是，在不脱离由下列权利要求所阐述的本发明的范围的情况下可以对那些实施例进行变型和修改。

Claims (25)

1.一种制造半导体器件的方法，包括：
提供具有第一表面和第二表面的衬底；
形成通过所述衬底的第一表面和第二表面的空腔；
形成通过第一半导体管芯的通路；
利用导电材料填充所述通路以形成导电通路；
在所述空腔中安装第一半导体管芯；
在第一半导体管芯的第一表面和衬底上沉积密封剂；
从第一半导体管芯的第一表面除去密封剂的一部分以暴露所述导电通路；
将第二半导体管芯安装到第一半导体管芯的第一表面，第二半导体管芯电连接到所述导电通路；以及
在与第一半导体管芯的第一表面相对的第一半导体管芯的第二表面上安装第三半导体管芯。
2.如权利要求1所述的方法，进一步包括：
在所述衬底的第一表面上形成第一导电层；以及
在第一导电层和所述导电通路之间形成结合线。
3.如权利要求1所述的方法，进一步包括在第一半导体管芯和第二半导体管芯之间设置插入物。
4.如权利要求1所述的方法，进一步包括在第一半导体管芯和第二半导体管芯之间设置具有多个导电通路的第四半导体管芯。
5.如权利要求1所述的方法，其中第一半导体管芯在所述空腔之上延伸。
6.如权利要求1所述的方法，进一步包括在与第一半导体管芯相对的第三半导体管芯的表面上形成热沉。
7.一种制造半导体器件的方法，包括：
提供具有第一表面和第二表面的衬底；
形成通过所述衬底的第一表面和第二表面的空腔；
在所述空腔中安装第一半导体部件，第一半导体部件具有导电直通硅通路(TSV)；
在第一半导体部件的第一表面和衬底上沉积密封剂；
从第一半导体部件的第一表面除去密封剂的一部分以暴露所述导电TSV；以及
将第二半导体部件安装到第一半导体部件的第一表面，第二半导体部件电连接到所述导电TSV。
8.如权利要求7所述的方法，进一步包括在与第一半导体部件的第一表面相对的第一半导体部件的第二表面上安装第三半导体部件。
9.如权利要求7所述的方法，进一步包括：
在所述衬底的第一表面上形成第一导电层；以及
在第一导电层和所述导电TSV之间形成结合线。
10.如权利要求7所述的方法，进一步包括在第一半导体部件和第二半导体部件之间设置插入物。
11.如权利要求7所述的方法，进一步包括在第一半导体部件和第二半导体部件之间设置具有多个导电通路的第三半导体部件。
12.如权利要求7所述的方法，其中第一半导体部件在所述空腔之上延伸。
13.如权利要求7所述的方法，其中第一半导体部件是半导体管芯、集成的无源器件、或插入物。
14.一种制造半导体器件的方法，包括：
提供具有第一表面和第二表面的衬底；
形成通过所述衬底的第一表面和第二表面的空腔；
在所述空腔上安装第一半导体部件，第一半导体部件具有导电直通硅通路(TSV)；
在第一半导体部件的第一表面上安装第二半导体部件；
在衬底和第二半导体部件上沉积密封剂；以及
在与第一半导体部件的第一表面相对的第一半导体部件的第二表面上安装第三半导体部件。
15.如权利要求14所述的方法，进一步包括在第一半导体部件和第二半导体部件之间形成凸块。
16.如权利要求14所述的方法，进一步包括在第一半导体部件和第二半导体部件之间设置插入物。
17.如权利要求14所述的方法，进一步包括在第一半导体部件和第二半导体部件之间设置具有导电TSV的第四半导体部件。
18.如权利要求14所述的方法，其中第一半导体部件是半导体管芯、集成的无源器件、或插入物。
19.如权利要求14所述的方法，进一步包括：
在所述衬底的第一表面上形成第一导电层；
在第一导电层和导电TSV之间形成结合线；以及
在所述结合线上沉积膜中线材料。
20.一种半导体器件，包括：
具有通过衬底的第一表面和第二表面形成的空腔的衬底；
安装在所述空腔中的第一半导体部件，第一半导体部件具有导电直通硅通路(TSV)；
安装在第一半导体部件的第一表面上的第二半导体部件；
沉积在衬底和第二半导体部件上的密封剂；以及
安装在与第一半导体部件的第一表面相对的第一半导体部件的第二表面上的第三半导体部件。
21.如权利要求20所述的器件，进一步包括设置在第一半导体部件和第二半导体部件之间的插入物。
22.如权利要求20所述的器件，进一步包括在第一半导体部件和第二半导体部件之间设置具有导电TSV的第四半导体部件。
23.如权利要求20所述的器件，其中第一半导体部件是半导体管芯、集成的无源器件、或插入物。
24.如权利要求20所述的器件，进一步包括形成在与第一半导体管芯相对的第三半导体管芯的表面上的热沉。
25.如权利要求20所述的器件，其中第一半导体管芯在所述空腔之上延伸。
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