SG168467A1 - Semiconductor device and method of mounting die with tsv in cavity of substrate for electrical interconnect of fi-pop - Google Patents
Semiconductor device and method of mounting die with tsv in cavity of substrate for electrical interconnect of fi-popInfo
- Publication number
- SG168467A1 SG168467A1 SG201004467-5A SG2010044675A SG168467A1 SG 168467 A1 SG168467 A1 SG 168467A1 SG 2010044675 A SG2010044675 A SG 2010044675A SG 168467 A1 SG168467 A1 SG 168467A1
- Authority
- SG
- Singapore
- Prior art keywords
- semiconductor die
- substrate
- cavity
- tsv
- semiconductor device
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title abstract 14
- 239000000758 substrate Substances 0.000 title abstract 4
- 239000008393 encapsulating agent Substances 0.000 abstract 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5385—Assembly of a plurality of insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/141—Disposition
- H01L2224/1418—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/14181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
- H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73257—Bump and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
- H01L2224/85005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate being a temporary or sacrificial substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/0651—Wire or wire-like electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01032—Germanium [Ge]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01049—Indium [In]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01073—Tantalum [Ta]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/1026—Compound semiconductors
- H01L2924/1032—III-V
- H01L2924/10329—Gallium arsenide [GaAs]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12044—OLED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1433—Application-specific integrated circuit [ASIC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/533,943 US8263434B2 (en) | 2009-07-31 | 2009-07-31 | Semiconductor device and method of mounting die with TSV in cavity of substrate for electrical interconnect of Fi-PoP |
Publications (1)
Publication Number | Publication Date |
---|---|
SG168467A1 true SG168467A1 (en) | 2011-02-28 |
Family
ID=43526207
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG201004467-5A SG168467A1 (en) | 2009-07-31 | 2010-06-22 | Semiconductor device and method of mounting die with tsv in cavity of substrate for electrical interconnect of fi-pop |
SG2012081378A SG185950A1 (en) | 2009-07-31 | 2010-06-22 | Semiconductor device and method of mounting die with tsv in cavity of substrate for electrical interconnect of fi-pop |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG2012081378A SG185950A1 (en) | 2009-07-31 | 2010-06-22 | Semiconductor device and method of mounting die with tsv in cavity of substrate for electrical interconnect of fi-pop |
Country Status (4)
Country | Link |
---|---|
US (2) | US8263434B2 (zh) |
CN (1) | CN101989558B (zh) |
SG (2) | SG168467A1 (zh) |
TW (1) | TWI508226B (zh) |
Families Citing this family (173)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7420206B2 (en) * | 2006-07-12 | 2008-09-02 | Genusion Inc. | Interposer, semiconductor chip mounted sub-board, and semiconductor package |
US8569876B2 (en) | 2006-11-22 | 2013-10-29 | Tessera, Inc. | Packaged semiconductor chips with array |
JP5584474B2 (ja) | 2007-03-05 | 2014-09-03 | インヴェンサス・コーポレイション | 貫通ビアによって前面接点に接続された後面接点を有するチップ |
JP2010535427A (ja) | 2007-07-31 | 2010-11-18 | テッセラ,インコーポレイテッド | 貫通シリコンビアを使用する半導体実装プロセス |
TWI373109B (en) | 2008-08-06 | 2012-09-21 | Unimicron Technology Corp | Package structure |
US8471376B1 (en) * | 2009-05-06 | 2013-06-25 | Marvell International Ltd. | Integrated circuit packaging configurations |
US8263434B2 (en) * | 2009-07-31 | 2012-09-11 | Stats Chippac, Ltd. | Semiconductor device and method of mounting die with TSV in cavity of substrate for electrical interconnect of Fi-PoP |
US9466561B2 (en) * | 2009-08-06 | 2016-10-11 | Rambus Inc. | Packaged semiconductor device for high performance memory and logic |
US8441123B1 (en) * | 2009-08-13 | 2013-05-14 | Amkor Technology, Inc. | Semiconductor device with metal dam and fabricating method |
USRE48111E1 (en) | 2009-08-21 | 2020-07-21 | JCET Semiconductor (Shaoxing) Co. Ltd. | Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect |
US8383457B2 (en) | 2010-09-03 | 2013-02-26 | Stats Chippac, Ltd. | Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect |
US8169058B2 (en) * | 2009-08-21 | 2012-05-01 | Stats Chippac, Ltd. | Semiconductor device and method of stacking die on leadframe electrically connected by conductive pillars |
US8895358B2 (en) * | 2009-09-11 | 2014-11-25 | Stats Chippac, Ltd. | Semiconductor device and method of forming cavity in PCB containing encapsulant or dummy die having CTE similar to CTE of large array WLCSP |
US8803332B2 (en) * | 2009-09-11 | 2014-08-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Delamination resistance of stacked dies in die saw |
TWI436470B (zh) | 2009-09-30 | 2014-05-01 | Advanced Semiconductor Eng | 封裝製程及封裝結構 |
TWI392069B (zh) | 2009-11-24 | 2013-04-01 | Advanced Semiconductor Eng | 封裝結構及其封裝製程 |
US8405229B2 (en) * | 2009-11-30 | 2013-03-26 | Endicott Interconnect Technologies, Inc. | Electronic package including high density interposer and circuitized substrate assembly utilizing same |
CN102097335B (zh) * | 2009-12-10 | 2013-03-20 | 日月光半导体制造股份有限公司 | 封装结构及其封装工艺 |
US20110193235A1 (en) * | 2010-02-05 | 2011-08-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3DIC Architecture with Die Inside Interposer |
US10297550B2 (en) | 2010-02-05 | 2019-05-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D IC architecture with interposer and interconnect structure for bonding dies |
US8519537B2 (en) | 2010-02-26 | 2013-08-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D semiconductor package interposer with die cavity |
US9385095B2 (en) | 2010-02-26 | 2016-07-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D semiconductor package interposer with die cavity |
KR101695846B1 (ko) * | 2010-03-02 | 2017-01-16 | 삼성전자 주식회사 | 적층형 반도체 패키지 |
US8618654B2 (en) * | 2010-07-20 | 2013-12-31 | Marvell World Trade Ltd. | Structures embedded within core material and methods of manufacturing thereof |
US8455995B2 (en) | 2010-04-16 | 2013-06-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | TSVs with different sizes in interposers for bonding dies |
TWI427753B (zh) * | 2010-05-20 | 2014-02-21 | Advanced Semiconductor Eng | 封裝結構以及封裝製程 |
US9048233B2 (en) * | 2010-05-26 | 2015-06-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package systems having interposers |
TWI502723B (zh) * | 2010-06-18 | 2015-10-01 | Chipmos Technologies Inc | 多晶粒堆疊封裝結構 |
KR101765473B1 (ko) * | 2010-06-21 | 2017-08-24 | 삼성전자 주식회사 | 인쇄 회로 기판 및 이를 포함하는 반도체 패키지 |
JP5826532B2 (ja) * | 2010-07-15 | 2015-12-02 | 新光電気工業株式会社 | 半導体装置及びその製造方法 |
US8796135B2 (en) | 2010-07-23 | 2014-08-05 | Tessera, Inc. | Microelectronic elements with rear contacts connected with via first or via middle structures |
US8791575B2 (en) | 2010-07-23 | 2014-07-29 | Tessera, Inc. | Microelectronic elements having metallic pads overlying vias |
US9640437B2 (en) | 2010-07-23 | 2017-05-02 | Tessera, Inc. | Methods of forming semiconductor elements using micro-abrasive particle stream |
TWI460834B (zh) * | 2010-08-26 | 2014-11-11 | Unimicron Technology Corp | 嵌埋穿孔晶片之封裝結構及其製法 |
US8409918B2 (en) * | 2010-09-03 | 2013-04-02 | Stats Chippac, Ltd. | Semiconductor device and method of forming pre-molded substrate to reduce warpage during die mounting |
US8847380B2 (en) | 2010-09-17 | 2014-09-30 | Tessera, Inc. | Staged via formation from both sides of chip |
US8610259B2 (en) | 2010-09-17 | 2013-12-17 | Tessera, Inc. | Multi-function and shielded 3D interconnects |
US8786066B2 (en) | 2010-09-24 | 2014-07-22 | Intel Corporation | Die-stacking using through-silicon vias on bumpless build-up layer substrates including embedded-dice, and processes of forming same |
US20120119345A1 (en) * | 2010-11-15 | 2012-05-17 | Cho Sungwon | Integrated circuit packaging system with device mount and method of manufacture thereof |
US8895380B2 (en) | 2010-11-22 | 2014-11-25 | Bridge Semiconductor Corporation | Method of making semiconductor assembly with built-in stiffener and semiconductor assembly manufactured thereby |
US8736066B2 (en) | 2010-12-02 | 2014-05-27 | Tessera, Inc. | Stacked microelectronic assemby with TSVS formed in stages and carrier above chip |
US8587126B2 (en) | 2010-12-02 | 2013-11-19 | Tessera, Inc. | Stacked microelectronic assembly with TSVs formed in stages with plural active chips |
US8637968B2 (en) * | 2010-12-02 | 2014-01-28 | Tessera, Inc. | Stacked microelectronic assembly having interposer connecting active chips |
US8610264B2 (en) | 2010-12-08 | 2013-12-17 | Tessera, Inc. | Compliant interconnects in wafers |
US11101408B2 (en) * | 2011-02-07 | 2021-08-24 | Creeled, Inc. | Components and methods for light emitting diode (LED) lighting |
US9059160B1 (en) | 2010-12-23 | 2015-06-16 | Marvell International Ltd. | Semiconductor package assembly |
TWI496271B (zh) * | 2010-12-30 | 2015-08-11 | Ind Tech Res Inst | 晶圓級模封接合結構及其製造方法 |
CN102751248A (zh) * | 2011-04-22 | 2012-10-24 | 欣兴电子股份有限公司 | 嵌埋穿孔芯片的封装结构及其制法 |
US8966747B2 (en) | 2011-05-11 | 2015-03-03 | Vlt, Inc. | Method of forming an electrical contact |
US8514576B1 (en) | 2011-06-14 | 2013-08-20 | Juniper Networks, Inc. | Dual sided system in a package |
US8247269B1 (en) * | 2011-06-29 | 2012-08-21 | Fairchild Semiconductor Corporation | Wafer level embedded and stacked die power system-in-package packages |
US9245773B2 (en) | 2011-09-02 | 2016-01-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device packaging methods and structures thereof |
US9418876B2 (en) | 2011-09-02 | 2016-08-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of three dimensional integrated circuit assembly |
US9082832B2 (en) * | 2011-09-21 | 2015-07-14 | Stats Chippac, Ltd. | Semiconductor device and method of forming protection and support structure for conductive interconnect structure |
US9484259B2 (en) | 2011-09-21 | 2016-11-01 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming protection and support structure for conductive interconnect structure |
US9236278B2 (en) | 2011-09-23 | 2016-01-12 | Stats Chippac Ltd. | Integrated circuit packaging system with a substrate embedded dummy-die paddle and method of manufacture thereof |
US20130082383A1 (en) * | 2011-10-03 | 2013-04-04 | Texas Instruments Incorporated | Electronic assembly having mixed interface including tsv die |
US9076664B2 (en) * | 2011-10-07 | 2015-07-07 | Freescale Semiconductor, Inc. | Stacked semiconductor die with continuous conductive vias |
US9414484B2 (en) | 2011-11-09 | 2016-08-09 | Intel Corporation | Thermal expansion compensators for controlling microelectronic package warpage |
US20130154106A1 (en) | 2011-12-14 | 2013-06-20 | Broadcom Corporation | Stacked Packaging Using Reconstituted Wafers |
DE112011105990T5 (de) | 2011-12-22 | 2014-09-11 | Intel Corporation | Integriertes 3D-Schaltungspaket mit Fensterinterposer |
US9484319B2 (en) * | 2011-12-23 | 2016-11-01 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming extended semiconductor device with fan-out interconnect structure to reduce complexity of substrate |
US9123700B2 (en) | 2012-01-06 | 2015-09-01 | Micron Technology, Inc. | Integrated circuit constructions having through substrate vias and methods of forming integrated circuit constructions having through substrate vias |
KR101818507B1 (ko) | 2012-01-11 | 2018-01-15 | 삼성전자 주식회사 | 반도체 패키지 |
US9548251B2 (en) | 2012-01-12 | 2017-01-17 | Broadcom Corporation | Semiconductor interposer having a cavity for intra-interposer die |
US20130187284A1 (en) | 2012-01-24 | 2013-07-25 | Broadcom Corporation | Low Cost and High Performance Flip Chip Package |
US8558395B2 (en) * | 2012-02-21 | 2013-10-15 | Broadcom Corporation | Organic interface substrate having interposer with through-semiconductor vias |
US8587132B2 (en) | 2012-02-21 | 2013-11-19 | Broadcom Corporation | Semiconductor package including an organic substrate and interposer having through-semiconductor vias |
US8749072B2 (en) | 2012-02-24 | 2014-06-10 | Broadcom Corporation | Semiconductor package with integrated selectively conductive film interposer |
US8872321B2 (en) | 2012-02-24 | 2014-10-28 | Broadcom Corporation | Semiconductor packages with integrated heat spreaders |
US9275976B2 (en) | 2012-02-24 | 2016-03-01 | Broadcom Corporation | System-in-package with integrated socket |
US8928128B2 (en) | 2012-02-27 | 2015-01-06 | Broadcom Corporation | Semiconductor package with integrated electromagnetic shielding |
US9633149B2 (en) * | 2012-03-14 | 2017-04-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | System and method for modeling through silicon via |
US8648473B2 (en) * | 2012-03-27 | 2014-02-11 | Infineon Technologies Ag | Chip arrangement and a method for forming a chip arrangement |
US9484320B2 (en) * | 2012-04-27 | 2016-11-01 | Freescale Semiconductor, Inc. | Vertically packaged integrated circuit |
US9040346B2 (en) | 2012-05-03 | 2015-05-26 | Infineon Technologies Ag | Semiconductor package and methods of formation thereof |
US9349663B2 (en) | 2012-06-29 | 2016-05-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Package-on-package structure having polymer-based material for warpage control |
US9508563B2 (en) * | 2012-07-12 | 2016-11-29 | Xilinx, Inc. | Methods for flip chip stacking |
US8519543B1 (en) * | 2012-07-17 | 2013-08-27 | Futurewei Technologies, Inc. | Large sized silicon interposers overcoming the reticle area limitations |
US8907227B2 (en) * | 2012-08-02 | 2014-12-09 | Hong Kong Science and Technology Research Institute Company Limited | Multiple surface integrated devices on low resistivity substrates |
US9136293B2 (en) * | 2012-09-07 | 2015-09-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus for sensor module |
CN102915984A (zh) * | 2012-09-20 | 2013-02-06 | 日月光半导体制造股份有限公司 | 半导体封装构造及其制造方法 |
US9620413B2 (en) | 2012-10-02 | 2017-04-11 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of using a standardized carrier in semiconductor packaging |
US9496195B2 (en) | 2012-10-02 | 2016-11-15 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of depositing encapsulant along sides and surface edge of semiconductor die in embedded WLCSP |
KR101419601B1 (ko) | 2012-11-20 | 2014-07-16 | 앰코 테크놀로지 코리아 주식회사 | Emc 웨이퍼 서포트 시스템을 이용한 반도체 디바이스 및 이의 제조방법 |
JP2014112606A (ja) * | 2012-12-05 | 2014-06-19 | Shinko Electric Ind Co Ltd | 半導体パッケージ |
KR102107038B1 (ko) * | 2012-12-11 | 2020-05-07 | 삼성전기주식회사 | 칩 내장형 인쇄회로기판과 그를 이용한 반도체 패키지 및 칩 내장형 인쇄회로기판의 제조방법 |
US9704824B2 (en) | 2013-01-03 | 2017-07-11 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming embedded wafer level chip scale packages |
US9721862B2 (en) | 2013-01-03 | 2017-08-01 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of using a standardized carrier to form embedded wafer level chip scale packages |
US9997443B2 (en) | 2013-02-25 | 2018-06-12 | Infineon Technologies Ag | Through vias and methods of formation thereof |
KR20140119522A (ko) | 2013-04-01 | 2014-10-10 | 삼성전자주식회사 | 패키지-온-패키지 구조를 갖는 반도체 패키지 |
US8878350B1 (en) * | 2013-04-12 | 2014-11-04 | Maxim Integrated Products, Inc. | Semiconductor device having a buffer material and stiffener |
JPWO2014188632A1 (ja) * | 2013-05-23 | 2017-02-23 | パナソニック株式会社 | 放熱構造を有する半導体装置および半導体装置の積層体 |
US9082757B2 (en) | 2013-10-31 | 2015-07-14 | Freescale Semiconductor, Inc. | Stacked semiconductor devices |
KR101631934B1 (ko) * | 2013-11-13 | 2016-06-21 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지 구조물 및 그 제작 방법 |
US9059127B1 (en) | 2014-01-09 | 2015-06-16 | International Business Machines Corporation | Packages for three-dimensional die stacks |
TWI557865B (zh) * | 2014-01-29 | 2016-11-11 | 矽品精密工業股份有限公司 | 堆疊組及其製法與基板結構 |
US9935090B2 (en) | 2014-02-14 | 2018-04-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Substrate design for semiconductor packages and method of forming same |
US10056267B2 (en) | 2014-02-14 | 2018-08-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Substrate design for semiconductor packages and method of forming same |
US10026671B2 (en) | 2014-02-14 | 2018-07-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Substrate design for semiconductor packages and method of forming same |
US9653443B2 (en) | 2014-02-14 | 2017-05-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Thermal performance structure for semiconductor packages and method of forming same |
US9768090B2 (en) | 2014-02-14 | 2017-09-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Substrate design for semiconductor packages and method of forming same |
US9136256B2 (en) | 2014-02-20 | 2015-09-15 | Texas Instruments Incorporated | Converter having partially thinned leadframe with stacked chips and interposer, free of wires and clips |
US11291146B2 (en) | 2014-03-07 | 2022-03-29 | Bridge Semiconductor Corp. | Leadframe substrate having modulator and crack inhibiting structure and flip chip assembly using the same |
US10121768B2 (en) * | 2015-05-27 | 2018-11-06 | Bridge Semiconductor Corporation | Thermally enhanced face-to-face semiconductor assembly with built-in heat spreader and method of making the same |
US20170133352A1 (en) * | 2015-05-27 | 2017-05-11 | Bridge Semiconductor Corporation | Thermally enhanced semiconductor assembly with three dimensional integration and method of making the same |
US20170133353A1 (en) * | 2015-05-27 | 2017-05-11 | Bridge Semiconductor Corporation | Semiconductor assembly with three dimensional integration and method of making the same |
US10361151B2 (en) | 2014-03-07 | 2019-07-23 | Bridge Semiconductor Corporation | Wiring board having isolator and bridging element and method of making wiring board |
US9269700B2 (en) | 2014-03-31 | 2016-02-23 | Micron Technology, Inc. | Stacked semiconductor die assemblies with improved thermal performance and associated systems and methods |
KR101676916B1 (ko) * | 2014-08-20 | 2016-11-16 | 앰코 테크놀로지 코리아 주식회사 | 반도체 디바이스의 제조 방법 및 이에 따른 반도체 디바이스 |
KR102237978B1 (ko) | 2014-09-11 | 2021-04-09 | 삼성전자주식회사 | 반도체 패키지 및 그 제조방법 |
KR102194722B1 (ko) * | 2014-09-17 | 2020-12-23 | 삼성전기주식회사 | 패키지 기판, 패키지 기판의 제조 방법 및 이를 포함하는 적층형 패키지 |
US9718678B2 (en) * | 2014-09-25 | 2017-08-01 | Infineon Technologies Ag | Package arrangement, a package, and a method of manufacturing a package arrangement |
KR102307490B1 (ko) * | 2014-10-27 | 2021-10-05 | 삼성전자주식회사 | 반도체 패키지 |
US10002653B2 (en) | 2014-10-28 | 2018-06-19 | Nxp Usa, Inc. | Die stack address bus having a programmable width |
US11069734B2 (en) | 2014-12-11 | 2021-07-20 | Invensas Corporation | Image sensor device |
US9899442B2 (en) | 2014-12-11 | 2018-02-20 | Invensas Corporation | Image sensor device |
DE102014118769B4 (de) * | 2014-12-16 | 2017-11-23 | Infineon Technologies Ag | Drucksensor-Modul mit einem Sensor-Chip und passiven Bauelementen innerhalb eines gemeinsamen Gehäuses |
US9331043B1 (en) * | 2015-01-30 | 2016-05-03 | Invensas Corporation | Localized sealing of interconnect structures in small gaps |
US9564416B2 (en) | 2015-02-13 | 2017-02-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structures and methods of forming the same |
US20170243803A1 (en) * | 2015-05-27 | 2017-08-24 | Bridge Semiconductor Corporation | Thermally enhanced semiconductor assembly with three dimensional integration and method of making the same |
US10264664B1 (en) | 2015-06-04 | 2019-04-16 | Vlt, Inc. | Method of electrically interconnecting circuit assemblies |
US9601461B2 (en) * | 2015-08-12 | 2017-03-21 | Semtech Corporation | Semiconductor device and method of forming inverted pyramid cavity semiconductor package |
US9559081B1 (en) | 2015-08-21 | 2017-01-31 | Apple Inc. | Independent 3D stacking |
US11901274B2 (en) | 2015-09-25 | 2024-02-13 | Intel Corporation | Packaged integrated circuit device with recess structure |
WO2017111825A1 (en) * | 2015-12-26 | 2017-06-29 | Intel Corporation | Hybrid technology 3-d die stacking |
CN107039389B (zh) * | 2016-02-04 | 2020-04-24 | 欣兴电子股份有限公司 | 封装基板与其制作方法 |
US10797038B2 (en) * | 2016-02-25 | 2020-10-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor package and rework process for the same |
KR102085789B1 (ko) | 2016-02-29 | 2020-03-06 | 스몰텍 에이비 | 인터포저 디바이스 및 인터포저 디바이스 제조방법 |
US11336167B1 (en) | 2016-04-05 | 2022-05-17 | Vicor Corporation | Delivering power to semiconductor loads |
US10785871B1 (en) | 2018-12-12 | 2020-09-22 | Vlt, Inc. | Panel molded electronic assemblies with integral terminals |
US10158357B1 (en) | 2016-04-05 | 2018-12-18 | Vlt, Inc. | Method and apparatus for delivering power to semiconductors |
FR3050073B1 (fr) * | 2016-04-12 | 2018-05-04 | Mbda France | Systeme electronique pourvu d'une pluralite de fonctions electroniques interconnectees |
US10121766B2 (en) * | 2016-06-30 | 2018-11-06 | Micron Technology, Inc. | Package-on-package semiconductor device assemblies including one or more windows and related methods and packages |
US9935079B1 (en) | 2016-12-08 | 2018-04-03 | Nxp Usa, Inc. | Laser sintered interconnections between die |
TWI625080B (zh) * | 2016-12-20 | 2018-05-21 | 鈺橋半導體股份有限公司 | 具有隔離件及橋接件之線路板及其製法 |
US11276667B2 (en) * | 2016-12-31 | 2022-03-15 | Intel Corporation | Heat removal between top and bottom die interface |
TWI657555B (zh) * | 2017-02-02 | 2019-04-21 | 鈺橋半導體股份有限公司 | 三維整合之半導體組體及其製作方法 |
US10005660B1 (en) | 2017-02-15 | 2018-06-26 | Advanced Semiconductor Engineering, Inc. | Semiconductor package device including microelectromechanical system |
JP6649308B2 (ja) | 2017-03-22 | 2020-02-19 | キオクシア株式会社 | 半導体装置およびその製造方法 |
US10269756B2 (en) | 2017-04-21 | 2019-04-23 | Invensas Bonding Technologies, Inc. | Die processing |
US10242967B2 (en) * | 2017-05-16 | 2019-03-26 | Raytheon Company | Die encapsulation in oxide bonded wafer stack |
US10217720B2 (en) | 2017-06-15 | 2019-02-26 | Invensas Corporation | Multi-chip modules formed using wafer-level processing of a reconstitute wafer |
US10373893B2 (en) * | 2017-06-30 | 2019-08-06 | Intel Corporation | Embedded bridge with through-silicon vias |
US10804115B2 (en) | 2017-08-03 | 2020-10-13 | General Electric Company | Electronics package with integrated interconnect structure and method of manufacturing thereof |
US10541153B2 (en) | 2017-08-03 | 2020-01-21 | General Electric Company | Electronics package with integrated interconnect structure and method of manufacturing thereof |
US10541209B2 (en) * | 2017-08-03 | 2020-01-21 | General Electric Company | Electronics package including integrated electromagnetic interference shield and method of manufacturing thereof |
TWI766072B (zh) | 2017-08-29 | 2022-06-01 | 瑞典商斯莫勒科技公司 | 能量存儲中介層裝置、電子裝置和製造方法 |
CN108346588B (zh) * | 2017-09-30 | 2020-12-04 | 中芯集成电路(宁波)有限公司 | 一种晶圆级系统封装方法以及封装结构 |
DE102018102144A1 (de) * | 2018-01-31 | 2019-08-01 | Tdk Electronics Ag | Elektronisches Bauelement |
US10727219B2 (en) | 2018-02-15 | 2020-07-28 | Invensas Bonding Technologies, Inc. | Techniques for processing devices |
WO2020010265A1 (en) | 2018-07-06 | 2020-01-09 | Invensas Bonding Technologies, Inc. | Microelectronic assemblies |
US10832985B2 (en) | 2018-09-27 | 2020-11-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Sensor package and method |
CN110010487B (zh) * | 2018-10-10 | 2021-01-26 | 浙江集迈科微电子有限公司 | 一种立式焊接的射频芯片系统级封装工艺 |
US11152333B2 (en) * | 2018-10-19 | 2021-10-19 | Micron Technology, Inc. | Semiconductor device packages with enhanced heat management and related systems |
EP3644359A1 (en) * | 2018-10-23 | 2020-04-29 | AT & S Austria Technologie & Systemtechnik Aktiengesellschaft | Z-axis interconnection with protruding component |
EP3644693A1 (en) * | 2018-10-23 | 2020-04-29 | AT & S Austria Technologie & Systemtechnik Aktiengesellschaft | Surface mounted device in cavity |
JP2022510692A (ja) * | 2018-12-06 | 2022-01-27 | アナログ ディヴァイスィズ インク | パッシブデバイスアセンブリを備えた集積デバイスパッケージ |
CN113395936A (zh) | 2018-12-06 | 2021-09-14 | 美国亚德诺半导体公司 | 屏蔽的集成器件封装 |
KR102589684B1 (ko) | 2018-12-14 | 2023-10-17 | 삼성전자주식회사 | 반도체 패키지 |
KR20200092566A (ko) * | 2019-01-25 | 2020-08-04 | 에스케이하이닉스 주식회사 | 브리지 다이를 포함한 반도체 패키지 |
US11296053B2 (en) | 2019-06-26 | 2022-04-05 | Invensas Bonding Technologies, Inc. | Direct bonded stack structures for increased reliability and improved yield in microelectronics |
US11189604B2 (en) * | 2019-10-15 | 2021-11-30 | Advanced Semiconductor Engineering, Inc. | Device assembly structure and method of manufacturing the same |
US11329016B2 (en) * | 2020-02-12 | 2022-05-10 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package and method of manufacturing the same |
US11742314B2 (en) | 2020-03-31 | 2023-08-29 | Adeia Semiconductor Bonding Technologies Inc. | Reliable hybrid bonded apparatus |
US11239220B2 (en) * | 2020-06-30 | 2022-02-01 | Nanya Technology Corporation | Semiconductor package and method of fabricating the same |
US11631647B2 (en) | 2020-06-30 | 2023-04-18 | Adeia Semiconductor Bonding Technologies Inc. | Integrated device packages with integrated device die and dummy element |
US11664340B2 (en) | 2020-07-13 | 2023-05-30 | Analog Devices, Inc. | Negative fillet for mounting an integrated device die to a carrier |
US11942386B2 (en) * | 2020-08-24 | 2024-03-26 | Texas Instruments Incorporated | Electronic devices in semiconductor package cavities |
US11764177B2 (en) | 2020-09-04 | 2023-09-19 | Adeia Semiconductor Bonding Technologies Inc. | Bonded structure with interconnect structure |
US11728273B2 (en) | 2020-09-04 | 2023-08-15 | Adeia Semiconductor Bonding Technologies Inc. | Bonded structure with interconnect structure |
US11557565B2 (en) | 2020-10-06 | 2023-01-17 | Nxp Usa, Inc. | Semiconductor device assembly and method therefor |
US11502054B2 (en) | 2020-11-11 | 2022-11-15 | Nxp Usa, Inc. | Semiconductor device assembly and method therefor |
Family Cites Families (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001077301A (ja) * | 1999-08-24 | 2001-03-23 | Amkor Technology Korea Inc | 半導体パッケージ及びその製造方法 |
TW494549B (en) * | 1999-12-13 | 2002-07-11 | Siliconware Precision Industries Co Ltd | Semiconductor package having plural chips |
US7273769B1 (en) * | 2000-08-16 | 2007-09-25 | Micron Technology, Inc. | Method and apparatus for removing encapsulating material from a packaged microelectronic device |
US6706553B2 (en) * | 2001-03-26 | 2004-03-16 | Intel Corporation | Dispensing process for fabrication of microelectronic packages |
US6906415B2 (en) * | 2002-06-27 | 2005-06-14 | Micron Technology, Inc. | Semiconductor device assemblies and packages including multiple semiconductor devices and methods |
SG120879A1 (en) * | 2002-08-08 | 2006-04-26 | Micron Technology Inc | Packaged microelectronic components |
KR100620203B1 (ko) * | 2002-12-30 | 2006-09-01 | 동부일렉트로닉스 주식회사 | 반도체의 더블 사이드 스택 패키징 방법 |
SG133445A1 (en) * | 2005-12-29 | 2007-07-30 | Micron Technology Inc | Methods for packaging microelectronic devices and microelectronic devices formed using such methods |
US7741707B2 (en) * | 2006-02-27 | 2010-06-22 | Stats Chippac Ltd. | Stackable integrated circuit package system |
TWI330401B (en) * | 2006-12-25 | 2010-09-11 | Unimicron Technology Corp | Circuit board structure having embedded semiconductor component and fabrication method thereof |
KR100891330B1 (ko) * | 2007-02-21 | 2009-03-31 | 삼성전자주식회사 | 반도체 패키지 장치와, 반도체 패키지의 제조방법과,반도체 패키지 장치를 갖는 카드 장치 및 반도체 패키지장치를 갖는 카드 장치의 제조 방법 |
TW200840008A (en) * | 2007-03-27 | 2008-10-01 | Phoenix Prec Technology Corp | Multi-chip semiconductor package structure |
US7723159B2 (en) * | 2007-05-04 | 2010-05-25 | Stats Chippac, Ltd. | Package-on-package using through-hole via die on saw streets |
TWI335059B (en) * | 2007-07-31 | 2010-12-21 | Siliconware Precision Industries Co Ltd | Multi-chip stack structure having silicon channel and method for fabricating the same |
TW200917431A (en) * | 2007-10-05 | 2009-04-16 | Advanced Semiconductor Eng | Stacked-type chip package structure and method of fabricating the same |
TW200929509A (en) * | 2007-12-21 | 2009-07-01 | Powertech Technology Inc | Package structure for multi-die stacking |
US8722457B2 (en) | 2007-12-27 | 2014-05-13 | Stats Chippac, Ltd. | System and apparatus for wafer level integration of components |
SG155793A1 (en) * | 2008-03-19 | 2009-10-29 | Micron Technology Inc | Upgradeable and repairable semiconductor packages and methods |
US7977779B2 (en) * | 2008-06-10 | 2011-07-12 | Stats Chippac Ltd. | Mountable integrated circuit package-in-package system |
US7973310B2 (en) * | 2008-07-11 | 2011-07-05 | Chipmos Technologies Inc. | Semiconductor package structure and method for manufacturing the same |
US7911070B2 (en) * | 2008-09-25 | 2011-03-22 | Stats Chippac Ltd. | Integrated circuit packaging system having planar interconnect |
US8237257B2 (en) * | 2008-09-25 | 2012-08-07 | King Dragon International Inc. | Substrate structure with die embedded inside and dual build-up layers over both side surfaces and method of the same |
US8063475B2 (en) | 2008-09-26 | 2011-11-22 | Stats Chippac Ltd. | Semiconductor package system with through silicon via interposer |
US7786008B2 (en) * | 2008-12-12 | 2010-08-31 | Stats Chippac Ltd. | Integrated circuit packaging system having through silicon vias with partial depth metal fill regions and method of manufacture thereof |
US20100327419A1 (en) * | 2009-06-26 | 2010-12-30 | Sriram Muthukumar | Stacked-chip packages in package-on-package apparatus, methods of assembling same, and systems containing same |
US8263434B2 (en) * | 2009-07-31 | 2012-09-11 | Stats Chippac, Ltd. | Semiconductor device and method of mounting die with TSV in cavity of substrate for electrical interconnect of Fi-PoP |
-
2009
- 2009-07-31 US US12/533,943 patent/US8263434B2/en active Active
-
2010
- 2010-06-22 SG SG201004467-5A patent/SG168467A1/en unknown
- 2010-06-22 SG SG2012081378A patent/SG185950A1/en unknown
- 2010-07-15 TW TW099123256A patent/TWI508226B/zh active
- 2010-07-30 CN CN201010243890.0A patent/CN101989558B/zh active Active
-
2012
- 2012-08-03 US US13/566,287 patent/US9064876B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
SG185950A1 (en) | 2012-12-28 |
CN101989558B (zh) | 2014-12-31 |
US8263434B2 (en) | 2012-09-11 |
US20120292785A1 (en) | 2012-11-22 |
US20110024888A1 (en) | 2011-02-03 |
US9064876B2 (en) | 2015-06-23 |
TW201104797A (en) | 2011-02-01 |
CN101989558A (zh) | 2011-03-23 |
TWI508226B (zh) | 2015-11-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
SG168467A1 (en) | Semiconductor device and method of mounting die with tsv in cavity of substrate for electrical interconnect of fi-pop | |
SG169931A1 (en) | Semiconductor device and method of forming open cavity in tsv interposer to contain semiconductor die in wlcsmp | |
GB2492512B (en) | Semiconductor structure | |
SG169266A1 (en) | Semiconductor device and method of dualmolding die formed on opposite sides of build-up interconnect structure | |
SG152981A1 (en) | Wafer level package integration and method | |
SG169929A1 (en) | Semiconductor device and method of forming cavity in pcb containing encapsulant or dummy die having cte similar to cte of large array wlcsp | |
SG153721A1 (en) | Semiconductor device and method of forming interconnect structure for encapsulated die having pre-applied protective layer | |
TW201130102A (en) | Semiconductor device and method for forming the same | |
SG170693A1 (en) | Semiconductor package and method of mounting semiconductor die to opposite sides of tsv substrate | |
WO2007089723A3 (en) | Thermal enhanced package | |
SG169268A1 (en) | Semiconductor device and method of forming dual-active sided semiconductor die in fan-out wafer level chip scale package | |
SG168468A1 (en) | Semiconductor device and method of forming cavity in build-up interconnect structure for short signal path between die | |
TW200644187A (en) | Semiconductor device and method for manufacturing semiconductor device | |
SG153722A1 (en) | Semiconductor device and method of forming the device using sacrificial carrier | |
EP2461361A3 (en) | Package substrate unit and method for manufacturing package substrate unit | |
TW200629490A (en) | Semiconductor device, method of manufacturing the same, capacitor structure, and method of manufacturing the same | |
SG165243A1 (en) | Semiconductor device and method of forming a thin wafer without a carrier | |
SG153719A1 (en) | System-in-package having integrated passive devices and method therefor | |
TW200627562A (en) | Chip electrical connection structure and fabrication method thereof | |
SG10201403206VA (en) | Semiconductor device and method of forming low profile 3d fan-out package | |
SG148920A1 (en) | Wafer level integration package | |
EP2988325A3 (en) | Electrical interconnect structure for an embedded semiconductor device package and method of manufacturing thereof | |
SG171522A1 (en) | Semiconductor device and method of forming compliant stress relief buffer around large array wlcsp | |
TW200729398A (en) | 3D IC method and device | |
WO2009002381A3 (en) | Mold compound circuit structure for enhanced electrical and thermal performance |