CN108336037B - 一种晶圆级系统封装结构和电子装置 - Google Patents

一种晶圆级系统封装结构和电子装置 Download PDF

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CN108336037B
CN108336037B CN201810070260.4A CN201810070260A CN108336037B CN 108336037 B CN108336037 B CN 108336037B CN 201810070260 A CN201810070260 A CN 201810070260A CN 108336037 B CN108336037 B CN 108336037B
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substrate
chips
chip
plug
electrically connected
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CN108336037A (zh
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刘孟彬
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Ningbo Semiconductor International Corp
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Ningbo Semiconductor International Corp
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Priority to PCT/CN2018/093769 priority Critical patent/WO2019062240A1/zh
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Priority to US16/158,789 priority patent/US10811385B2/en
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Abstract

本发明提供一种晶圆级系统封装结构和电子装置，包括：形成有多个第一芯片的衬底，所述第一芯片利用半导体工艺生长而成；内嵌有多个第二芯片的封装层，所述封装层覆盖所述衬底和所述第一芯片；至少其中一个所述第二芯片与至少其中一个所述第一芯片通过导电凸块电连接，电连接的第一芯片和第二芯片具有重叠部分。根据本发明的晶圆级系统封装结构，使晶圆级封装与系统集成方法相结合，同时实现了多种芯片的集成和在衬底上完成封装制造优势。

Description

一种晶圆级系统封装结构和电子装置
技术领域
本发明涉及半导体技术领域，具体而言涉及一种晶圆级系统封装结构和电子装置。
背景技术
系统封装(System in Package，简称SiP)将多个不同功能的有源元件，以及无源元件、微机电系统(MEMS)、光学元件等其他元件，组合到一个单元中，形成一个可提供多种功能的系统或子系统，允许异质IC集成，是最好的封装集成技术。相比于片上系统(SystemOn Chip，简称SoC)封装，SiP集成相对简单，设计周期和面市周期更短，成本较低，可以实现更复杂的系统。
与传统的SiP相比，晶圆级系统封装(wafer level package,简称WLP)是在衬底上完成封装集成制程，具有大幅减小封装结构的面积、降低制造成本、优化电性能、批次制造等优势，可明显的降低工作量与设备的需求。
传统的晶圆级封装方法通常包括：提供基底，在基底上形成介电层，然后再在基底上通过黏合层来将多个第一芯片附着至介电层，之后，再在基底上形成另一介电层，再在介电层中形成导电层，随后，在第一芯片上堆叠第二芯片，接着，在介电层上形成成型材料以围绕第二芯片。然而上述方法具有过程复杂，使用黏合层粘接芯片的稳定性差等问题。
鉴于晶圆级系统封装的显著优势，如何能够更好的实现晶圆级系统封装一直是业界内研究的热点。
发明内容
在发明内容部分中引入了一系列简化形式的概念，这将在具体实施方式部分中进一步详细说明。本发明的发明内容部分并不意味着要试图限定出所要求保护的技术方案的关键特征和必要技术特征，更不意味着试图确定所要求保护的技术方案的保护范围。
针对目前存在的问题，本发明一方面提供一种晶圆级系统封装结构，包括：
形成有多个第一芯片的衬底，所述第一芯片利用半导体工艺在所述衬底上生长而成；
内嵌有多个第二芯片的封装层，所述封装层覆盖所述衬底和所述第一芯片；
至少其中一个所述第二芯片与至少其中一个所述第一芯片通过导电凸块电连接，电连接的第一芯片和第二芯片具有重叠部分。
示例性地，所述衬底具有正面和背面，所述封装层覆盖所述正面或背面。
示例性地，所述封装结构还包括：
相对于所述封装层，位于所述衬底另一面的第一焊盘；
插塞，电连接所述第一焊盘和所述第一芯片。
示例性地，所述导电凸块材料为锡，或者，铜。
示例性地，所述封装层为塑封层。
示例性地，所述塑封层的材料为环氧树脂。
示例性地，还包括：具有开口的钝化层，覆盖所述第一焊盘和所述衬底，所述开口暴露出所述第一焊盘。
示例性地，还包括：第二焊盘，位于所述衬底正面，与所述第一芯片电连接。
本发明再一方面还提供一种电子装置，包括：
形成有多个第一芯片的衬底，所述第一芯片利用半导体工艺在所述衬底上生长而成；
内嵌有多个第二芯片的封装层，所述封装层覆盖所述衬底和所述第一芯片；
至少其中一个所述第二芯片与至少其中一个所述第一芯片通过导电凸块电连接，电连接的第一芯片和第二芯片具有重叠部分。
示例性地，所述衬底具有正面和背面，所述封装层覆盖所述正面或背面。
示例性地，所述封装结构还包括：
相对于所述封装层，位于所述衬底另一面的第一焊盘；
插塞，电连接所述第一焊盘和所述第一芯片。
示例性地，所述导电凸块材料为锡，或者，铜。
示例性地，所述封装层为塑封层。
示例性地，所述塑封层的材料为环氧树脂。
示例性地，还包括：具有开口的钝化层，覆盖所述第一焊盘和所述衬底，所述开口暴露出所述第一焊盘。
示例性地，还包括：第二焊盘，位于所述衬底正面，与所述第一芯片电连接。
本发明的晶圆级系统封装结构包括形成有多个第一芯片的衬底，所述第一芯片利用半导体工艺生长而成；内嵌有多个第二芯片的封装层，所述封装层覆盖所述衬底和所述第一芯片；至少其中一个所述第二芯片与至少其中一个所述第一芯片电连接，将由半导体工艺生长在衬底上的第一芯片和第二芯片集成在晶圆级系统封装结构中，因此可以大幅减小晶圆级系统封装结构的面积，并提供更好的电性能。本发明的电子装置也具有与所述晶圆级封装结构相同的优点。
另外，在本发明的晶圆级系统封装结构的制备过程中，使晶圆级封装与系统集成方法相结合，同时实现了多种芯片的集成和在衬底上完成封装制造优势，能够大幅减小形成的封装结构的面积、降低制造成本、优化封装结构的电性能、批次制造，并明显的降低工作量与设备的需求，从而最终提高了晶圆级系统封装方法的良率，以及形成的封装结构的性能。
附图说明
本发明的下列附图在此作为本发明的一部分用于理解本发明。附图中示出了本发明的实施例及其描述，用来解释本发明的原理。
附图中：
图1A至图1E示出了本发明一个具体实施方式的方法依次实施所获得结构的剖面示意图；
图2A至图2E示出了为了获得图1A所示的结构一个具体实施方式的方法依次实施获得结构的剖面示意图；
图3A至图3C示出了一个具体实施方式的形成插塞的方法依次实施获得结构的剖面示意图；
图4A至图4F示出了为了获得图1C所示的结构一个具体实施方式的方法依次实施获得结构的剖面示意图；
图5A至图5E示出了本发明再一个具体实施方式的方法依次实施所获得结构的剖面示意图；
图6示出了本发明一个具体实施方式的晶圆级系统封装方法的流程图；
图7示出了本发明一个具体实施方式的电子装置的示意图。
具体实施方式
在下文的描述中，给出了大量具体的细节以便提供对本发明更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本发明可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本发明发生混淆，对于本领域公知的一些技术特征未进行描述。
应当理解的是，本发明能够以不同形式实施，而不应当解释为局限于这里提出的实施例。相反地，提供这些实施例将使公开彻底和完全，并且将本发明的范围完全地传递给本领域技术人员。在附图中，为了清楚，层和区的尺寸以及相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本发明教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本发明的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
这里参考作为本发明的理想实施例(和中间结构)的示意图的横截面图来描述发明的实施例。这样，可以预期由于例如制造技术和/或容差导致的从所示形状的变化。因此，本发明的实施例不应当局限于在此所示的区的特定形状，而是包括由于例如制造导致的形状偏差。图中显示的区实质上是示意性的，它们的形状并不意图显示器件的区的实际形状且并不意图限定本发明的范围。
为了彻底理解本发明，将在下列的描述中提出详细结构以及步骤，以便阐释本发明提出的技术方案。本发明的较佳实施例详细描述如下，然而除了这些详细描述外，本发明还可以具有其他实施方式。
实施例一
鉴于晶圆级封装的优势，本发明提出一种晶圆级系统封装结构，其主要包括：
形成有多个第一芯片的衬底，所述第一芯片利用半导体工艺在所述衬底上生长而成；
内嵌有多个第二芯片的封装层，所述封装层覆盖所述衬底和所述第一芯片；
至少其中一个所述第二芯片与至少其中一个所述第一芯片通过导电凸块电连接，电连接的第一芯片和第二芯片具有重叠部分。
下面，参考图1E对本发明的晶圆级系统封装结构做详细描述，其中，图1E示出了本发明一个具体实施方式的晶圆级系统封装结构的剖面示意图。
作为示例，如图1E所示，所述晶圆级系统封装结构包括形成有多个第一芯片101的衬底100。
在一个示例中，如图1E所示，所述晶圆级系统封装结构还包括内嵌有多个第二芯片201的封装层202，所述封装层202覆盖所述衬底100和所述第一芯片101。
示例性地，至少其中一个所述第二芯片201与至少其中一个所述第一芯片101电连接，例如，至少其中一个所述第二芯片201与至少其中一个所述第一芯片101通过导电凸块电连接。
在一个示例中，如图1E所示，电连接的所述第一芯片101和所述第二芯片201具有重叠部分，也即电连接的所述第一芯片101和所述第二芯片201上下具有重叠部分，可以是部分重叠，在第一芯片101和第二芯片201尺寸完全相同时，还可以是完全重叠，其中，此处的重叠可以是指：第一芯片101和第二芯片201在俯视方向上重叠。
在一个示例中，电连接的所述第一芯片101和第二芯片201通过导电凸块(bump)104电连接。
示例性地，在多个第一芯片101中的至少一个的表面上设置有多个导电凸块104，所述导电凸块104在所述第一芯片的表面上呈阵列排布。
在一个示例中，如图1E所示，所述封装结构还包括：相对于所述封装层202(也可以为相对于第二芯片201)，位于所述衬底100另一面的第一焊盘105。
示例性地，如图1E所示，所述封装层202覆盖所述衬底100的正面，则所述第一焊盘105设置在所述衬底100的背面。
示例性地，在多个所述第一芯片101中的至少一个中设置有至少一个插塞102，所述插塞102贯穿所述第一芯片101，例如，所述插塞102贯穿所述第一芯片101，并贯穿所述衬底的正面和背面，与形成在衬底背面的第一焊盘105电连接。
示例性地，所述插塞102设置在所述第一芯片101的边缘区域，或者其他适合的能够实现与第一芯片101电连接而不影响第一芯片101功能实现的区域。
在一个示例中，每个第一焊盘105分别电连接一个所述插塞102，所述第一焊盘105用于将第一芯片101和/或第二芯片201组成的器件结构引出与外部电路实现连接。
在一个示例中，如图1E，所述封装结构还包括第二焊盘103，所述第二焊盘103设置在所述衬底100设置有所述第二芯片201的表面上，例如，如图1E所示，所述第二焊盘103位于所述衬底100正面，并与所述第一芯片101电连接。
在一个示例中，在所述第一芯片101的表面还形成有多个间隔设置的第二焊盘103，其中，多个第二焊盘103中的至少一个设置在所述插塞102的表面上与所述插塞102电连接，也即第二焊盘103设置在所述导电凸块104和所述第一芯片101之间，相邻所述第二焊盘103之间存在间隔。
在一个示例中，所述导电凸块104设置在所述第二焊盘103上，并与所述第二焊盘电连接。
在一个示例中，在第二焊盘和所述导电凸块104之间还可以设置有凸块下金属化(UBM)结构(未示出)，凸块下金属化(UBM)结构可由粘附层、阻挡层、和种子或润湿层的多层金属堆叠而成。UBM结构有助于防止凸块和多芯片半导体器件的集成电路之间的扩散，同时提供了低阻电连接。
在一个示例中，如图1E所示，所述封装层202覆盖所述衬底100和所述第一芯片101，并使所述第二芯片201包围在所述封装层202内。
示例性地，如图1E所示，所述衬底100具有正面和背面，所述封装层202覆盖所述正面。
其中，所述封装层202的顶面高于所述第二芯片201的顶面，所述封装层202对第二芯片起到固定作用，并且能够提供物理和电气保护，防止外界干扰。
在一个示例中，如图1E所示，所述封装结构还包括具有开口107的钝化层106，所述钝化层106覆盖所述第一焊盘105和所述衬底100，所述开口107暴露出所述第一焊盘105，所述开口107露出所述第一焊盘105的至少部分表面。
示例性地，所述钝化层106的顶面高于所述第一焊盘105的顶面。所述钝化层的厚度可以是任意适合的厚度，在此不做具体限定
本发明所涉及的衬底100可以是以下所提到的半导体材料中的至少一种：Si、Ge、SiGe、SiC、SiGeC、InAs、GaAs、InP、InGaAs或者其它III/V化合物半导体，还包括这些半导体构成的多层结构等，或者为绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等。衬底100还可以是其他适合的衬底结构，衬底100还可以为单层或者包括多层(即两层或者多于两层)。
值得一提的是，在本发明中所提及的芯片(例如第一芯片101和第二芯片201)可以是任意一种半导体芯片，其可以包括存储器、逻辑电路、功率器件、双极器件、单独的MOS晶体管、微机电系统(MEMS)等有源器件，甚至也可以是发光二极管等光电器件，其也可以为无源器件，例如电阻、电容等。其中，所述第一芯片101和第二芯片201通过半导体工艺生长在所述衬底上，第一芯片和第二芯片的功能不同其所使用的半导体工艺也会不同，并且直接生长在衬底上的芯片相比通过其他的例如粘接工艺形成的芯片，其可靠性更高，并且可以节省更多的工艺过程。
在此为了简便，仅以一方框的形式简单示出了第一芯片101和第二芯片201，但可以想到的是第一芯片的结构可以包括多个构成元件以及将第一芯片引出的再布线(也即金属互连结构)等等，其中，金属互连结构可以包括多层金属层以及电连接相邻金属层的接触孔，在第一芯片生长的过程中会在衬底上形成多层介电层，相邻的第一芯片101之间以及相邻的第二芯片201之间可以由形成在衬底上的介电层隔开，形成类似如图1E所示的每个所述第一芯片101和第二芯片201嵌入在衬底表面内的结构。
在一个示例中，介电层的材料可以是本领域技术人员熟知的任何适合的介电材料，包括但不限于SiO2、碳氟化合物(CF)、掺碳氧化硅(SiOC)或碳氮化硅(SiCN)等等。
多个第一芯片101之间以及多个第二芯片201之间可以具有相同或不同的功能。多个第一芯片101之间多个第二芯片201之间可以具有相同或不同的尺寸。第一芯片101和第二芯片201的实际数目、功能和尺寸由设计要求决定并且不受限制。可选地，第二芯片201可以是和第一芯片101具有不同功能的不同类型的芯片，也可以是为相同的芯片。
本发明所涉及的导电凸块104可以为锡球、或铜柱、或金凸点、或合金凸块等等，也可以为其他适合的导电凸块结构。
导电凸块104主要包括金属材料，金属材料包括但不限于锡、铜、镍、银锡铜合金或者锡基合金中的至少一种材料。
本发明所涉及的第一焊盘105和第二焊盘103的材料均可以为任意适合的金属材料，包括但不限于Ag、Au、Cu、Pd、Cr、Mo、Ti、Ta、Sn、W和Al中的至少一种金属。
本发明所涉及的插塞102可以是本领域技术人员熟知的任何适合的金属插塞或者硅插塞(也即硅通孔，TSV)，金属插塞的材料可以包括但不限于Ag、Au、Cu、Pd、Cr、Mo、Ti、Ta、Sn、W和Al中的至少一种金属，而硅插塞的材料可以包括掺杂的多晶硅或者未掺杂的多晶硅等。
在一个示例中，本发明所涉及的封装层202可以是本领域技术人员熟知的任何适合的封装材料，例如，所述封装层202为塑封层，所述塑封层包括热固性树脂，在成型过程中能软化或流动，具有可塑性，可制成一定形状，同时又发生化学反应而交联固化，塑封层可以包括酚醛树脂、脲醛树脂、三聚氰胺－甲醛树脂、环氧树脂、不饱和树脂、聚氨酯、聚酰亚胺等热固性树脂中的至少一种，其中，较佳地使用环氧树脂作为塑封层，其中环氧树脂可以采用有填料物质或者是无填料物质的环氧树脂，还包括各种添加剂(例如，固化剂、改性剂、脱模剂、热色剂、阻燃剂等)，例如以酚醛树脂作为固化剂，以固体颗粒(例如硅微粉)等作为填料。示例性地，塑封层还可以包括硅胶。
本发明所涉及的钝化层106的材料可以使用任何适合的绝缘材料，例如所述钝化层106使用诸如氧化硅层、氮化硅层、或氮氧化硅层的无机绝缘层，可通过化学气相沉积、物理气相沉积或原子层沉积等沉积方法沉积形成所述钝化层106；还可以使用诸如包含聚乙烯苯酚、聚酰亚胺、或硅氧烷等的层的绝缘层等。聚乙烯苯酚、聚酰亚胺、或硅氧烷可有效地通过微滴排放法、印刷术或旋涂法形成。硅氧烷根据其结构可被分类成二氧化硅玻璃、烷基硅氧烷聚合物、烷基倍半硅氧烷(alkylsilsesquioxane)聚合物、倍半硅氧烷氢化物(silsesquioxane hydride)聚合物、烷基倍半硅氧烷氢化物(alkylsilsesquioxanehydride)聚合物等。此外，绝缘材料可用包括具有Si-N键的聚合物(聚硅氨烷)的材料形成。此外，可层叠这些膜以形成钝化层。
至此完成了对本发明的封装结构的描述，对于完整的结构，还可能包括其他的元件，在此不做具体赘述。
综上所述，本发明的晶圆级系统封装结构包括形成有多个第一芯片的衬底，所述第一芯片利用半导体工艺生长而成，内嵌有多个第二芯片的封装层，所述封装层覆盖所述衬底和所述第一芯片，至少其中一个所述第二芯片与至少其中一个所述第一芯片电连接，将由半导体工艺生长在衬底上的第一芯片和第二芯片集成在晶圆级系统封装结构中，因此可以大幅减小晶圆级系统封装结构的面积，并提供更好的电性能。本发明的电子装置也具有与所述晶圆级封装结构相同的优点。
实施例二
下面，参考图5E对本发明的晶圆级系统封装结构做详细描述。
作为示例，本发明还提供一种晶圆级系统封装结构，如图5E所示，所述衬底100具有正面和背面，所述封装层202覆盖所述背面，也即所述封装层202覆盖所述衬底100设置有第二芯片的表面。
示例性地，所述封装层202覆盖所述衬底100的背面，则所述第一焊盘105设置在所述衬底100的正面。
在一个示例中，所述封装结构还包括插塞102，所述插塞102电连接所述第一焊盘105和所述第一芯片101。
示例性地，如图5E所示，所述插塞102贯穿所述第一芯片101，并贯穿所述衬底的正面和背面，与形成在衬底正面的第一焊盘105电连接，具体可以根据实际的封装结构进行合理设置。
示例性地，如图5E所示，所述第二焊盘103位于所述衬底100背面，并与所述插塞102和所述第一芯片101电连接。
在本实施例中，所涉及的与前述实施例一相同的结构和膜层可以参考前述实施例一中的描述，在此不做赘述。
本实施例的晶圆级系统封装结构也同样具有前述实施一中晶圆级系统封装结构的优点。
实施例三
鉴于晶圆级系统封装的优势，本发明提出一种晶圆级系统封装方法，如图6所示，其主要包括以下步骤：
步骤S1，提供具有多个第一芯片的衬底，所述第一芯片利用半导体工艺在所述衬底上生长而成；
步骤S2，提供多个第二芯片，将所述第二芯片设置在所述衬底上，使至少其中一个第二芯片与至少其中一个所述第一芯片通过导电凸块电连接，电连接的第一芯片和第二芯片具有重叠部分；
步骤S3，将封装材料覆盖所述第二芯片和所述衬底，以固定所述第二芯片。
根据本发明的晶圆级系统封装方法，使晶圆级封装与系统集成方法相结合，同时实现了多种芯片的集成和在衬底上完成封装制造优势，能够大幅减小形成的封装结构的面积、降低制造成本、优化封装结构的电性能、批次制造，并明显的降低工作量与设备的需求，从而最终提高了晶圆级系统封装方法的良率，以及形成的封装结构的性能。
下面，参考图1A至图1E、图2A至图2E、图3A至图3C、图4A至图4F、图5A至图5E对本发明的晶圆级系统封装方法做详细描述。
作为示例，该封装方法可以用于前述实施例一中的封装结构的制备，本发明的晶圆级系统封装方法包括以下步骤：
首先，执行步骤一，如图1A所示，提供具有多个第一芯片101的衬底100，电连接的第一芯片和第二芯片具有重叠部分。
多个第一芯片101之间可以具有相同或不同的功能。多个第一芯片101之间可以具有相同或不同的尺寸。第一芯片101的实际数目、功能和尺寸由设计要求决定并且不受限制。
在一个示例中，如图1A所示，在对衬底的背面进行减薄之前，所述衬底100中还具有与所述第一芯片101电连接的插塞102，所述插塞102向衬底100背面延伸的端部埋在所述背面之下，也即插塞102的端部埋在衬底100中。
示例性地，所述插塞102设置在所述第一芯片101的边缘区域，或者其他适合的能够实现与第一芯片101电连接而不影响第一芯片101功能实现的区域。
插塞102可以是本领域技术人员熟知的任何适合的金属插塞或者硅插塞(TSV)，金属插塞的材料可以包括但不限于Ag、Au、Cu、Pd、Cr、Mo、Ti、Ta、Sn、W和Al中的至少一种金属，而硅插塞的材料可以包括掺杂的多晶硅或者未掺杂的多晶硅等。
可以使用本领域技术人员熟知的任何适合的方法形成所述插塞102，在一个示例中，可以首先在衬底的正面形成图案化的掩膜层(未示出)，该掩膜层可以包括书中掩膜材料中的任何一种，包括但不限于：硬掩膜材料和光刻胶掩膜材料，较佳地，所述掩膜层使用光刻胶掩膜材料，可以通过在衬底的表面旋涂光刻胶掩膜材料，再利用光刻工艺对光刻胶掩膜材料进行图案化，以形成图案化的光刻胶掩膜材料，在图案化的光刻胶掩膜材料中定义了预定形成的插塞的位置和关键尺寸，然后再以图案化的掩膜层为掩膜，刻蚀部分所述第一芯片101和部分衬底100，以形成通孔，该刻蚀工艺可以是湿法刻蚀或者干法刻蚀工艺，其中较佳地使用干法刻蚀工艺，干法刻蚀包括但不限于：反应离子刻蚀(RIE)、离子束刻蚀、等离子体刻蚀或者激光切割，随后，将图案化的掩膜层去除，例如使用灰化的方法去除光刻胶掩膜材料，最后，沉积金属材料或者多晶硅材料填充所述通孔，以形成金属插塞或者硅插塞。
在一个示例中，在所述衬底的正面形成第二焊盘103，所述第二焊盘103与所述第一芯片101电连接，其中，所述第二焊盘103设置在所述第一芯片101的表面，并且还可以使部分所述第二焊盘103设置在所述插塞102的表面上与所述插塞102电连接，相邻所述第二焊盘103之间存在间隔。
可以使用任何适合的方法形成所述第二焊盘103，例如，可以通过包括但不限于物理气相沉积方法或者化学气相沉积方法的沉积方法形成焊盘材料层以覆盖衬底的正面，再通过刻蚀的方法去除部分所述焊盘材料层，以形成多个间隔设置的第二焊盘103。
接着，执行步骤二，提供多个第二芯片，将所述第二芯片设置在所述衬底上，使至少其中一个第二芯片与至少其中一个所述第一芯片通过导电凸块电连接。
示例性地，第二芯片201可以是和第一芯片101具有不同功能的不同类型的芯片，也可以是为相同的芯片。
示例性地，如图1A所示，至少其中一个所述第二芯片201与至少其中一个所述第一芯片101通过导电凸块104电连接。
在一个示例中，如图1A所示，电连接的所述第一芯片101和所述第二芯片201具有重叠部分，也即电连接的所述第一芯片101和所述第二芯片201上下具有重叠部分，可以是部分重叠，在第一芯片101和第二芯片201尺寸完全相同时，还可以是完全重叠，其中，此处的重叠可以是指：第一芯片101和第二芯片201在俯视方向上重叠。
在一个示例中，继续如图1A所示，将所述第二芯片201设置在所述衬底100上，使至少其中一个第二芯片201与至少其中一个所述第一芯片101电连接的步骤包括A1和A2：
步骤A1，在所述第一芯片101的表面形成至少一个导电凸块104，例如，在每个所述第一芯片的表面形成至少一个导电凸块104。
示例性地，所述导电凸块104还进一步地形成在第二焊盘103上。所述导电凸块104还可以在所述第一芯片101的表面上呈阵列排布。
可以通过任何适合的方法形成所述导电凸块104，在一个示例中，所述导电凸块104为焊球(例如锡球)时，可以通过植球工艺将焊球放置于至少其中一个所述第一芯片的表面上(也即预定形成凸块的位置上)，进一步地，放置在相应的第二焊盘103上，其中，所述植球工艺是指将选择好的与焊盘相匹配的焊球，对应放置于焊盘之上，此过程称为植球，植球工艺可以为人工植球或者植球器植球。
示例性地，所述植球工艺可以是将植球网罩设在第一芯片101的表面上，将焊球放置到植球网上平铺，将所述焊球从所述植球网上的通孔粘到第一芯片的表面。
再经过回流焊工艺，熔融焊球以使其与第一芯片电连接，在设置有第二焊盘103时，则与所述第二焊盘103电连接。作为一个实例，回流焊的温度范围为200℃～260℃，也可以是其他适合的温度。
步骤A2，继续如图1A所示，将所述第二芯片201放置在所述导电凸块104上，所述第一芯片101和第二芯片201通过所述导电凸块104电连接。
在一个示例中，将所述第二芯片201放置在所述导电凸块上之后，通过回流焊的方式熔融所述导电凸块104，以将所述第二芯片201与所述导电凸块104电连接。
在一个示例中，还可以通过在第一芯片上(尤其是第二焊盘103上)通过丝网印刷法沉积焊锡膏，将第二芯片对应设置在衬底上后，再进行回流焊，以实现第一芯片和第二芯片的电连接。
尽管仅示出了以导电凸块的方式实现第一芯片和第二芯片的连接，但可以想到的是，对于其他的能够实现第一芯片和第二芯片相接合并电连接的接合方式也同样适用于本发明，例如可以通过丝焊等方式。
在一个示例中，在第二焊盘103和所述导电凸块104之间还可以设置有凸块下金属化(UBM)结构(未示出)，凸块下金属化(UBM)结构可由粘附层、阻挡层、和种子或润湿层的多层金属堆叠而成。UBM结构有助于防止凸块和多芯片半导体器件的集成电路之间的扩散，同时提供了低阻电连接。
接着，执行步骤三，将封装材料覆盖所述第二芯片和所述衬底，以固定所述第二芯片。
示例性地，如图1B所示，可以通过注塑成型工艺将封装材料覆盖所述第二芯片201和所述衬底100，所述注塑成型可以为热压注塑成型工艺，或者其他适合的注塑成型工艺。
示例性地，所述注塑成型工艺使用液体的塑封料(Mold Compound)或者固体的塑封料，其中，较佳得使用液体的塑封料，以使液体的塑封料在固化前能够填充在相邻导电凸块之间的间隙中，也即第一芯片和第二芯片之间的间隙中，增加第一芯片和第二芯片之间的粘结性，提高封装的稳固性。
在一个示例中，将封装材料覆盖所述第二芯片和所述衬底的步骤包括：提供模具，将所述衬底放置于所述模具中，其中，所述模具可以为任何适合的模具，在此不做具体限定，随后，在所述模具中注入熔融状态的塑封料，液态的塑封料均匀涂覆于整个衬底上，将第二芯片201包裹起来，接着，进行固化处理，以使所述塑封料凝固，以形成塑封层作为所述封装层202，所述固化可以为热固化工艺，具体的根据实际使用的塑封料而合理选择适合的固化方式，最后进行脱模。
示例性地，所述封装层202的顶面高于所述第二芯片201的顶面，所述封装层202对芯片提供物理和电气保护，防止外界干扰。
在一个示例中，如图1B所示，所述衬底100具有正面和背面，所述封装层202覆盖所述正面，此时所述第二芯片201设置在所述衬底100的正面。
在一个示例中，如图1C所示，所述衬底100中还具有与所述第一芯片101电连接的插塞102，所述插塞102向衬底100背面延伸的端部埋在所述背面之下，再将封装材料覆盖所述第二芯片201和所述衬底200的正面之后，还包括：对所述衬底100的背面进行减薄，直至露出所述插塞102。
值得一提的是，该减薄还可以对插塞进行过刻蚀，直到衬底的厚度达到目标厚度。
在将封装材料覆盖所述第二芯片和所述衬底的正面之后，再进行插塞的制作的封装方法，由于塑封层通常使用的为有机材料，而衬底通常为无机材料(例如硅)，两者材料不同，热膨胀系数相应也不一致，很容易使得封装结构发生翘曲变形，进而影响后续制程例如背部研磨(grinding)的可操作性以及良率，并且使得机械手在不同制程之间传输晶圆时对晶圆的抓取变的更加不易，导致碎片或者抓取不成功出现的概率增大，以及在后续形成插塞时易发生插塞偏离预定位置而无法实现预定的电连接的问题，而本发明中在将封装材料覆盖所述第二芯片和所述衬底的正面之前，已经形成有插塞，在将封装材料覆盖所述第二芯片和所述衬底的正面之后，再进行减薄工艺，可以避免了由于先进行注塑成型工艺后制作插塞连接所产生的各种工艺问题(例如由于翘曲变形导致的插塞位置偏离电连接失败，以及翘曲问题对减薄工艺造成的负面影响)，进而提高了电性能。
在另一个示例中，将封装材料覆盖所述第二芯片和所述衬底的正面之前，并未在衬底中形成插塞时，可以先进行以下步骤：如图4A至图4C所示，对所述衬底100的背面进行减薄，该减薄停止于目标厚度；在所述衬底100中形成与所述第一芯片101电连接的插塞102，所述插塞102的端部从所述衬底100的背面露出。其中，减薄的方法可以参考前述的减薄方法，为避免重复，在此不做赘述，也可以通过前述示例中的插塞的形成方法形成所述插塞。
在另一个示例中，还可以在步骤二之前，也即将所述第二芯片设置在所述衬底上之前，进行以下步骤C1至C4：首先，执行步骤C1，如图4A至4B所示，对所述衬底100的背面进行减薄，减薄至目标厚度；接着，执行步骤C2，如图4C所示，提供支撑基底21，所述支撑基底21可以是本领域技术人员熟知的任何适合的基底，例如半导体衬底、玻璃基底、陶瓷基底等，将所述支撑基底21与所述衬底100的背面进行接合，该接合可以使用任何适合的接合方式，例如临时键合或者粘接等，例如使用键合胶层将支撑基底和衬底的背面接合，键合胶层可以是但不限于是有机高分子材料或可紫外变性的有机材料；接着，执行步骤C3，如图4D所示，在所述衬底100的正面放置所述第二芯片201，其中放置方法可以参阅前述步骤中的方法；最后，执行步骤C4，如图4E所示，去除所述支撑基底，根据所使用的接合方式选择适合的去除方法，例如，高温或者紫外照射的方式，使键合胶层变性失去粘性，从而将支撑基底剥离。其中，值得一提的是，该支撑基底的去除还可以在将封装材料覆盖所述第二芯片和所述衬底，以固定所述第二芯片的步骤之后进行。
值得一提的是，在所述步骤C1执行之前，也即在所述减薄之前，所述衬底中还具有与所述第一芯片电连接的插塞，所述插塞向衬底背面延伸的端部埋在所述背面之下，所述减薄之后，所述插塞的端部从所述衬底的背面露出。
也可以是，在将封装材料覆盖所述第二芯片和所述衬底之后，或者，在所述衬底的正面放置所述第二芯片之前，所述步骤C1的减薄之后，还包括：在所述衬底中形成与第一芯片电连接的插塞，所述插塞的端部从所述衬底的背面露出，例如如图4F所示，在将封装材料覆盖所述第二芯片和所述衬底之后，在所述衬底100中形成与第一芯片101电连接的插塞102，所述插塞102的端部从所述衬底100的背面露出。
在其他的一个示例中，还可以在所述衬底的背面放置所述第二芯片之前，进行以下步骤：如图3A至图3C所示，对所述衬底的背面进行减薄；在所述衬底中形成与所述第一芯片电连接的插塞，所述插塞的端部从所述衬底的背面露出。
值得一提的是，前述示例中所提及的减薄可以使用任何适合的工艺执行本步骤的减薄，例如机械研磨(grinding)工艺、化学机械研磨工艺或者刻蚀工艺等。
减薄后的衬底的厚度可以根据实际工艺进行合理设定，例如，减薄后的衬底100的厚度在10μm至100μm之间，也可以根据技术节点的不同，该厚度相应变化，在此不做具体限定。
其中，前述示例中所提及的插塞的形成方法可以使用任何适合的方法，也可以使用前述示例中的方法。
随后，执行步骤四，如图1D所示，所述衬底100上形成第一焊盘105，其中，所述第一焊盘105相对于所述第二芯片201位于所述衬底100另一面，并且所述第一焊盘105电连接所述插塞102。
在一个示例中，如图1D所示，在将封装材料覆盖所述第二芯片201和所述衬底之前，在所述减薄之后，并已经在衬底中形成有插塞102时，进行以下步骤：所述衬底上形成第一焊盘105，其中，所述第一焊盘105相对于所述第二芯片位于所述衬底另一面，并且所述第一焊盘105电连接所述插塞102，例如，如图1D所示，将所述第二芯片201设置在所述衬底100正面时，则所述第一焊盘105形成在所述衬底100的背面。
在另一个示例中，如图1D所示，还可以在所述将封装材料覆盖所述第二芯片201和所述衬底100以及所述减薄之后，并且所述衬底100中已经形成插塞102之后，执行步骤四，如图1D所示，所述衬底100上形成第一焊盘105，其中，所述第一焊盘105相对于所述第二芯片201位于所述衬底100另一面，并且所述第一焊盘105电连接所述插塞102。
可以使用任何适合的方法形成所述第一焊盘105，例如，形成焊盘材料层以覆盖衬底100，其中，可以使用物理气相沉积方法(PVD)、化学气相沉积方法(CVD)、溅射、电解电镀、无电极电镀工艺、或其它合适的金属沉积工艺形成所述焊盘材料层，再通过刻蚀的方法去除部分所述焊盘材料层，以形成多个间隔设置的第一焊盘105。
示例性地，每个第一焊盘105分别电连接一个所述插塞102，所述焊盘用于将第一芯片和第二芯片组成的器件结构引出与外部电路实现连接。
随后，执行步骤五，如图1E所示，形成钝化层106，以覆盖所述第一焊盘105以及所述衬底100。
示例性地，所述钝化层106的顶面高于所述第一焊盘105的顶面。所述钝化层的厚度可以是任意适合的厚度，在此不做具体限定。
示例性地，在沉积钝化层106后还可以选择性的对钝化层106的表面进行化学机械研磨，以获得平坦的表面。
接着，在所述第一焊盘105上方的所述钝化层106中形成开口107，所述开口107露出所述第一焊盘105的至少部分表面。
为了实现第一焊盘与外部电路的连接，需要露出第一焊盘表面的开口107，可以使用任何适合的方法形成所述开口107，在一个示例中，首先在钝化层106的表面形成图案化的掩膜层，例如光刻胶层，该图案化的掩膜层定义有开口的位置、形状和关键尺寸等，然后再以该图案化的掩膜层为掩膜，刻蚀露出的钝化层106，直到露出第二第一焊盘105的表面，以形成所述开口107，随后，将图案化的掩膜层去除，例如通过灰化或者湿法刻蚀的方法去除光刻胶材质的掩膜层。
至此，完成了对本发明的晶圆级系统封装方法的关键步骤的介绍，对于完整的方法还可能包括其他的步骤，例如封装完成后，还可以沿切割道对衬底进行切割工艺，以将集成在衬底上的多个芯片分割为各自独立的单元，每个单元均包括相接合的第一芯片和第二芯片，该单元形成一个可提供多种功能的系统或子系统，该功能取决于实际集成的芯片的功能。
综上所述，根据本发明的晶圆级系统封装方法，使晶圆级封装与系统集成方法相结合，同时实现了多种芯片的集成和在衬底上完成封装制造优势，在衬底上完成封装集成制程，具有大幅减小封装结构的面积、降低制造成本、优化电性能、批次制造等优势，可明显的降低工作量与设备的需求。并且预先在衬底上形成了插塞，避免了由于先进行注塑成型工艺后制作插塞连接所产生的各种工艺问题(例如由于翘曲变形导致的插塞位置偏离电连接失败，以及翘曲问题对减薄工艺造成的负面影响)，提高了器件的良率和性能。
实施例四
下面，参考图5A至图5E对本发明的晶圆级系统封装方法做详细描述。
本发明还提供一种前述实施例二中的晶圆级系统封装结构的制造方法，包括：
首先，执行步骤一，如图5A所示，提供具有多个第一芯片101的衬底100。该步骤一参考前述实施三中的描述，在此不再重复描述。
接着，执行步骤二，提供多个第二芯片，将所述第二芯片设置在所述衬底上，使至少其中一个第二芯片与至少其中一个所述第一芯片通过导电凸块电连接。
还可以将所述第二芯片201设置在所述衬底100的背面，此时可以先在衬底100中已经形成了插塞，可以使用前述实施三中的方法在所述衬底100中形成插塞102，示例性地，如图5A所示，所述衬底100中还具有与所述第一芯片101电连接的插塞102，所述插塞102向衬底100背面延伸的端部埋在所述背面之下，其中，在所述衬底的背面放置所述第二芯片之前，还包括：如图5B所示，对所述衬底100的背面进行减薄，直至露出所述插塞102。
随后，如图5C所示，提供多个第二芯片201，将所述第二芯片201设置在所述衬底100上，使至少其中一个第二芯片201与至少其中一个所述第一芯片101通过导电凸块104电连接，电连接的第一芯片101和第二芯片201具有重叠部分。
接着，执行步骤三，将封装材料覆盖所述第二芯片和所述衬底，以固定所述第二芯片。
在一个示例中，如图5D所示，所述衬底100具有正面和背面，所述封装层202覆盖所述背面，此时所述第二芯片201设置在所述衬底100的背面。
具体地形成封装层的方法，参考前述实施三，在此不做赘述。
随后，执行步骤四，如图5E所示，所述衬底100上形成第一焊盘105，其中，所述第一焊盘105相对于所述第二芯片201位于所述衬底100另一面，并且所述第一焊盘105电连接所述插塞102。
如图5E所示，将所述第二芯片201设置在所述衬底100背面时，则所述第一焊盘105形成在所述衬底100的正面。
随后，执行步骤五，继续如图5E所示，形成钝化层106，以覆盖所述第一焊盘105以及所述衬底100。
随后，在所述第一焊盘105上方的所述钝化层106中形成开口107，所述开口107露出所述第一焊盘105的至少部分表面。
值得一提的是，为了避免重复在本实施例中，并未对前述实施例三中所涉及的相同步骤进行赘述，但应当知道的是，前述实施例三中的相应步骤均可以适用于本实施例。
实施例五
本发明的另一实施例中还提供一种电子装置，所述电子装置包括将前述的晶圆级系统封装结构进行切割而形成的具有一定功能的电子器件。
本实施例的电子装置，可以是手机、平板电脑、笔记本电脑、上网本、游戏机、电视机、VCD、DVD、导航仪、数码相框、照相机、摄像机、录音笔、MP3、MP4、PSP等任何电子产品或设备，也可为任何包括电路的中间产品。本发明实施例的电子装置，由于使用了上述的晶圆级系统封装结构，因而具有更好的性能。
其中，图7示出移动电话手机的示例。移动电话手机300被设置有包括在外壳301中的显示部分302、操作按钮303、外部连接端口304、扬声器305、话筒306等。
作为示例，所述电子装置包括：形成有至少一个第一芯片的衬底，所述第一芯片利用半导体工艺在所述衬底上生长而成；内嵌有至少一个第二芯片的封装层，所述封装层覆盖所述衬底和所述第一芯片；至少其中一个所述第二芯片与至少其中一个所述第一芯片通过导电凸块电连接，电连接的第一芯片和第二芯片具有重叠部分。示例性地，所述衬底具有正面和背面，所述封装层覆盖所述正面或背面。示例性地，所述电子装置还包括：相对于所述封装层，位于所述衬底另一面的第一焊盘；插塞，电连接所述第一焊盘和所述第一芯片。示例性地，所述封装层为塑封层。示例性地，所述塑封层的材料为环氧树脂。示例性地，还包括：具有开口的钝化层，覆盖所述第一焊盘和所述衬底，所述开口暴露出所述第一焊盘。示例性地，还包括：还包括：第二焊盘，位于所述衬底正面，与所述第一芯片电连接。
本发明已经通过上述实施例进行了说明，但应当理解的是，上述实施例只是用于举例和说明的目的，而非意在将本发明限制于所描述的实施例范围内。此外本领域技术人员可以理解的是，本发明并不局限于上述实施例，根据本发明的教导还可以做出更多种的变型和修改，这些变型和修改均落在本发明所要求保护的范围以内。本发明的保护范围由附属的权利要求书及其等效范围所界定。

Claims (10)

1.一种晶圆级系统封装结构，其特征在于，包括：
形成有多个第一芯片的衬底，所述第一芯片利用半导体工艺在所述衬底上生长而成，所述衬底中还具有与所述第一芯片电连接的插塞，所述插塞贯穿所述第一芯片和所述衬底，所述插塞的端部埋在衬底中，所述第一芯片的表面还形成有多个间隔设置的第二焊盘，所述插塞与设置在所述第一芯片表面的至少一个所述第二焊盘电连接，所述第二焊盘设置在所述衬底中且与所述衬底面向封装层的一面的表面平齐；
内嵌有多个第二芯片的封装层，所述封装层覆盖所述衬底和所述第一芯片，所述封装层为塑封层；
至少其中一个所述第二芯片与至少其中一个所述第一芯片通过导电凸块电连接，电连接的第一芯片和第二芯片具有重叠部分，所述导电凸块位于所述第一芯片和所述第二芯片的所述重叠部分之间；
相对于所述封装层，位于所述衬底另一面的第一焊盘，所述第一焊盘与所述插塞电连接且位于所述插塞上，用于连接外部电路。
2.如权利要求1所述的封装结构，其特征在于，所述衬底具有正面和背面，所述封装层覆盖所述正面或背面。
3.如权利要求1所述的封装结构，其特征在于，所述导电凸块材料为锡或者铜。
4.如权利要求1所述的封装结构，其特征在于，所述塑封层的材料为环氧树脂。
5.如权利要求1所述的封装结构，其特征在于，还包括：具有开口的钝化层，覆盖所述第一焊盘和所述衬底，所述开口暴露出所述第一焊盘。
6.一种电子装置，其特征在于，包括：
形成有至少一个第一芯片的衬底，所述第一芯片利用半导体工艺在所述衬底上生长而成，所述衬底中还具有与所述第一芯片电连接的插塞，所述插塞贯穿所述第一芯片和所述衬底，所述插塞的端部埋在衬底中，所述第一芯片的表面还形成有多个间隔设置的第二焊盘，所述插塞与设置在所述第一芯片表面的至少一个所述第二焊盘电连接，所述第二焊盘设置在所述衬底中且与所述衬底面向封装层的一面的表面平齐；
内嵌有至少一个第二芯片的封装层，所述封装层覆盖所述衬底和所述第一芯片，所述封装层为塑封层；
至少其中一个所述第二芯片与至少其中一个所述第一芯片通过导电凸块电连接，电连接的第一芯片和第二芯片具有重叠部分，所述导电凸块位于所述第一芯片和所述第二芯片的所述重叠部分之间；
相对于所述封装层，位于所述衬底另一面的第一焊盘，所述第一焊盘与所述插塞电连接且位于所述插塞上，用于连接外部电路。
7.如权利要求6所述的电子装置，其特征在于，所述衬底具有正面和背面，所述封装层覆盖所述正面或背面。
8.如权利要求6所述的电子装置，其特征在于，所述导电凸块材料为锡或者铜。
9.如权利要求6所述的电子装置，其特征在于，所述塑封层的材料为环氧树脂。
10.如权利要求6所述的电子装置，其特征在于，还包括：具有开口的钝化层，覆盖所述第一焊盘和所述衬底，所述开口暴露出所述第一焊盘。
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