WO2019062238A1 - 一种晶圆级系统封装方法以及封装结构 - Google Patents

一种晶圆级系统封装方法以及封装结构 Download PDF

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Publication number
WO2019062238A1
WO2019062238A1 PCT/CN2018/093684 CN2018093684W WO2019062238A1 WO 2019062238 A1 WO2019062238 A1 WO 2019062238A1 CN 2018093684 W CN2018093684 W CN 2018093684W WO 2019062238 A1 WO2019062238 A1 WO 2019062238A1
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chip
substrate
chips
plug
electrically connected
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PCT/CN2018/093684
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English (en)
French (fr)
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刘孟彬
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中芯集成电路（宁波）有限公司
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Priority to US16/208,307 priority Critical patent/US10930617B2/en
Publication of WO2019062238A1 publication Critical patent/WO2019062238A1/zh

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Definitions

  • the present invention relates to the field of semiconductor technology, and in particular to a wafer level system packaging method and a package structure.
  • SiP System in Package
  • MEMS micro-electromechanical systems
  • optical components and other components into one unit to form a variety Functional systems or subsystems that allow heterogeneous IC integration are the best package integration technologies.
  • SoC System On Chip
  • wafer level package is a package integration process on the wafer, which greatly reduces the area of the package structure, reduces manufacturing costs, optimizes electrical performance, and manufactures batches. Other advantages can significantly reduce the workload and equipment needs.
  • an aspect of the present invention provides a wafer level system packaging method, including:
  • An encapsulation layer having a plurality of second chips embedded therein, the encapsulation layer covering the substrate and the first chip;
  • At least one of the second chips is electrically connected to at least one of the first chips, and the first chip and the second chip are mutually staggered and electrically connected by an electrical connection structure.
  • the electrical connection structure comprises:
  • the electrical connection structure further includes:
  • the electrical connection structure further includes:
  • the substrate has a front side and a back side, the encapsulation layer covering the front side or the back side.
  • the package structure further includes:
  • the front side of the second chip is bonded to the substrate, or the back side of the second chip is bonded to the substrate.
  • the second chip is disposed on the substrate by an adhesive layer.
  • the bonding layer comprises a chip connection film, a dry film or a photoresist.
  • the encapsulation layer is a plastic encapsulation layer.
  • Another aspect of the present invention provides a wafer level system packaging method, including:
  • the second chip is disposed on the substrate, and the second chip and the first chip are staggered;
  • An encapsulation material covers the second chip and the substrate to fix the second chip.
  • the method of forming an electrical connection structure includes:
  • Rewiring electrically connected to at least one of the first chips is formed on the substrate before the second chip is disposed on the substrate;
  • the second chip is placed on the substrate, and the first chip and the second chip are staggered from each other, and the two are electrically connected by the rewiring.
  • the method of disposing the second chip on the substrate comprises:
  • the second chip is placed on the conductive bump, and the first chip and the second chip are electrically connected by the conductive bump.
  • the substrate further has a plug electrically connected to the first chip, an end of the plug extending toward the back surface of the substrate is buried under the back surface, and the packaging material covers the first After the two chips and the front side of the substrate, the back side of the substrate is thinned until the plug is exposed; or
  • the back surface of the substrate is thinned, and then a plug electrically connected to the first chip is formed in the substrate, The end of the plug is exposed from the back side of the substrate.
  • the method of disposing the second chip on the substrate comprises:
  • the support substrate is removed.
  • the method of forming the electrical connection structure includes: forming a plug in the substrate, and the The plug corresponding to a chip electrically connects the first chip, and the plug corresponding to the second chip electrically connects the second chip.
  • the front side of the second chip is bonded to the substrate, or the back side of the second chip is bonded to the substrate.
  • the method of placing the second chip on the substrate comprises the steps of:
  • the second chip is bonded to the substrate by an adhesive layer.
  • the bonding layer comprises a chip connection film, a dry film or a photoresist.
  • the substrate has a front side and a back side, and the encapsulation layer covers the front side or the back side.
  • the wafer level system package structure of the present invention comprises a substrate formed with a plurality of first chips, the first chip is grown by a semiconductor process; an encapsulation layer of a plurality of second chips is embedded, and the encapsulation layer is covered The substrate and the first chip; at least one of the second chips is electrically connected to at least one of the first chips, and the first chip and the second chip grown on the substrate by a semiconductor process are integrated in the crystal
  • the area of the wafer-level system package structure can be greatly reduced and better electrical performance can be provided.
  • the wafer level system packaging method of the invention combines the wafer level packaging and the system packaging method, and realizes the advantages of integration of various chips and packaging manufacturing on the wafer, and can greatly reduce the area of the package structure, Reduce manufacturing costs, optimize electrical performance, batch manufacturing, etc., and significantly reduce the workload and equipment requirements, resulting in the yield of the final wafer-level system packaging method, and the performance of the resulting package structure.
  • FIGS. 1A to 1F are schematic cross-sectional views showing a structure obtained by sequentially performing a method according to an embodiment of the present invention
  • FIGS. 2A to 2E are schematic cross-sectional views showing the structure obtained by sequentially performing the method of another embodiment of the present invention.
  • FIG. 3 is a flow chart showing a wafer level system packaging method in accordance with an embodiment of the present invention.
  • Spatial relationship terms such as “under”, “below”, “below”, “under”, “above”, “above”, etc. This description may be used to describe the relationship of one element or feature shown in the figures to the other elements or features. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation shown in the figures. For example, if the device in the figures is turned “on” or “below” or “below” or “under” the element or feature is to be “on” the other element or feature. Thus, the exemplary terms “below” and “include” can include both the above and the The device may be otherwise oriented (rotated 90 degrees or other orientation) and the spatial descriptors used herein interpreted accordingly.
  • composition and/or “comprising”, when used in the specification, is used to determine the presence of the features, integers, steps, operations, components and/or components, but does not exclude one or more The presence or addition of features, integers, steps, operations, components, components, and/or groups.
  • the term “and/or” includes any and all combinations of the associated listed items.
  • Embodiments of the invention are described herein with reference to cross-section illustrations of schematic representations of the preferred embodiments (and intermediate structures) of the invention.
  • variations from the shapes shown can be expected as a result, for example, of manufacturing techniques and/or tolerances. Therefore, the embodiments of the present invention should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing.
  • an implanted region shown as a rectangle typically has rounded or curved features and/or implanted concentration gradients at its edges rather than a binary change from implanted to non-implanted regions.
  • a buried region formed by implantation can result in some implantation in the region between the buried region and the surface through which the implantation takes place.
  • the regions shown in the figures are, therefore, are not intended to limit the scope of the invention.
  • the present invention provides a wafer level system package structure, which mainly includes:
  • An encapsulation layer having a plurality of second chips embedded therein, the encapsulation layer covering the substrate and the first chip;
  • At least one of the second chips is electrically connected to at least one of the first chips, and the first chip and the second chip are mutually staggered and electrically connected by an electrical connection structure.
  • the wafer level system package structure of the present invention includes a substrate formed with a plurality of first chips, the first chip is grown by a semiconductor process; an encapsulation layer of a plurality of second chips is embedded, and the encapsulation layer is covered The substrate and the first chip; at least one of the second chips is electrically connected to at least one of the first chips, and the first chip and the second chip grown on the substrate by a semiconductor process are integrated in the crystal
  • the area of the wafer-level system package structure can be greatly reduced and better electrical performance can be provided.
  • a package structure of the present invention will be explained and explained below with reference to FIG. 1F.
  • the wafer level system package structure includes a substrate 100 formed with a plurality of first chips 101 grown using a semiconductor process.
  • the wafer level system package structure further includes an encapsulation layer 102 having a plurality of second chips 201 embedded therein, the encapsulation layer 102 covering the substrate 100 and the first chip 101.
  • At least one of the second chips 201 is electrically connected to at least one of the first chips 101.
  • the first chip 101 and the second chip 201 are staggered from each other, that is, the first chip 101 and the second chip 201 are staggered from each other in a plan view direction, the first chip. 101 and the second chip 201 are electrically connected by an electrical connection structure.
  • the electrical connection structure includes plugs 1031, 1032 located in the substrate 100 and electrically connected to the first chip 101 and the second chip 201, respectively.
  • the plug 1031 corresponding to the first chip 101 is electrically connected to the first chip 101
  • the plug 1032 corresponding to the second chip 201 is electrically connected to the first Two chips 201.
  • the front side of the second chip 201 is bonded to the substrate 100.
  • the back side of the second chip may be bonded to the substrate, and the specific bonding mode may be selected according to actual process requirements.
  • the second chip 201 is disposed on a substrate region outside the first chip 101 such that the second chip 201 and the first chip 101 are completely staggered.
  • the second chip 201 is disposed on the substrate 100 by an adhesive layer (not shown), that is, an adhesive layer is disposed between the second chip and the substrate ( Not shown), the second chip 201 is bonded to the substrate.
  • the encapsulation layer 102 covers the substrate 100 and the first chip 101 and encloses the second chip 201 within the encapsulation layer 102.
  • the substrate 100 has a front side and a back side, and the encapsulation layer 102 covers the front side.
  • the substrate has a front side and a back side, and the encapsulation layer covers the back side, that is, the encapsulation layer covers a surface of the substrate on which the second chip is disposed.
  • the top surface of the encapsulation layer 102 is higher than the top surface of the second chip 201.
  • the encapsulation layer 102 plays a fixed role on the second chip and can provide physical and electrical protection against external interference.
  • a plug 1032 corresponding to the second chip sequentially penetrates the substrate and the The bonding layer is electrically connected to the second chip 201, and the plug 1031 is electrically connected to the first chip 101 through a portion of the substrate.
  • the second chip and the second chip may also be formed by a plug corresponding to the second chip and a rewiring formed on the front surface of the substrate.
  • the first chip is electrically connected.
  • the wafer level system package structure further includes a pad 104 that is located on the other side of the substrate 100 with respect to the package layer 102.
  • the package structure further includes a passivation layer 105 having an opening 106 covering the pad 104 and the substrate 100, the opening 106 exposing the pad 104 .
  • the top surface of the passivation layer 105 is higher than the top surface of the pad 104.
  • the thickness of the passivation layer may be any suitable thickness, which is not specifically limited herein.
  • the substrate to which the present invention relates may be at least one of the following semiconductor materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs, or other III/V compound semiconductors, including these
  • the substrate 100 may also be other suitable substrate structures, and the substrate 100 may also be a single layer or include multiple layers (ie, two or more layers).
  • the chips mentioned in the present invention may be any one of semiconductor chips, which may include a memory, a logic circuit, a power device, a bipolar device, and a separate MOS transistor.
  • Active devices such as micro-electro-mechanical systems (MEMS), or even photovoltaic devices such as light-emitting diodes, can also be passive devices such as resistors, capacitors, and the like.
  • the first chip 101 is grown on the substrate by a semiconductor process, and the functions of the first chip are different, the semiconductor process used is different, the reliability is higher, and more processes can be saved.
  • the first chip 101 is simply shown in the form of a box, but it is conceivable that the structure of the first chip may include a plurality of constituent elements and rewiring of the first chip (ie, metal mutual And a structure, etc., wherein the metal interconnect structure may include a plurality of metal layers and contact holes electrically connecting adjacent metal layers, and a plurality of dielectric layers are formed on the substrate during the growth of the first chip.
  • the adjacent first chips 101 may be separated by a dielectric layer formed on the substrate to form a structure similar to that shown in FIG. 1F in which each of the first chips 101 is embedded in the surface of the substrate.
  • the material of the dielectric layer can be any suitable dielectric material well known to those skilled in the art including, but not limited to, SiO 2 , fluorocarbon (CF), carbon doped silicon oxide (SiOC), or carbonitriding. Silicon (SiCN) and so on.
  • the plurality of first chips 101 may have the same or different functions.
  • the plurality of first chips 101 may have the same or different sizes.
  • the actual number, function and size of the first chip 101 are determined by design requirements and are not limited.
  • the second chip 201 may be a different type of chip having a different function from the first chip 101, or may be the same chip.
  • the foregoing bonding layer may have adhesiveness on both surfaces, and one surface is bonded to the surface of the substrate 100, and one surface is bonded to the surface of the second chip 201 to bond the second chip.
  • a 201 is attached to the substrate to effect a physical connection between the chip to be integrated and the substrate.
  • the bonding layer may be formed only on a region where the substrate is intended to be used to fix the second chip, or may be over the entire substrate.
  • the bonding layer may be an organic film, and the organic film may include various organic film layers, such as a die attach film (DAF), a dry film, or a photoresist.
  • DAF die attach film
  • the thickness of the bonding layer is set as needed, and the number of layers of the bonding layer is not limited to one layer, and two or more layers may be provided.
  • the die attach film may be any suitable material well known to those skilled in the art, and may be, for example, a resin glue, particularly a highly thermally conductive resin glue.
  • the dry film is a polymer compound which, after being irradiated by ultraviolet rays, can generate a polymerization reaction to form a stable substance attached to the surface to be bonded of the substrate and the second chip, and the dry film can include three layers, one The layer is a PE protective film, the middle is a dry film layer, the other layer is a PET protective layer, and the dry film layer is located between the PE protective film and the PET protective layer.
  • the thickness of the bonding layer can be appropriately set according to the needs of the device, and is not particularly limited herein, as long as any thickness capable of ensuring that the second chip is firmly fixed on the substrate can be applied to the present invention.
  • the aforementioned encapsulation layer 102 can be any suitable encapsulation material well known to those skilled in the art, for example, the encapsulation layer 102 is a plastic encapsulation layer, and the plastic encapsulation layer includes a thermosetting resin that can be formed during the molding process.
  • the plastic sealing layer can include phenolic resin, urea-formaldehyde resin, melamine-formaldehyde resin, epoxy resin, unsaturated resin, polyurethane, polyacyl At least one of a thermosetting resin such as an imide, wherein an epoxy resin is preferably used as the plastic sealing layer, wherein the epoxy resin may be an epoxy resin having a filler material or a filler-free material, and various additives (for example, , a curing agent, a modifier, a mold release agent, a thermochromic agent, a flame retardant, etc.), for example, a phenol resin as a curing agent, and a solid particle (for example, a silicon fine powder) or the like as a filler.
  • the plastic seal layer may also include silica gel.
  • the plugs 1031, 1032 can be any suitable metal plug or silicon plug (ie, through silicon via, TSV) well known to those skilled in the art, and the material of the metal plug can include, but is not limited to, Ag, Au, Cu, Pd. At least one of Cr, Mo, Ti, Ta, Sn, W, and Al, and the material of the silicon plug may include doped polysilicon or undoped polysilicon or the like.
  • the pads 104 are electrically connected to corresponding plugs.
  • the material of the pad 104 may be any suitable metal material including, but not limited to, at least one of Ag, Au, Cu, Pd, Cr, Mo, Ti, Ta, Sn, W, and Al.
  • the material of the passivation layer 105 may use any suitable insulating material, for example, the passivation layer 105 uses an inorganic insulating layer such as a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer, which may be deposited by chemical vapor deposition,
  • the passivation layer 105 is deposited by a deposition method such as physical vapor deposition or atomic layer deposition; an insulating layer such as a layer containing polyvinylphenol, polyimide, or siloxane or the like may also be used.
  • Polyvinylphenol, polyimide, or siloxane can be effectively formed by a droplet discharge method, a printing method, or a spin coating method.
  • Siloxanes can be classified according to their structure into silica glass, alkylsiloxane polymers, alkylsilsesquioxane polymers, silsesquioxane hydride polymers, An alkylsilsesquioxane hydride polymer or the like.
  • the insulating material may be formed of a material including a polymer having a Si-N bond (polysilazane). Further, these films may be laminated to form a passivation layer.
  • the present invention integrates the first chip and the second chip in a wafer level system package structure, which can greatly reduce the area of the wafer level system package structure and provide better electrical performance, and thus the present invention
  • the wafer level system package structure has higher performance.
  • the present invention also provides a wafer level system package structure.
  • a package structure of the present invention will be explained and explained below with reference to FIG. 2E.
  • the wafer level system package structure of the present invention includes a substrate 300 formed with a plurality of first chips 301 grown on the substrate 300 using a semiconductor process.
  • the wafer level system package structure of the present invention further includes an encapsulation layer 402 having a plurality of second chips 401 embedded therein, the encapsulation layer 402 covering the substrate 300 and the first chip 301.
  • the substrate 300 has a front side and a back side, and the encapsulation layer 402 covers the front side.
  • the substrate has a front side and a back side, and the encapsulation layer covers the back side, that is, the encapsulation layer covers a surface of the substrate on which the second chip is disposed.
  • the wafer level system package structure of the present invention further includes: at least one of the second chips 401 is electrically connected to at least one of the first chips 301, and the first chip 301 and the second chip 401 They are staggered from each other and electrically connected through an electrical connection structure.
  • the electrical connection structure includes a plug 302 located in the substrate 300, electrically connected to the first chip 301, and located between the first chip 301 and the second chip 401 or the plug 302 Rewiring of the top (not shown).
  • At least one plug 302 is disposed in at least one of the plurality of first chips 301, the plug 302 penetrating the first chip 301, for example, the plug 302 runs through the first A chip 301 is electrically connected to the first pad 305 formed on the back surface of the substrate through the front and back surfaces of the substrate.
  • the plug penetrates the first chip 301 and penetrates the front and back sides of the substrate to be electrically connected to the first pad 305 formed on the front surface of the substrate, depending on the actual package.
  • the structure is properly set.
  • the plug 302 is disposed in an edge region of the first chip 301, or other suitable region capable of electrically connecting to the first chip 301 without affecting the functional realization of the first chip 301.
  • the electrical connection structure further includes: a conductive bump 304 formed between the rewiring and the second chip 401.
  • the conductive bumps 304 are arranged in an array.
  • the conductive bumps 304 may be solder balls, or copper pillars, or gold bumps, or alloy bumps, or the like, or other suitable conductive bump structures.
  • the conductive bumps 304 mainly include a metal material including, but not limited to, at least one of tin, copper, nickel, silver tin copper alloy, or tin-based alloy.
  • the conductive bumps may also be disposed on the substrate, but the positions thereof are offset from the position of the first chip, and the conductive bumps are electrically connected to the first chip.
  • Wiring, the second chip is disposed on the conductive bump, and the first chip and the second chip are electrically connected by the conductive bump and the rewiring.
  • the package structure further includes a second pad 303 located on the front side of the substrate 300 and electrically connected to the first chip 301.
  • the second pad 303 may also be disposed between the second chip 401 and the substrate 300, and second The pad 303 may electrically connect the rewiring electrically connected to the first chip 301, and the second pad 303 realizes the electrical connection of the first chip 301 and the second chip 401.
  • the conductive bumps 304 are disposed on the second pads 303 and are electrically connected to the second pads.
  • an under bump metallization (UBM) structure (not shown) may also be disposed between the second pad and the conductive bump 304, and the under bump metallization (UBM) structure may be adhered.
  • the layer, the barrier layer, and the multi-layer metal of the seed or wetting layer are stacked.
  • the UBM structure helps prevent diffusion between the bumps and integrated circuits of the multi-chip semiconductor device while providing a low resistance electrical connection.
  • the package structure further includes a first pad 305 on the other side of the substrate 300 with respect to the encapsulation layer 402, the first pad 305 electrically connecting the corresponding plug 302.
  • the encapsulation layer 402 covers the front side of the substrate 300, then the first pad 305 is disposed on the back side of the substrate 300, or the encapsulation layer 402 covers the substrate 300. On the back side, the first pad 305 is disposed on the front side of the substrate 300.
  • the package structure further includes a passivation layer 306 having an opening 307 covering the first pad 305 and the substrate 300, the opening 307 exposing the first pad 305.
  • the present invention provides an improved wafer level system packaging method, as shown in FIG. 3, which mainly includes the following steps:
  • Step S1 providing a substrate having a plurality of first chips, wherein the first chip is grown on the substrate by a semiconductor process;
  • Step S2 providing a plurality of second chips, the second chip is disposed on the substrate, and the second chip and the first chip are staggered;
  • Step S3 forming an electrical connection structure, wherein at least one of the second chips is electrically connected to at least one of the first chips;
  • Step S4 covering the second chip and the substrate with an encapsulation material to fix the second chip.
  • the wafer level system packaging method of the present invention combines wafer level packaging and system packaging method, and realizes integration of various chips and packaging manufacturing advantages on a wafer, and greatly reduces the area of the package structure and reduces Manufacturing cost, optimized electrical performance, batch manufacturing and other advantages can significantly reduce the workload and equipment requirements, and improve the efficiency and yield of the package.
  • the package structure obtained by the wafer level system packaging method of the present invention also has higher performance and yield.
  • FIGS. 1A to 1F are schematic cross-sectional views showing the structure obtained by sequentially performing the method of one embodiment of the present invention.
  • the packaging method can be used for the preparation of the package structure in the first embodiment.
  • the wafer level system packaging method of the present invention includes the following steps:
  • step one is performed, as shown in FIG. 1A, a substrate 100 having a plurality of first chips 101 is provided.
  • the descriptions of the specific structure and the like of the first chip 101 and the substrate 100 are referred to the description in the first embodiment, and are not described herein.
  • step 2 is performed to continue, as shown in FIG. 1A, a plurality of second chips 201 are provided, the second chip 201 is disposed on the substrate 100, and the second chip 201 and the first chip 101 are Staggered.
  • the type and the like of the second chip 201 refer to the foregoing first embodiment, and no further details are provided herein.
  • the second chip 201 may be a different type of chip having a different function from the first chip 101, or may be the same chip.
  • the front side of the second chip 201 is bonded to the substrate 100.
  • the back surface of the second chip and the substrate are bonded, and the specific bonding manner can be selected according to actual process requirements.
  • the second chip 201 is disposed in a region of the substrate outside the first chip 101, so that the second chip 201 and the first chip 101 are completely staggered to facilitate the execution of the subsequent plugging process.
  • a method of fixing the second chip to the substrate any suitable method may be used, and in one example, a method of fixing the second chip 201 to the substrate 100 includes the following steps: An adhesive layer (not shown) is formed on the substrate 100 to bond the second chip 201 to the substrate.
  • the two surfaces of the bonding layer are adhesive, one surface is bonded to the surface of the substrate 100, and one surface is bonded to the surface of the second chip 201 to fix the second chip 201 to the substrate.
  • the physical connection between the chip to be integrated and the substrate is implemented.
  • the bonding layer may be formed only in a region where the substrate is intended to be used to fix the second chip, or may cover the entire substrate.
  • steps A1 to A4 may also be included before the second chip is disposed on the substrate:
  • step A1 is performed to thin the back surface of the substrate; the thinning of this step may be performed using any suitable process, such as a mechanical grinding process, a chemical mechanical polishing process, or an etching process.
  • the thickness of the thinned substrate can be appropriately set according to an actual process.
  • the thickness of the thinned substrate 100 is between 10 ⁇ m and 100 ⁇ m, and the thickness may be changed according to different technical nodes. No specific restrictions.
  • step A2 is performed to provide a support substrate for bonding the support substrate to the back surface of the substrate;
  • the support substrate may be any suitable substrate known to those skilled in the art, such as a semiconductor substrate, a glass substrate, a ceramic substrate or the like, joining the support substrate to the back surface of the substrate, the bonding may be performed using any suitable bonding means such as temporary bonding or bonding, etc., for example, using a bonding layer to support the substrate and the substrate
  • the back bonding, the bonding layer may be, but not limited to, an organic polymer material or an ultraviolet-densable organic material.
  • step A3 is performed to place the second chip on the front side of the substrate;
  • the method of placing the second chip may be any suitable method well known to those skilled in the art, preferably using the method described in the foregoing steps.
  • the second chip is placed onto the substrate, for example by bonding.
  • step A4 is performed to remove the support substrate.
  • the support substrate is removed, and a suitable removal method is selected according to the bonding method used, for example, high temperature or ultraviolet irradiation, the bond layer is denatured and loses viscosity, thereby peeling off the support substrate.
  • the removal of the support substrate can also be performed after the step of covering the second chip and the substrate with the encapsulation material to fix the second chip.
  • step three is performed. As shown in FIG. 1B, the encapsulation material covers the second chip 201 and the substrate 100 to fix the second chip 201.
  • the encapsulating material may be covered by the second chip 201 and the substrate 100 by an injection molding process, which may be a hot press molding process, or other suitable injection molding process.
  • the injection molding process uses a liquid molding compound or a solid molding compound, wherein a liquid molding compound is preferably used so that the liquid molding compound can be filled in adjacent conductive before curing.
  • a liquid molding compound is preferably used so that the liquid molding compound can be filled in adjacent conductive before curing.
  • the adhesion between the first chip and the second chip is increased, and the stability of the package is improved.
  • the step of covering the second chip and the substrate with an encapsulation material includes: providing a mold, placing the substrate in the mold, wherein the mold can be any suitable mold, Here, it is not specifically limited, and then, a molten molding compound is injected into the mold, a liquid molding compound is uniformly applied to the entire substrate, the second chip 201 is wrapped, and then, a curing treatment is performed to make The molding compound is solidified to form a plastic sealing layer as the encapsulating layer 102.
  • the curing may be a thermal curing process, and a specific curing method is appropriately selected according to the actually used molding compound, and finally demolding is performed.
  • the top surface of the encapsulation layer 102 is higher than the top surface of the second chip 201, and the encapsulation layer 102 provides physical and electrical protection to the chip from external interference.
  • the substrate 100 has a front side and a back side, and the encapsulation layer 102 covers the front side, at which time the second chip is disposed on the front side of the substrate.
  • the substrate has a front side and a back side, and the encapsulation layer 102 covers the back side, at which time the second chip 201 is disposed on the back side of the substrate 100.
  • the method further includes the step of thinning the back surface of the substrate, the thinning step is usually The process of thinning the back side of the substrate is not performed before the second chip is placed on the substrate.
  • step four is performed to form an electrical connection structure, such that at least one of the second chips is electrically connected to at least one of the first chips.
  • plugs 1031, 1032 are formed in the substrate, and the plugs 1031 corresponding to the first chip 101 are electrically connected to the first chip 101, and The plug 1032 corresponding to the second chip 201 is electrically connected to the second chip 201, and the ends of the plugs 1031, 1032 are exposed from the back surface of the substrate 100.
  • the plug 1031 is used to implement electrical connection between the first chip 101 and an external circuit
  • the plug 1032 is used to implement electrical connection between the second chip 201 and an external circuit, although only one is shown in FIG. 1D.
  • the first chip 101 is electrically connected to one of the plugs 1031
  • the second chip 201 is electrically connected to one of the plugs 1032.
  • the plug 1031 and the plug 1032 can be formed using any suitable method known to those skilled in the art, and in one example, when the second chip is bonded to the substrate by an adhesive layer, the plug 1031 is formed. And the plug 1032 includes the steps of first forming a patterned mask layer (not shown) on the other side of the substrate with respect to the encapsulation layer, the plug being defined in the patterned mask layer
  • the mask layer may include any one of several mask materials, including but not limited to: a hard mask material and a photoresist mask material. Preferably, the mask layer uses a photoresist.
  • the mask material can be patterned by spin-coating a photoresist mask material on the back side of the substrate, and then patterning the photoresist mask material by using a photolithography process to form a patterned photoresist mask material.
  • the position and critical dimension of the plug and plug to be formed are defined in the photoresist mask material, and then the portion of the substrate 100 is etched by using the patterned mask layer as a mask until the exposed portion is exposed.
  • etching process may be a wet etching or a dry etching process, wherein a dry etching process is preferably used,
  • the etching includes, but is not limited to, reactive ion etching (RIE), ion beam etching, plasma etching, or laser cutting, followed by removing the patterned mask layer, for example, using ashing to remove the photoresist.
  • RIE reactive ion etching
  • plasma etching plasma etching
  • laser cutting followed by removing the patterned mask layer, for example, using ashing to remove the photoresist.
  • a conductive material for example, a metal material or polysilicon
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • the conductive material is formed by sputtering, electrolytic plating, electroless plating, or other suitable metal deposition process.
  • the bonding layer is usually an organic thin film
  • the general substrate may include various inorganic film layers, for example, including a semiconductor substrate and a dielectric layer, wherein the dielectric layer is, for example, a silicon oxide layer or a silicon nitride layer, and
  • the number of layers of the inorganic film layer is not limited to one layer, and two or more layers may be used.
  • the substrate may be etched by dry etching using, for example, an etching method using a fluorine-containing gas such as CF 4 as an etching gas, and then the bonding layer (that is, the organic film) is etched to etch the organic film.
  • a fluorine-containing gas such as CF 4
  • Oxygen or argon is used as the etching gas.
  • the plug 1031 extends from the back surface of the substrate 100 to the front surface until it is electrically connected to the corresponding first chip 101, and the plug 1032 extends from the back surface of the substrate 100 to the front side. Until the second chip 201 corresponding thereto is electrically connected.
  • the back surface of the substrate may be thinned first, then the second chip is placed on the back side of the substrate, and then the packaging material is covered. a second chip and the substrate, and then forming a plug in the substrate, the plug corresponding to the first chip electrically connecting the first chip, and the second The plug corresponding to the chip is electrically connected to the second chip.
  • step B1 is performed, as shown in FIG. 1E, a pad 104 is formed on the substrate, wherein The pad 104 is located on the other side of the substrate 100 with respect to the second chip 201, and the pad 104 is electrically connected to the plugs 1031, 1032.
  • the pads 104 electrically connect at least one of the plugs 1031 and/or at least one of the plugs 1032.
  • the pad 104 is electrically connected to the plug to achieve electrical connection of the first chip and the second chip.
  • the pads are used to connect the first chip and the second chip to the external circuit, and one of the pads 104 may be disposed on each of the plugs 1031 and the plugs 1032 to implement
  • the pad 104 is electrically connected to each chip independently, or a pad 104 may be electrically connected to the plurality of plugs 1031, and one pad 104 is electrically connected to the plurality of plugs 1032, or may be
  • One pad 104 electrically connects at least one of the plugs 1031 and at least one of the plugs 1032 to achieve more functional connections.
  • the pad 104 may be formed using any suitable method, for example, forming a pad material layer to cover the back surface of the substrate 100, wherein physical vapor deposition (PVD), chemical vapor deposition (CVD), sputtering may be used. Forming the pad material layer by electrolytic plating, electroless plating, or other suitable metal deposition process, and removing a portion of the pad material layer by etching to form the pad 104, adjacent to The pads 104 are spaced apart from each other.
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • sputtering may be used.
  • step B2 is performed, as shown in FIG. 1F, a passivation layer 105 is formed to cover the pad 104 and the substrate 100.
  • the top surface of the passivation layer 105 is higher than the top surface of the pad 104.
  • the thickness of the passivation layer may be any suitable thickness, which is not specifically limited herein.
  • the surface of the passivation layer 105 can also be selectively chemically ground after depositing the passivation layer 105 to obtain a flat surface.
  • step B3 is performed to continue, as shown in FIG. 1F, an opening 106 is formed in the passivation layer 105 above each of the pads 104, the opening 106 exposing at least a portion of the surface of the pad 104.
  • the opening 106 of the pad surface which may be formed using any suitable method, in one example, first forming a patterned mask on the surface of the passivation layer 105.
  • a layer such as a photoresist layer
  • the patterned mask layer defines the position, shape, and critical dimension of the opening
  • the exposed passivation layer 105 is etched by using the patterned mask layer as a mask.
  • the surface of the pad 104 is exposed until the opening 106 is formed, and then the patterned mask layer is removed, for example, by a ashing or wet etching method to remove the mask layer of the photoresist material.
  • the substrate may be cut along the scribe line to integrate
  • the plurality of chips on the substrate are divided into separate units, for example, each unit includes a first chip and a second chip that are joined, and the unit forms a system or subsystem that provides multiple functions, depending on the function.
  • the functionality of the actual integrated chip is not limited to, but not limited to, but not limited to, but not limited to, but not limited to, but not limited to, but not limited to, but not limited to the semiconductor chip.
  • the wafer level system packaging method combines a wafer level package and a system package method, and simultaneously realizes integration of a plurality of chips and completes package manufacturing advantages on a substrate, on a substrate. Completing the package integration process, which has the advantages of greatly reducing the area of the package structure, reducing the manufacturing cost, optimizing the electrical performance, and batch manufacturing, can significantly reduce the workload and equipment requirements, and improve the efficiency, yield and performance of the package.
  • the present invention also provides a method for fabricating a wafer level system package structure according to the second embodiment.
  • the wafer level system package method of the present invention will be explained and explained in detail below with reference to FIGS. 2A to 2E.
  • step one is performed, as shown in FIG. 2A, a substrate 300 having a plurality of first chips 301 grown using a semiconductor process.
  • the substrate 300 before the back side of the substrate is thinned, the substrate 300 further has a plug 302 electrically connected to the first chip 301, the plug 302 extending toward the back of the substrate 300.
  • the ends are buried under the back side, that is, the ends of the plugs 302 are buried in the substrate 300.
  • the plug 302 is disposed in an edge region of the first chip 301, or other suitable region capable of electrically connecting to the first chip 301 without affecting the functional realization of the first chip 301.
  • a second pad 303 is formed on a front surface of the substrate, the second pad 303 is electrically connected to the first chip 301, wherein the second pad 303 is disposed in the first a surface of a chip 301, and a portion of the second pad 303 may be disposed on the surface of the plug 302 to be electrically connected to the plug 302, and there is a gap between the adjacent second pads 303 .
  • the second pad 303 may be formed using any suitable method.
  • the pad material layer may be formed by a deposition method including, but not limited to, a physical vapor deposition method or a chemical vapor deposition method to cover the front surface of the substrate, and then engraved The etch method removes a portion of the pad material layer to form a plurality of spaced apart second pads 303.
  • step 2 is performed.
  • a plurality of second chips 401 are provided, the second chip 401 is disposed on the substrate, and the second chip 401 and the first chip 301 are staggered.
  • an electrical connection structure is formed such that at least one of the second chips is electrically connected to at least one of the first chips.
  • the method of forming an electrical connection structure includes steps C1 through C2:
  • Step C1 a rewiring (not shown) electrically connected to at least one of the first chips 301 is formed on the substrate 300 before the second chip is placed on the substrate, and those skilled in the art may be used.
  • a well-known method forms the rewiring layer and will not be described herein.
  • step C2 the second chip 401 is placed on the substrate 300, and the first chip and the second chip are staggered from each other, and the two are electrically connected through the rewiring.
  • the rewiring is formed on top of the plug.
  • the electrical connection structure for electrically connecting at least one of the second chips to at least one of the first chips comprises the aforementioned plug 302 and rewiring or the like.
  • the method of placing the second chip on the substrate comprises steps D1 and D2:
  • Step D1 forming at least one conductive bump on the rewiring
  • the conductive bumps 304 may be formed by any suitable method.
  • the solder balls eg, solder balls
  • the solder balls may be placed in at least one of the solder balls by a ball placement process.
  • the ball placement process refers to matching the selected pads
  • the solder ball is placed on the pad. This process is called ball planting.
  • the ball planting process can be used for artificial ball or ball planting.
  • the ball placement process may be to cover the surface of the first chip 301 with a ball net, place the solder ball on the ball net, and pass the solder ball from the ball net.
  • the holes are adhered to the surface of the first chip.
  • the solder balls are melted to be electrically connected to the first chip, and when the second pads 303 are provided, they are electrically connected to the second pads 303.
  • the reflow soldering temperature ranges from 200 ° C to 260 ° C, and may be other suitable temperatures.
  • step D2 the second chip 401 is placed on the conductive bump 304, and the first chip 301 and the second chip 401 are electrically connected through the conductive bump 304.
  • a second pad 303 may be formed between the conductive bump 304 and the rewiring.
  • the solder paste may be deposited on the first chip (especially on the second pad 303) by screen printing, and the second chip is correspondingly disposed on the substrate, and then reflow soldered to The electrical connection of the first chip and the second chip is achieved.
  • step three is performed. As shown in FIG. 2B, the encapsulation material covers the second chip 401 and the substrate 300 to fix the second chip 401.
  • the encapsulating material may be covered by the second chip 401 and the substrate 300 by an injection molding process, which may be a hot press molding process, or other suitable injection molding process.
  • the substrate 300 has a front side and a back side, and the encapsulation layer 402 covers the front side, at which time the second chip is disposed on the front side of the substrate.
  • the substrate has a front side and a back side, and the encapsulation layer covers the back side, at which time the second chip is disposed on the back side of the substrate.
  • the substrate 300 further has a plug 302 electrically connected to the first chip 301, and the plug 302 is buried at the end of the back surface of the substrate 300.
  • the encapsulation material covers the second chip 401 and the front surface of the substrate 200, the back surface of the substrate 300 is further thinned until the plug 302 is exposed.
  • the thinning can also etch the plug until the thickness of the substrate reaches the target thickness.
  • the encapsulation method of the plug is performed, since the plastic sealing layer is usually made of an organic material, and the substrate is usually an inorganic material (for example, silicon).
  • the plastic sealing layer is usually made of an organic material
  • the substrate is usually an inorganic material (for example, silicon).
  • the materials are different, the thermal expansion coefficients are also inconsistent, and it is easy to cause the package structure to warp and deform, thereby affecting the operability and yield of subsequent processes such as grinding, and allowing the robot to transfer crystals between different processes.
  • the thinning process can avoid various process problems caused by the plug connection after the injection molding process is first performed (for example, due to warpage deformation) Positional deviation electrical plug connection fails, and the negative impact on warpage problems caused by the thinning process), thereby improving the electrical performance.
  • the following steps may be performed: subtracting the back surface of the substrate Thin, the thinning stops at the target thickness; a plug electrically connected to the first chip is formed in the substrate, and an end of the plug is exposed from a back surface of the substrate.
  • the plug may be formed by the plug forming method in the foregoing example.
  • step E1 is performed to perform the back surface of the substrate. Thinning, thinning to target thickness; then, performing step E2 to provide a support substrate, then performing step E3 to place the second chip on the front side of the substrate; finally, performing step E4 to remove the support substrate.
  • the removal of the support substrate can also be performed after the step of covering the second chip and the substrate with the encapsulation material to fix the second chip.
  • the substrate before the step E1 is performed, that is, before the thinning, the substrate further has a plug electrically connected to the first chip, the plug is facing the back of the substrate. An extended end is buried under the back surface, and after the thinning, the end of the plug is exposed from the back side of the substrate.
  • the thinning of the step E1 may further include: after the encapsulation of the second chip and the substrate, or before the second chip is placed on the front surface of the substrate, the method further includes: A plug electrically connected to the first chip is formed in the substrate, and an end of the plug is exposed from a back surface of the substrate.
  • the second chip may also be disposed on the back surface of the substrate.
  • a plug may be formed in the substrate, for example, the substrate 300 further has a plug 302 electrically connected to the first chip 301, the end of the plug 302 extending toward the back surface of the substrate 300 is buried under the back surface, wherein before the second chip is placed on the back side of the substrate, The method further includes: thinning the back surface of the substrate until the plug is exposed.
  • the second chip may also be placed on the back side of the substrate, and the following steps are performed: thinning the back side of the substrate; forming the first in the substrate A plug electrically connected to the chip, the end of the plug being exposed from the back side of the substrate.
  • the thinning mentioned in the foregoing examples can perform the thinning of this step using any suitable process, such as a mechanical grinding process, a chemical mechanical grinding process, or an etching process.
  • the thickness of the thinned substrate can be appropriately set according to an actual process.
  • the thickness of the thinned substrate 300 is between 10 ⁇ m and 100 ⁇ m, and the thickness can be changed according to different technical nodes. No specific restrictions.
  • the method of forming the plug mentioned in the foregoing examples may use any suitable method, and the method in the foregoing examples may also be used.
  • a first pad 305 is formed on the substrate 300, wherein the first pad 305 is located on the substrate with respect to the second chip 401 The other side of the 300, and the first pad 305 is electrically connected to the plug 302.
  • a passivation layer 306 is formed to cover the first pad 305 and the substrate 300.
  • an opening 307 is formed in the passivation layer 306 above each of the first pads 305, the opening 307 exposing the first pad 305.
  • the substrate may be cut along the scribe line to integrate
  • the plurality of chips on the substrate are divided into separate units, for example, each unit includes a first chip and a second chip that are joined, and the unit forms a system or subsystem that provides multiple functions, depending on the function.
  • the functionality of the actual integrated chip is not limited to, but not limited to, but not limited to, but not limited to, but not limited to, but not limited to, but not limited to, but not limited to the semiconductor chip.
  • the wafer level system packaging method combines a wafer level package and a system package method, and simultaneously realizes integration of a plurality of chips and completes package manufacturing advantages on a substrate, on a substrate. Completing the package integration process, which has the advantages of greatly reducing the area of the package structure, reducing the manufacturing cost, optimizing the electrical performance, and batch manufacturing, can significantly reduce the workload and equipment requirements, and improve the efficiency, yield and performance of the package.

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Abstract

本发明提供一种晶圆级系统封装方法以及封装结构，所述封装结构包括：形成有多个第一芯片的衬底，所述第一芯片利用半导体工艺生长而成；内嵌有多个第二芯片的封装层，所述封装层覆盖所述衬底和所述第一芯片；至少其中一个所述第二芯片与至少其中一个所述第一芯片电连接，所述第一芯片和所述第二芯片相互错开，通过电连接结构电连接。本发明的晶圆级系统封装方法，使用晶圆级封装和系统封装方法相结合，同时实现了多种芯片的集成和在晶圆上完成封装制造的优势。

Description

一种晶圆级系统封装方法以及封装结构
说明书
技术领域
本发明涉及半导体技术领域，具体而言涉及一种晶圆级系统封装方法以及封装结构。
背景技术
系统封装(System in Package，简称SiP)将多个不同功能的有源元件，以及无源元件、微机电系统(MEMS)、光学元件等其他元件，组合到一个单元中，形成一个可提供多种功能的系统或子系统，允许异质IC集成，是最好的封装集成技术。相比于片上系统(System On Chip，简称SoC)封装，SiP集成相对简单，设计周期和面市周期更短，成本较低，可以实现更复杂的系统。
与传统的SiP相比，晶圆级系统封装(wafer level package,简称WLP)是在晶圆上完成封装集成制程，具有大幅减小封装结构的面积、降低制造成本、优化电性能、批次制造等优势，可明显的降低工作量与设备的需求。
鉴于晶圆级系统封装的显著优势，如何能够更好的实现晶圆级系统封装一直是业界内研究的热点。
发明内容
在发明内容部分中引入了一系列简化形式的概念，这将在具体实施方式部分中进一步详细说明。本发明的发明内容部分并不意味着要试图限定出所要求保护的技术方案的关键特征和必要技术特征，更不意味着试图确定所要求保护的技术方案的保护范围。
针对目前存在的问题，本发明一方面提供一种晶圆级系统封装方法，包括：
形成有多个第一芯片的衬底，所述第一芯片利用半导体工艺在所述衬底上生长而成；
内嵌有多个第二芯片的封装层，所述封装层覆盖所述衬底和所述 第一芯片；
至少其中一个所述第二芯片与至少其中一个所述第一芯片电连接，所述第一芯片和所述第二芯片相互错开，通过电连接结构电连接。
示例性地，所述电连接结构包括：
位于所述衬底中与所述第一芯片电连接的插塞。
示例性地，所述电连接结构还包括：
位于第一芯片和第二芯片之间或所述插塞顶部的再布线。
示例性地，所述电连接结构还包括：
形成在所述再布线和所述第二芯片之间的导电凸块。
示例性地，所述衬底具有正面和背面，所述封装层覆盖所述正面或背面。
示例性地，所述封装结构还包括：
相对于所述封装层，位于所述衬底另一面的焊盘，所述焊盘电连接相应的所述插塞。
示例性地，所述第二芯片的正面和所述衬底接合，或者，所述第二芯片的背面和所述衬底接合。
示例性地，所述第二芯片通过粘接层设置在所述衬底上。
示例性地，所述粘接层包括芯片连接薄膜、干膜或光阻。
示例性地，所述封装层为塑封层。
本发明再一方面还提供一种晶圆级系统封装方法，包括：
提供具有多个第一芯片的衬底，所述第一芯片利用半导体工艺在所述衬底上生长而成；
提供多个第二芯片，将所述第二芯片设置在所述衬底上，所述第二芯片和所述第一芯片错开；
形成电连接结构，使至少其中一个所述第二芯片与至少其中一个所述第一芯片电连接；
将封装材料覆盖所述第二芯片和所述衬底，以固定所述第二芯片。
示例性地，所述形成电连接结构的方法包括：
在将所述第二芯片设置在所述衬底上之前，在所述衬底上形成与至少其中一个所述第一芯片电连接的再布线；
将所述第二芯片放置在所述衬底上，并使所述第一芯片和所述第二芯片相互错开，二者通过所述再布线电连接。
示例性地，将所述第二芯片设置在所述衬底上的方法包括：
在所述再布线上形成至少一个导电凸块；
将所述第二芯片放置在所述导电凸块上，所述第一芯片和第二芯片通过所述导电凸块电连接。
示例性地，所述衬底中还具有与所述第一芯片电连接的插塞，所述插塞向衬底背面延伸的端部埋在所述背面之下，将封装材料覆盖所述第二芯片和所述衬底的正面之后，对所述衬底的背面进行减薄，直至露出所述插塞；或者，
将封装材料覆盖所述第二芯片和所述衬底的正面之前，对所述衬底的背面进行减薄，之后，在所述衬底中形成与所述第一芯片电连接的插塞，所述插塞的端部从所述衬底的背面露出。
示例性地，将所述第二芯片设置在所述衬底上的方法，包括：
对所述衬底的背面进行减薄；
提供支撑基底，将所述支撑基底与所述衬底的背面进行接合；
在所述衬底的正面放置所述第二芯片；
去除所述支撑基底。
示例性地，在将封装材料覆盖所述第二芯片和所述衬底以及所述减薄之后，形成所述电连接结构的方法包括：在所述衬底中形成插塞，与所述第一芯片相对应的所述插塞电连接所述第一芯片，以及与所述第二芯片相对应的所述插塞电连接所述第二芯片。
示例性地，所述第二芯片的正面和所述衬底接合，或者，所述第二芯片的背面和所述衬底接合。
示例性地，将所述第二芯片设置在所述衬底上的方法，包括以下步骤：
通过粘接层将所述第二芯片粘接在所述衬底上。
示例性地，所述粘接层包括芯片连接薄膜、干膜或光阻。
示例性地，所述衬底具有正面和背面，所述封装层覆盖所述正面或所述背面。
本发明的晶圆级系统封装结构包括形成有多个第一芯片的衬底， 所述第一芯片利用半导体工艺生长而成；内嵌有多个第二芯片的封装层，所述封装层覆盖所述衬底和所述第一芯片；至少其中一个所述第二芯片与至少其中一个所述第一芯片电连接，将由半导体工艺生长在衬底上的第一芯片和第二芯片集成在晶圆级系统封装结构中，因此可以大幅减小晶圆级系统封装结构的面积，并提供更好的电性能。
本发明的晶圆级系统封装方法，使晶圆级封装和系统封装方法相结合，同时实现了多种芯片的集成和在晶圆上完成封装制造的优势，能够大幅减小封装结构的面积、降低制造成本、优化电性能、批次制造等，并明显的降低工作量与设备的需求，从而最终晶圆级系统封装方法的良率，以及形成的封装结构的性能。
附图说明
本发明的下列附图在此作为本发明的一部分用于理解本发明。附图中示出了本发明的实施例及其描述，用来解释本发明的原理。
附图中：
图1A至图1F示出了本发明一个具体实施方式的方法依次实施所获得结构的剖面示意图；
图2A至图2E示出了本发明另一个具体实施方式的方法依次实施所获得结构的剖面示意图；
图3示出了本发明一个具体实施方式的晶圆级系统封装方法的流程图。
具体实施方式
在下文的描述中，给出了大量具体的细节以便提供对本发明更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本发明可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本发明发生混淆，对于本领域公知的一些技术特征未进行描述。
应当理解的是，本发明能够以不同形式实施，而不应当解释为局限于这里提出的实施例。相反地，提供这些实施例将使公开彻底和完全，并且将本发明的范围完全地传递给本领域技术人员。在附图中，为了清楚，层和区的尺寸以及相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本发明教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本发明的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
这里参考作为本发明的理想实施例(和中间结构)的示意图的横截面图来描述发明的实施例。这样，可以预期由于例如制造技术和/或容差导致的从所示形状的变化。因此，本发明的实施例不应当局限于在此所示的区的特定形状，而是包括由于例如制造导致的形状偏 差。例如，显示为矩形的注入区在其边缘通常具有圆的或弯曲特征和/或注入浓度梯度，而不是从注入区到非注入区的二元改变。同样，通过注入形成的埋藏区可导致该埋藏区和注入进行时所经过的表面之间的区中的一些注入。因此，图中显示的区实质上是示意性的，它们的形状并不意图显示器件的区的实际形状且并不意图限定本发明的范围。
为了彻底理解本发明，将在下列的描述中提出详细步骤和结构，以便阐释本发明提出的技术方案。本发明的较佳实施例详细描述如下，然而除了这些详细描述外，本发明还可以具有其他实施方式。
鉴于晶圆级封装的优势，本发明提供一种晶圆级系统封装结构，其主要包括：
形成有多个第一芯片的衬底，所述第一芯片利用半导体工艺在所述衬底上生长而成；
内嵌有多个第二芯片的封装层，所述封装层覆盖所述衬底和所述第一芯片；
至少其中一个所述第二芯片与至少其中一个所述第一芯片电连接，所述第一芯片和所述第二芯片相互错开，通过电连接结构电连接。
本发明的晶圆级系统封装结构包括形成有多个第一芯片的衬底，所述第一芯片利用半导体工艺生长而成；内嵌有多个第二芯片的封装层，所述封装层覆盖所述衬底和所述第一芯片；至少其中一个所述第二芯片与至少其中一个所述第一芯片电连接，将由半导体工艺生长在衬底上的第一芯片和第二芯片集成在晶圆级系统封装结构中，因此可以大幅减小晶圆级系统封装结构的面积，并提供更好的电性能。
实施例一
下面参考图1F对本发明的一种封装结构进行解释和说明。
作为示例，所述晶圆级系统封装结构包括形成有多个第一芯片101的衬底100，所述第一芯片利用半导体工艺生长而成。
在一个示例中，所述晶圆级系统封装结构还包括内嵌有多个第二芯片201的封装层102，所述封装层102覆盖所述衬底100和所述第一芯片101。
示例性地，至少其中一个所述第二芯片201与至少其中一个所述 第一芯片101电连接。
在一个示例中，如图1F所示，所述第一芯片101和所述第二芯片201相互错开，也即第一芯片101和第二芯片201在俯视方向上相互错开，所述第一芯片101和所述第二芯片201通过电连接结构电连接。
在一个示例中，所述电连接结构包括：位于所述衬底100中，分别与第一芯片101、第二芯片201电连接的插塞1031、1032。
在一个示例中，与所述第一芯片101相对应的所述插塞1031电连接所述第一芯片101，以及与所述第二芯片201相对应的所述插塞1032电连接所述第二芯片201。
在一个示例中，如图1F所示，所述第二芯片201的正面和所述衬底100相接合。
在另一个示例中，还可以是所述第二芯片的背面和所述衬底相接合，具体选择何种接合方式可以根据实际工艺需要进行合理选择。
所述第二芯片201设置在所述第一芯片101之外的衬底区域，以使所述第二芯片201和第一芯片101完全错开。
在一个示例中，所述第二芯片201通过粘接层(未示出)设置在所述衬底100上，也即在所述第二芯片和所述衬底之间设置有粘接层(未示出)，所述第二芯片201粘接在所述衬底上。
在一个示例中，所述封装层102覆盖所述衬底100和所述第一芯片101，并使所述第二芯片201包围在所述封装层102内。
示例性地，如图1F所示，所述衬底100具有正面和背面，所述封装层102覆盖所述正面。
在另一个示例中，所述衬底具有正面和背面，所述封装层覆盖所述背面，也即所述封装层覆盖所述衬底设置有第二芯片的表面。
其中，所述封装层102的顶面高于所述第二芯片201的顶面，所述封装层102对第二芯片起到固定作用，并且能够提供物理和电气保护，防止外界干扰。
在一个示例中，如1F所示，在所述衬底100和所述第二芯片201之间设置有粘接层时，与第二芯片对应的插塞1032依次贯穿所述衬底以及所述粘接层，以与所述第二芯片201电连接，所述插塞1031 贯穿部分所述衬底与所述第一芯片101电连接。
在另一个示例中，在所述封装层覆盖所述衬底的背面时，还可以通过与所述第二芯片相对应的插塞，以及形成在衬底正面的再布线，将第二芯片和第一芯片电连接。
在一个示例中，所述晶圆级系统封装结构还包括焊盘104，所述焊盘104相对于所述封装层102，位于所述衬底100另一面。
在一个示例中，所述封装结构还包括具有开口106的钝化层105，所述钝化层105覆盖所述焊盘104和所述衬底100，所述开口106暴露出所述焊盘104。
示例性地，所述钝化层105的顶面高于所述焊盘104的顶面。所述钝化层的厚度可以是任意适合的厚度，在此不做具体限定。
本发明所涉及的衬底可以是以下所提到的半导体材料中的至少一种：Si、Ge、SiGe、SiC、SiGeC、InAs、GaAs、InP、InGaAs或者其它III/V化合物半导体，还包括这些半导体构成的多层结构等，或者为绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等。衬底100还可以是其他适合的衬底结构，衬底100还可以为单层或者包括多层(即两层或者多于两层)。
在本发明中所提及的芯片(例如所述第一芯片101和第二芯片201)可以是任意一种半导体芯片，其可以包括存储器、逻辑电路、功率器件、双极器件、单独的MOS晶体管、微机电系统(MEMS)等有源器件，甚至也可以是发光二极管等光电器件，其也可以为无源器件，例如电阻、电容等。其中，所述第一芯片101通过半导体工艺生长在所述衬底上，第一芯片的功能不同其所使用的半导体工艺也会不同，其可靠性更高，并且可以节省更多的工艺过程。
在此为了简便，仅以一方框的形式简单示出了第一芯片101，但可以想到的是第一芯片的结构可以包括多个构成元件以及将第一芯片引出的再布线(也即金属互连结构)等等，其中，金属互连结构可以包括多层金属层以及电连接相邻金属层的接触孔，在第一芯片生长的过程中会在衬底上形成多层介电层，相邻的第一芯片101之间可以由形成在衬底上的介电层隔开，形成类似如图1F所示的每个所述第 一芯片101嵌入在衬底表面内的结构。
在一个示例中，介电层的材料可以是本领域技术人员熟知的任何适合的介电材料，包括但不限于SiO 2、碳氟化合物(CF)、掺碳氧化硅(SiOC)或碳氮化硅(SiCN)等等。
多个第一芯片101之间可以具有相同或不同的功能。多个第一芯片101之间可以具有相同或不同的尺寸。第一芯片101的实际数目、功能和尺寸由设计要求决定并且不受限制。
可选地，第二芯片201可以是和第一芯片101具有不同功能的不同类型的芯片，也可以是为相同的芯片。
示例性地，前述的所述粘接层的可以两个表面具有粘性，一面粘接在所述衬底100的表面，一面粘接在所述第二芯片201的表面上，以将第二芯片201固定在所述衬底上，实现待集成芯片和衬底之间的物理连接。
所述粘接层可以仅形成在所述衬底预定用于固定所述第二芯片的区域，也可以覆盖在整个所述衬底上。
示例性地，所述粘接层可以为有机薄膜，有机薄膜可以包括各种有机膜层，例如芯片连接薄膜(die attach film，DAF)、干膜(dry film)或光阻等。粘接层的厚度根据需要设置，并且粘接层的层数也不限于一层，而可以使两层或更多层。
芯片连接薄膜(die attach film，DAF)可以是本领域技术人员熟知的任何适合的材料，例如可以是树脂胶，特别是高导热的树脂胶。
干膜是一种高分子的化合物，它通过紫外线的照射后能够产生一种聚合反应形成一种稳定的物质附着于衬底和第二芯片的待粘接表面，干膜可以包括三层，一层是PE保护膜，中间是干膜层，另一层是PET保护层，干膜层位于PE保护膜和PET保护层之间。
所述粘接层的厚度可以根据器件需要进行合理设定，在此不做具体限定，只要能够保证第二芯片牢固的固定在衬底上的任意厚度均可以适用于本发明。
在一个示例中，前述的所述封装层102可以是本领域技术人员熟知的任何适合的封装材料，例如，所述封装层102为塑封层，所述塑封层包括热固性树脂，在成型过程中能软化或流动，具有可塑性，可 制成一定形状，同时又发生化学反应而交联固化，塑封层可以包括酚醛树脂、脲醛树脂、三聚氰胺－甲醛树脂、环氧树脂、不饱和树脂、聚氨酯、聚酰亚胺等热固性树脂中的至少一种，其中，较佳地使用环氧树脂作为塑封层，其中环氧树脂可以采用有填料物质或者是无填料物质的环氧树脂，还包括各种添加剂(例如，固化剂、改性剂、脱模剂、热色剂、阻燃剂等)，例如以酚醛树脂作为固化剂，以固体颗粒(例如硅微粉)等作为填料。示例性地，塑封层还可以包括硅胶。
插塞1031、1032可以是本领域技术人员熟知的任何适合的金属插塞或者硅插塞(也即硅通孔，TSV)，金属插塞的材料可以包括但不限于Ag、Au、Cu、Pd、Cr、Mo、Ti、Ta、Sn、W和Al中的至少一种金属，而硅插塞的材料可以包括掺杂的多晶硅或者未掺杂的多晶硅等。
在一个示例中，所述焊盘104与所对应的插塞电连接。所述焊盘104的材料可以任意适合的金属材料，包括但不限于Ag、Au、Cu、Pd、Cr、Mo、Ti、Ta、Sn、W和Al中的至少一种金属。
所述钝化层105的材料可以使用任何适合的绝缘材料，例如所述钝化层105使用诸如氧化硅层、氮化硅层、或氮氧化硅层的无机绝缘层，可通过化学气相沉积、物理气相沉积或原子层沉积等沉积方法沉积形成所述钝化层105；还可以使用诸如包含聚乙烯苯酚、聚酰亚胺、或硅氧烷等的层的绝缘层等。聚乙烯苯酚、聚酰亚胺、或硅氧烷可有效地通过微滴排放法、印刷术或旋涂法形成。硅氧烷根据其结构可被分类成二氧化硅玻璃、烷基硅氧烷聚合物、烷基倍半硅氧烷(alkylsilsesquioxane)聚合物、倍半硅氧烷氢化物(silsesquioxane hydride)聚合物、烷基倍半硅氧烷氢化物(alkylsilsesquioxane hydride)聚合物等。此外，绝缘材料可用包括具有Si-N键的聚合物(聚硅氨烷)的材料形成。此外，可层叠这些膜以形成钝化层。
至此完成了对本发明的封装结构的描述，对于完整的结构，还可能包括其他的元件，在此不做具体赘述。
综上所述，本发明将第一芯片和第二芯片集成在晶圆级系统封装结构中，可以大幅减小晶圆级系统封装结构的面积，并提供更好的电性能，因此本发明的晶圆级系统封装结构具有更高的性能。
实施例二
本发明还提供一种晶圆级系统封装结构，下面参考图2E对本发明的一种封装结构进行解释和说明。
作为示例，本发明的晶圆级系统封装结构包括形成有多个第一芯片301的衬底300，所述第一芯片301利用半导体工艺在所述衬底300上生长而成。
在一个示例中，本发明的晶圆级系统封装结构还包括：内嵌有多个第二芯片401的封装层402，所述封装层402覆盖所述衬底300和所述第一芯片301。
示例性地，所述衬底300具有正面和背面，所述封装层402覆盖所述正面。
在另一个示例中，所述衬底具有正面和背面，所述封装层覆盖所述背面，也即所述封装层覆盖所述衬底设置有第二芯片的表面。
进一步地，本发明的晶圆级系统封装结构还包括：至少其中一个所述第二芯片401与至少其中一个所述第一芯片301电连接，所述第一芯片301和所述第二芯片401相互错开，通过电连接结构电连接。
在一个示例中，所述电连接结构包括：位于所述衬底300中，与第一芯片301电连接的插塞302，以及位于第一芯片301和第二芯片401之间或所述插塞302顶部的再布线(未示出)。
示例性地，在多个所述第一芯片301中的至少一个中设置有至少一个插塞302，所述插塞302贯穿所述第一芯片301，例如，所述插塞302贯穿所述第一芯片301，并贯穿所述衬底的正面和背面，与形成在衬底背面的第一焊盘305电连接。
在另一示例中，所述插塞贯穿所述第一芯片301，并贯穿所述衬底的正面和背面，与形成在衬底正面的第一焊盘305电连接，具体可以根据实际的封装结构进行合理设置。
示例性地，所述插塞302设置在所述第一芯片301的边缘区域，或者其他适合的能够实现与第一芯片301电连接而不影响第一芯片301功能实现的区域。
进一步地，所述电连接结构还包括：形成在所述再布线和所述第二芯片401之间的导电凸块304。
示例性地，所述导电凸块304呈阵列排布。所述导电凸块304可以为锡球、或铜柱、或金凸点、或合金凸块等等，也可以为其他适合的导电凸块结构。
导电凸块304主要包括金属材料，金属材料包括但不限于锡、铜、镍、银锡铜合金或者锡基合金中的至少一种材料。
在另一个示例中，所述导电凸块还可以设置在衬底上，但其位置与所述第一芯片的位置相互错开，而该导电凸块电连接与所述第一芯片电连接的再布线，第二芯片设置在导电凸块上，通过导电凸块和所述再布线使所述第一芯片和第二芯片电连接。
在一个示例中，所述封装结构还包括第二焊盘303，位于所述衬底300正面，与所述第一芯片301电连接。
在一个示例中，在所述第一芯片和所述第二芯片401相互错开时，所述第二焊盘303还可以设置在所述第二芯片401和所述衬底300之间，第二焊盘303可以电连接与所述第一芯片301电连接的再布线，由第二焊盘303实现第一芯片301和第二芯片401的电连接。
在一个示例中，所述导电凸块304设置在所述第二焊盘303上，并与所述第二焊盘电连接。
在一个示例中，在第二焊盘和所述导电凸块304之间还可以设置有凸块下金属化(UBM)结构(未示出)，凸块下金属化(UBM)结构可由粘附层、阻挡层、和种子或润湿层的多层金属堆叠而成。UBM结构有助于防止凸块和多芯片半导体器件的集成电路之间的扩散，同时提供了低阻电连接。
在一个示例中，所述封装结构还包括：相对于所述封装层402，位于所述衬底300另一面的第一焊盘305，所述第一焊盘305电连接相应的所述插塞302。
示例性地，所述封装层402覆盖所述衬底300的正面，则所述第一焊盘305设置在所述衬底300的背面，或者，所述封装层402覆盖所述衬底300的背面，则所述第一焊盘305设置在所述衬底300的正面。
在一个示例中，所述封装结构还包括具有开口307的钝化层306，其覆盖所述第一焊盘305和所述衬底300，所述开口307暴露出所述 第一焊盘305。
本实施例和前述实施例中的方案还可以交叉引用，在此为了避免重复，对于涉及的相同的结构和膜层等的解释和说明可以参考前述实施例，在此不做赘述。
实施例三
鉴于晶圆级系统封装的显著优势，本发明提出一种改进了的晶圆级系统封装方法，如图3所示，其主要包括以下步骤：
步骤S1，提供具有多个第一芯片的衬底，所述第一芯片利用半导体工艺在所述衬底上生长而成；
步骤S2，提供多个第二芯片，将所述第二芯片设置在所述衬底上，所述第二芯片和所述第一芯片错开；
步骤S3，形成电连接结构，使至少其中一个所述第二芯片与至少其中一个所述第一芯片电连接；
步骤S4，将封装材料覆盖所述第二芯片和所述衬底，以固定所述第二芯片。
本发明的晶圆级系统封装方法，使用晶圆级封装和系统封装方法相结合，同时实现了多种芯片的集成和在晶圆上完成封装制造优势，具有大幅减小封装结构的面积、降低制造成本、优化电性能、批次制造等优势，可明显的降低工作量与设备的需求，提高了封装的效率和良率。由本发明的晶圆级系统封装方法制备获得的封装结构同样具有更高的性能和良率。
下面，参考图1A至图1F对本发明的晶圆级系统封装方法做详细描述，其中，图1A至图1F示出了本发明一个具体实施方式的方法依次实施所获得结构的剖面示意图。
作为示例，该封装方法可以用于前述实施例一中的封装结构的制备，本发明的晶圆级系统封装方法包括以下步骤：
首先，执行步骤一，如图1A所示，提供具有多个第一芯片101的衬底100。该第一芯片101和衬底100的具体结构等描述参考前述实施例一中的描述，在此不做赘述。接着，执行步骤二，继续如图1A所示，提供多个第二芯片201，将所述第二芯片201设置在所述衬底100上，所述第二芯片201和所述第一芯片101错开。所述第二 芯片201的类型等描述可以参考前述实施例一，在此不做赘述。
可选地，第二芯片201可以是和第一芯片101具有不同功能的不同类型的芯片，也可以是为相同的芯片。
在一个示例中，所述第二芯片201的正面和所述衬底100相接合。
在另一个示例中，所述第二芯片的背面和所述衬底的相接合，具体选择何种接合方式可以根据实际工艺需要进行合理选择。
其中，所述第二芯片201设置在所述第一芯片101之外的衬底的区域，以使所述第二芯片201和第一芯片101完全错开，以便于后续插塞工艺的执行。
将所述第二芯片固定至所述衬底的方法，可以使用任何适合的方法，在一个示例中，将所述第二芯片201固定至所述衬底100的方法，包括以下步骤：在所述衬底100上形成粘接层(未示出)，以将所述第二芯片201粘接在所述衬底。
所述粘接层的两个表面具有粘性，一面粘接在所述衬底100的表面，一面粘接在所述第二芯片201的表面上，以将第二芯片201固定在所述衬底上，实现待集成芯片和衬底之间的物理连接。
所述粘接层可以仅形成在所述衬底预定用于固定所述第二芯片的区域，也可以覆盖在整个所述衬底。
在另一个示例中，还可以在将所述第二芯片设置在所述衬底上之前，还包括以下步骤A1至A4：
首先，进行步骤A1，对所述衬底的背面进行减薄；可以使用任何适合的工艺执行本步骤的减薄，例如机械研磨(grinding)工艺、化学机械研磨工艺或者刻蚀工艺等。减薄后的衬底的厚度可以根据实际工艺进行合理设定，例如，减薄后的衬底100的厚度在10μm至100μm之间，也可以根据技术节点的不同，该厚度相应变化，在此不做具体限定。
接着，进行步骤A2，提供支撑基底，将所述支撑基底与所述衬底的背面进行接合；所述支撑基底可以是本领域技术人员熟知的任何适合的基底，例如半导体衬底、玻璃基底、陶瓷基底等，将所述支撑基底与所述衬底的背面进行接合，该接合可以使用任何适合的接合方式，例如临时键合或者粘接等，例如使用键合胶层将支撑基底和衬底 的背面接合，键合胶层可以是但不限于是有机高分子材料或可紫外变性的有机材料。
接着，进行步骤A3，在所述衬底的正面放置所述第二芯片；放置第二芯片的方法可以是本领域技术人员熟知的任何适合的方法，较佳地使用前述步骤中所述的方法，例如通过粘接的方式将所述第二芯片放置到衬底上。
接着，进行步骤A4，去除所述支撑基底。去除所述支撑基底，根据所使用的接合方式选择适合的去除方法，例如，高温或者紫外照射的方式，使键合胶层变性失去粘性，从而将支撑基底剥离。其中，值得一提的是，该支撑基底的去除还可以在将封装材料覆盖所述第二芯片和所述衬底，以固定所述第二芯片的步骤之后进行。
接着，执行步骤三，如图1B所示，将封装材料覆盖所述第二芯片201和所述衬底100，以固定所述第二芯片201。
示例性地，可以通过注塑成型工艺将封装材料覆盖所述第二芯片201和所述衬底100，所述注塑成型可以为热压注塑成型工艺，或者其他适合的注塑成型工艺。
示例性地，所述注塑成型工艺使用液体的塑封料(Mold Compound)或者固体的塑封料，其中，较佳得使用液体的塑封料，以使液体的塑封料在固化前能够填充在相邻导电凸块之间的间隙中，也即第一芯片和第二芯片之间的间隙中，增加第一芯片和第二芯片之间的粘结性，提高封装的稳固性。
在一个示例中，将封装材料覆盖所述第二芯片和所述衬底的步骤包括：提供模具，将所述衬底放置于所述模具中，其中，所述模具可以为任何适合的模具，在此不做具体限定，随后，在所述模具中注入熔融状态的塑封料，液态的塑封料均匀涂覆于整个衬底上，将第二芯片201包裹起来，接着，进行固化处理，以使所述塑封料凝固，以形成塑封层作为所述封装层102，所述固化可以为热固化工艺，具体的根据实际使用的塑封料而合理选择适合的固化方式，最后进行脱模。
示例性地，所述封装层102的顶面高于所述第二芯片201的顶面，所述封装层102对芯片提供物理和电气保护，防止外界干扰。
在一个示例中，所述衬底100具有正面和背面，所述封装层102 覆盖所述正面，此时所述第二芯片设置在所述衬底的正面。
在一个示例中，所述衬底具有正面和背面，所述封装层102覆盖所述背面，此时所述第二芯片201设置在所述衬底100的背面。
在一个示例中，如图1C所示，在将封装材料覆盖所述第二芯片和所述衬底之后，还包括：对所述衬底的背面进行减薄的步骤，该减薄步骤通常是在第二芯片放置在衬底上之前并未执行对衬底的背面减薄的工艺时进行。
接着，执行步骤四，形成电连接结构，使至少其中一个所述第二芯片与至少其中一个所述第一芯片电连接。
示例性地，如图1D所示，在所述衬底中形成插塞1031、1032，与所述第一芯片101相对应的所述插塞1031电连接所述第一芯片101，以及与所述第二芯片201相对应的所述插塞1032电连接所述第二芯片201，所述插塞1031、1032的端部从所述衬底100的背面露出。
具体地，所述插塞1031用于实现第一芯片101和外部电路的电连接，所述插塞1032用于实现第二芯片201和外部电路的电连接，尽管图1D中仅示出了一个第一芯片101电连接一个所述插塞1031，一个第二芯片201电连接一个所述插塞1032的情况，但是对于其他的每个芯片电连接多个插塞的情况，也同样适用于本发明。
可以使用本领域技术人员熟知的任何适合的方法形成插塞1031和插塞1032，在一个示例中，通过粘接层将所述第二芯片粘接在所述衬底上时，形成插塞1031和插塞1032包括以下步骤：可以首先相对于所述封装层，在所述衬底另一面形成图案化的掩膜层(未示出)，图案化的掩膜层中定义有所述插塞的图案，该掩膜层可以包括数种掩膜材料中的任何一种，包括但不限于：硬掩膜材料和光刻胶掩膜材料，较佳地，所述掩膜层使用光刻胶掩膜材料，可以通过在衬底的背面旋涂光刻胶掩膜材料，再利用光刻工艺对光刻胶掩膜材料进行图案化，以形成图案化的光刻胶掩膜材料，在图案化的光刻胶掩膜材料中定义了预定形成的插塞和插塞的位置和关键尺寸，然后以所述图案化的掩膜层为掩膜，刻蚀部分衬底100，直到露出部分所述第一芯片以形成通孔，以及蚀刻部分所述衬底和所述粘接层，直到露出部分所述第二 芯片以形成通孔，该刻蚀工艺可以是湿法刻蚀或者干法刻蚀工艺，其中较佳地使用干法刻蚀工艺，干法刻蚀包括但不限于：反应离子刻蚀(RIE)、离子束刻蚀、等离子体刻蚀或者激光切割，随后，将图案化的掩膜层去除，例如使用灰化的方法去除光刻胶掩膜材料，最后，形成导电材料(例如金属材料或多晶硅)填充所述通孔，以形成插塞1031、1032，其中，可以使用物理气相沉积方法(PVD)、化学气相沉积方法(CVD)、溅射、电解电镀、无电极电镀工艺、或其它合适的金属沉积工艺形成所述导电材料。
值得注意的是，在通过粘接层实现第二芯片和衬底的接合时，在刻蚀形成通孔时，要实现电性连接，刻蚀的时候必须刻蚀穿复合膜(衬底和粘接层)，粘接层通常是有机薄膜，一般衬底可以包括各种无机膜层，例如包括半导体衬底以及介电层，其中，介电层例如为氧化硅层或氮化硅层，并且无机膜层的层数也不限于一层，而可以使两层或更多层。可以使用干法刻蚀例如采用诸如CF 4的含氟气体为刻蚀气体的刻蚀方法对衬底进行刻蚀，再对粘接层(也即有机薄膜)进行刻蚀，刻蚀有机薄膜时以氧气或氩气为刻蚀气体。
示例性地，所述插塞1031自所述衬底100的背面向正面延伸直到与其所对应的所述第一芯片101电连接，所述插塞1032自所述衬底100的背面向正面延伸直到与其所对应的所述第二芯片201电连接。
值得一提的是，对于将所述第二芯片设置在所述衬底的背面的情况，上述方法同样适用。
示例性地，在所述衬底的背面放置所述第二芯片之前，可以先对所述衬底的背面进行减薄，随后，将第二芯片放置在衬底的背面，再将封装材料覆盖所述第二芯片和所述衬底，接着，在所述衬底中形成插塞，与所述第一芯片相对应的所述插塞电连接所述第一芯片，以及与所述第二芯片相对应的所述插塞电连接所述第二芯片。
在一个示例中，在形成所述插塞之后，还包括执行以下步骤B1至步骤B3的过程，首先，执行步骤B1，如图1E所示，在所述衬底上形成焊盘104，其中，所述焊盘104相对于所述第二芯片201位于所述衬底100另一面，并且所述焊盘104电连接所述插塞1031、1032。
示例性地，所述焊盘104电连接至少一个所述插塞1031和/或至少一个所述插塞1032。所述焊盘104电连接插塞，以实现第一芯片和第二芯片的电连接。
示例性地，焊盘用于将第一芯片和第二芯片引出与外部电路实现连接，可以是在每个所述插塞1031和所述插塞1032上设置一个所述焊盘104，以实现焊盘104对每个芯片的独立电连接，或者，还可以是一个焊盘104电连接多个所述插塞1031，一个焊盘104电连接多个所述插塞1032，或者，也可以是一个焊盘104电连接至少一个所述插塞1031和至少一个所述插塞1032，以实现更多的功能连接。
可以使用任何适合的方法形成所述焊盘104，例如，形成焊盘材料层以覆盖衬底100的背面，其中，可以使用物理气相沉积方法(PVD)、化学气相沉积方法(CVD)、溅射、电解电镀、无电极电镀工艺、或其它合适的金属沉积工艺形成所述焊盘材料层，再通过刻蚀的方法去除部分所述焊盘材料层，以形成所述焊盘104，相邻所述焊盘104之间彼此间隔。
接着，执行步骤B2，如图1F所示，形成钝化层105，以覆盖所述焊盘104以及所述衬底100。
示例性地，所述钝化层105的顶面高于所述焊盘104的顶面。所述钝化层的厚度可以是任意适合的厚度，在此不做具体限定。
示例性地，在沉积钝化层105后还可以选择性的对钝化层105的表面进行化学机械研磨，以获得平坦的表面。
接着，执行步骤B3，继续如图1F所示，在每个所述焊盘104上方的所述钝化层105中形成开口106，所述开口106露出所述焊盘104的至少部分表面。
为了实现焊盘与外部电路的连接，需要露出焊盘表面的开口106，可以使用任何适合的方法形成所述开口106，在一个示例中，首先在钝化层105的表面形成图案化的掩膜层，例如光刻胶层，该图案化的掩膜层定义有开口的位置、形状和关键尺寸等，然后再以该图案化的掩膜层为掩膜，刻蚀露出的钝化层105，直到露出焊盘104的表面，以形成所述开口106，随后，将图案化的掩膜层去除，例如通过灰化或者湿法刻蚀的方法去除光刻胶材质的掩膜层。
至此，完成了对本发明的晶圆级系统封装方法的关键步骤的介绍，对于完整的方法还可能包括其他的步骤，例如封装完成后，还可以沿切割道对衬底进行切割工艺，以将集成在衬底上的多个芯片分割为各自独立的单元，例如每个单元均包括相接合的第一芯片和第二芯片，该单元形成一个可提供多种功能的系统或子系统，该功能取决于实际集成的芯片的功能。
综上所述，根据本发明的晶圆级系统封装方法，使用晶圆级封装和系统封装方法相结合，同时实现了多种芯片的集成和在衬底上完成封装制造优势，在衬底上完成封装集成制程，具有大幅减小封装结构的面积、降低制造成本、优化电性能、批次制造等优势，可明显的降低工作量与设备的需求，提高了封装的效率、良率和性能。
实施例四
本发明还提供一种前述实施例二中的晶圆级系统封装结构的制备方法，下面参考图2A至图2E对本发明的晶圆级系统封装方法做详细解释和说明。
值得一提的是，为了避免重复，在本实施例中主要针对该实施例的方法区别于前述实施例一和实施例三的部分作解释和说明，对于其他未进行详细解释的其可以参考前述实施例中的描述。
作为示例，首先，执行步骤一，如图2A所示，提供具有多个第一芯片301的衬底300，所述第一芯片301利用半导体工艺生长而成。
在一个示例中，在对衬底的背面进行减薄之前，所述衬底300中还具有与所述第一芯片301电连接的插塞302，所述插塞302向衬底300背面延伸的端部埋在所述背面之下，也即插塞302的端部埋在衬底300中。
示例性地，所述插塞302设置在所述第一芯片301的边缘区域，或者其他适合的能够实现与第一芯片301电连接而不影响第一芯片301功能实现的区域。
在一个示例中，在所述衬底的正面形成第二焊盘303，所述第二焊盘303与所述第一芯片301电连接，其中，所述第二焊盘303设置在所述第一芯片301的表面，并且还可以使部分所述第二焊盘303设置在所述插塞302的表面上与所述插塞302电连接，相邻所述第二焊 盘303之间存在间隔。
可以使用任何适合的方法形成所述第二焊盘303，例如，可以通过包括但不限于物理气相沉积方法或者化学气相沉积方法的沉积方法形成焊盘材料层以覆盖衬底的正面，再通过刻蚀的方法去除部分所述焊盘材料层，以形成多个间隔设置的第二焊盘303。
接着，执行步骤二，继续参考图2A，提供多个第二芯片401，将所述第二芯片401设置在所述衬底上，所述第二芯片401和所述第一芯片301错开。随后，形成电连接结构，使至少其中一个所述第二芯片与至少其中一个所述第一芯片电连接。
在一个示例中，继续如图2A所示，形成电连接结构的方法包括步骤C1至C2：
步骤C1，在将第二芯片放置在衬底上之前，在所述衬底300上形成与至少其中一个所述第一芯片301电连接的再布线(未示出)，可以使用本领域技术人员熟知的方法形成所述再布线层，在此不做赘述。
步骤C2，将所述第二芯片401放置在所述衬底300上，并使所述第一芯片和所述第二芯片相互错开，二者通过所述再布线电连接。
在一个示例中，在所述衬底中形成有插塞302时，所述再布线形成在所述插塞的顶部。
值得一提的是，使至少其中一个所述第二芯片与至少其中一个所述第一芯片电连接的电连接结构包括前述的插塞302和再布线等。
示例性地，将所述第二芯片设置在所述衬底上的方法包括步骤D1和D2：
步骤D1，在所述再布线上形成至少一个导电凸块；
可以通过任何适合的方法形成所述导电凸块304，在一个示例中，所述导电凸块304为焊球(例如锡球)时，可以通过植球工艺将焊球放置于至少其中一个所述第一芯片的表面上(也即预定形成凸块的位置上)，进一步地，放置在相应的第二焊盘303上，其中，所述植球工艺是指将选择好的与焊盘相匹配的焊球，对应放置于焊盘之上，此过程称为植球，植球工艺可以为人工植球或者植球器植球。
示例性地，所述植球工艺可以是将植球网罩设在第一芯片301的 表面上，将焊球放置到植球网上平铺，将所述焊球从所述植球网上的通孔粘到第一芯片的表面。
再经过回流焊工艺，熔融焊球以使其与第一芯片电连接，在设置有第二焊盘303时，则与所述第二焊盘303电连接。作为一个实例，回流焊的温度范围为200℃～260℃，也可以是其他适合的温度。
步骤D2，将所述第二芯片401放置在所述导电凸块304上，所述第一芯片301和第二芯片401通过所述导电凸块304电连接。可选地，在导电凸块304和所述再布线之间还可以形成有第二焊盘303。
在一个示例中，还可以通过在第一芯片上(尤其是第二焊盘303上)通过丝网印刷法沉积焊锡膏，将第二芯片对应设置在衬底上后，再进行回流焊，以实现第一芯片和第二芯片的电连接。
接着，执行步骤三，如图2B所示，将封装材料覆盖所述第二芯片401和所述衬底300，以固定所述第二芯片401。
示例性地，可以通过注塑成型工艺将封装材料覆盖所述第二芯片401和所述衬底300，所述注塑成型可以为热压注塑成型工艺，或者其他适合的注塑成型工艺。
值得一提的是，本步骤三可以参考前述实施例三中的步骤三的描述，在此不做赘述。
在一个示例中，所述衬底300具有正面和背面，所述封装层402覆盖所述正面，此时所述第二芯片设置在所述衬底的正面。
在另一个示例中，所述衬底具有正面和背面，所述封装层覆盖所述背面，此时所述第二芯片设置在所述衬底的背面。
在一个示例中，如图2C所示，所述衬底300中还具有与所述第一芯片301电连接的插塞302，所述插塞302向衬底300背面延伸的端部埋在所述背面之下，再将封装材料覆盖所述第二芯片401和所述衬底200的正面之后，还包括：对所述衬底300的背面进行减薄，直至露出所述插塞302。
值得一提的是，该减薄还可以对插塞进行过刻蚀，直到衬底的厚度达到目标厚度。
在将封装材料覆盖所述第二芯片和所述衬底的正面之后，再进行插塞的制作的封装方法，由于塑封层通常使用的为有机材料，而衬底 通常为无机材料(例如硅)，两者材料不同，热膨胀系数相应也不一致，很容易使得封装结构发生翘曲变形，进而影响后续制程例如背部研磨(grinding)的可操作性以及良率，并且使得机械手在不同制程之间传输晶圆时对晶圆的抓取变的更加不易，导致碎片或者抓取不成功出现的概率增大，以及在后续形成插塞时易发生插塞偏离预定位置而无法实现预定的电连接的问题，而本发明中在将封装材料覆盖所述第二芯片和所述衬底的正面之前，已经形成有插塞，在将封装材料覆盖所述第二芯片和所述衬底的正面之后，再进行减薄工艺，可以避免了由于先进行注塑成型工艺后制作插塞连接所产生的各种工艺问题(例如由于翘曲变形导致的插塞位置偏离电连接失败，以及翘曲问题对减薄工艺造成的负面影响)，进而提高了电性能。
在另一个示例中，将封装材料覆盖所述第二芯片和所述衬底的正面之前，并未在衬底中形成插塞时，可以先进行以下步骤：对所述衬底的背面进行减薄，该减薄停止于目标厚度；在所述衬底中形成与所述第一芯片电连接的插塞，所述插塞的端部从所述衬底的背面露出。其中，减薄的方法可以参考前述的减薄方法，为避免重复，在此不做赘述，也可以通过前述示例中的插塞的形成方法形成所述插塞。
在另一个示例中，还可以在步骤二之前，也即将所述第二芯片设置在所述衬底上之前，进行以下步骤E1至E4：首先，执行步骤E1，对所述衬底的背面进行减薄，减薄至目标厚度；接着，执行步骤E2，提供支撑基底，接着，执行步骤E3，在所述衬底的正面放置所述第二芯片；最后，执行步骤E4去除所述支撑基底。其中，值得一提的是，该支撑基底的去除还可以在将封装材料覆盖所述第二芯片和所述衬底，以固定所述第二芯片的步骤之后进行。
值得一提的是，在所述步骤E1执行之前，也即在所述减薄之前，所述衬底中还具有与所述第一芯片电连接的插塞，所述插塞向衬底背面延伸的端部埋在所述背面之下，所述减薄之后，所述插塞的端部从所述衬底的背面露出。
也可以是，在将封装材料覆盖所述第二芯片和所述衬底之后，或者，在所述衬底的正面放置所述第二芯片之前，所述步骤E1的减薄之后，还包括：在所述衬底中形成与第一芯片电连接的插塞，所述插 塞的端部从所述衬底的背面露出。
在再一个实施例中，还可以将所述第二芯片设置在所述衬底的背面，此时可以现在衬底中已经形成了插塞，例如，所述衬底300中还具有与所述第一芯片301电连接的插塞302，所述插塞302向衬底300背面延伸的端部埋在所述背面之下，其中，在所述衬底的背面放置所述第二芯片之前，还包括：对所述衬底的背面进行减薄，直至露出所述插塞。
在其他的一个示例中，还可以在所述衬底的背面放置所述第二芯片，进行以下步骤：对所述衬底的背面进行减薄；在所述衬底中形成与所述第一芯片电连接的插塞，所述插塞的端部从所述衬底的背面露出。
值得一提的是，前述示例中所提及的减薄可以使用任何适合的工艺执行本步骤的减薄，例如机械研磨(grinding)工艺、化学机械研磨工艺或者刻蚀工艺等。
减薄后的衬底的厚度可以根据实际工艺进行合理设定，例如，减薄后的衬底300的厚度在10μm至100μm之间，也可以根据技术节点的不同，该厚度相应变化，在此不做具体限定。
其中，前述示例中所提及的插塞的形成方法可以使用任何适合的方法，也可以使用前述示例中的方法。
随后，执行以下步骤：首先，如图2D所示，在所述衬底300上形成第一焊盘305，其中，所述第一焊盘305相对于所述第二芯片401位于所述衬底300另一面，并且所述第一焊盘305电连接所述插塞302。接着，如图2E所示，形成钝化层306，以覆盖第一焊盘305以及所述衬底300。接着，继续如图2E所示，在每个所述第一焊盘305上方的所述钝化层306中形成开口307，所述开口307露出所述第一焊盘305。
至此，完成了对本发明的晶圆级系统封装方法的关键步骤的介绍，对于完整的方法还可能包括其他的步骤，例如封装完成后，还可以沿切割道对衬底进行切割工艺，以将集成在衬底上的多个芯片分割为各自独立的单元，例如每个单元均包括相接合的第一芯片和第二芯片，该单元形成一个可提供多种功能的系统或子系统，该功能取决于 实际集成的芯片的功能。
综上所述，根据本发明的晶圆级系统封装方法，使用晶圆级封装和系统封装方法相结合，同时实现了多种芯片的集成和在衬底上完成封装制造优势，在衬底上完成封装集成制程，具有大幅减小封装结构的面积、降低制造成本、优化电性能、批次制造等优势，可明显的降低工作量与设备的需求，提高了封装的效率、良率和性能。
本发明已经通过上述实施例进行了说明，但应当理解的是，上述实施例只是用于举例和说明的目的，而非意在将本发明限制于所描述的实施例范围内。此外本领域技术人员可以理解的是，本发明并不局限于上述实施例，根据本发明的教导还可以做出更多种的变型和修改，这些变型和修改均落在本发明所要求保护的范围以内。本发明的保护范围由附属的权利要求书及其等效范围所界定。

Claims (20)

  1. 一种晶圆级系统封装结构，其特征在于，包括：
    形成有多个第一芯片的衬底，所述第一芯片利用半导体工艺在所述衬底上生长而成；
    内嵌有多个第二芯片的封装层，所述封装层覆盖所述衬底和所述第一芯片；
    至少其中一个所述第二芯片与至少其中一个所述第一芯片电连接，所述第一芯片和所述第二芯片相互错开，通过电连接结构电连接。
  2. 如权利要求1所述的封装结构，其特征在于，所述电连接结构包括：
    位于所述衬底中与所述第一芯片电连接的插塞。
  3. 如权利要求2所述的封装结构，其特征在于，所述电连接结构还包括：
    位于第一芯片和第二芯片之间或所述插塞顶部的再布线。
  4. 如权利要求3所述的封装结构，其特征在于，所述电连接结构还包括：
    形成在所述再布线和所述第二芯片之间的导电凸块。
  5. 如权利要求1所述的封装结构，其特征在于，所述衬底具有正面和背面，所述封装层覆盖所述正面或背面。
  6. 如权利要求2或3或4所述的封装结构，其特征在于，所述封装结构还包括：
    相对于所述封装层，位于所述衬底另一面的焊盘，所述焊盘电连接相应的所述插塞。
  7. 如权利要求1所述的封装结构，其特征在于，所述第二芯片的正面和所述衬底接合，或者，所述第二芯片的背面和所述衬底接合。
  8. 如权利要求1所述的封装结构，其特征在于，所述第二芯片通过粘接层设置在所述衬底上。
  9. 如权利要求8所述的封装结构，其特征在于，所述粘接层包括芯片连接薄膜、干膜或光阻。
  10. 如权利要求1所述的封装结构，其特征在于，所述封装层为塑封层。
  11. 一种晶圆级系统封装方法，其特征在于，包括：
    提供具有多个第一芯片的衬底，所述第一芯片利用半导体工艺在所述衬底上生长而成；
    提供多个第二芯片，将所述第二芯片设置在所述衬底上，所述第二芯片和所述第一芯片错开；
    形成电连接结构，使至少其中一个所述第二芯片与至少其中一个所述第一芯片电连接；
    将封装材料覆盖所述第二芯片和所述衬底，以固定所述第二芯片。
  12. 如权利要求11所述的封装方法，其特征在于，所述形成电连接结构的方法包括：
    在将所述第二芯片设置在所述衬底上之前，在所述衬底上形成与至少其中一个所述第一芯片电连接的再布线；
    将所述第二芯片放置在所述衬底上，并使所述第一芯片和所述第二芯片相互错开，二者通过所述再布线电连接。
  13. 如权利要求12所述的封装方法，其特征在于，将所述第二芯片设置在所述衬底上的方法包括：
    在所述再布线上形成至少一个导电凸块；
    将所述第二芯片放置在所述导电凸块上，所述第一芯片和第二芯片通过所述导电凸块电连接。
  14. 如权利要求11所述的封装方法，其特征在于，所述衬底中还具有与所述第一芯片电连接的插塞，所述插塞向衬底背面延伸的端部埋在所述背面之下，将封装材料覆盖所述第二芯片和所述衬底的正面之后，对所述衬底的背面进行减薄，直至露出所述插塞；或者，
    将封装材料覆盖所述第二芯片和所述衬底的正面之前，对所述衬底的背面进行减薄，之后，在所述衬底中形成与所述第一芯片电连接的插塞，所述插塞的端部从所述衬底的背面露出。
  15. 如权利要求11所述的封装方法，其特征在于，将所述第二芯片设置在所述衬底上的方法，包括：
    对所述衬底的背面进行减薄；
    提供支撑基底，将所述支撑基底与所述衬底的背面进行接合；
    在所述衬底的正面放置所述第二芯片；
    去除所述支撑基底。
  16. 如权利要求15所述的封装方法，其特征在于，在将封装材料覆盖所述第二芯片和所述衬底以及所述减薄之后，形成所述电连接结构的方法包括：在所述衬底中形成插塞，与所述第一芯片相对应的所述插塞电连接所述第一芯片，以及与所述第二芯片相对应的所述插塞电连接所述第二芯片。
  17. 如权利要求11所述的封装方法，其特征在于，所述第二芯片的正面和所述衬底接合，或者，所述第二芯片的背面和所述衬底接合。
  18. 如权利要求11所述的封装方法，其特征在于，将所述第二芯片设置在所述衬底上的方法，包括以下步骤：
    通过粘接层将所述第二芯片粘接在所述衬底上。
  19. 如权利要求18所述的封装方法，其特征在于，所述粘接层包括芯片连接薄膜、干膜或光阻。
  20. 如权利要求12所述的封装方法，其特征在于，所述衬底具有正面和背面，所述封装层覆盖所述正面或所述背面。
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