WO2019210617A1 - 晶圆级系统封装方法及封装结构 - Google Patents

晶圆级系统封装方法及封装结构 Download PDF

Info

Publication number
WO2019210617A1
WO2019210617A1 PCT/CN2018/101763 CN2018101763W WO2019210617A1 WO 2019210617 A1 WO2019210617 A1 WO 2019210617A1 CN 2018101763 W CN2018101763 W CN 2018101763W WO 2019210617 A1 WO2019210617 A1 WO 2019210617A1
Authority
WO
WIPO (PCT)
Prior art keywords
chip
adhesive layer
device wafer
hole
wafer
Prior art date
Application number
PCT/CN2018/101763
Other languages
English (en)
French (fr)
Inventor
刘孟彬
罗海龙
Original Assignee
中芯集成电路（宁波）有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 中芯集成电路（宁波）有限公司 filed Critical 中芯集成电路（宁波）有限公司
Priority to KR1020207022047A priority Critical patent/KR102400264B1/ko
Priority to JP2020562809A priority patent/JP7027577B2/ja
Priority to US16/206,037 priority patent/US10861821B2/en
Publication of WO2019210617A1 publication Critical patent/WO2019210617A1/zh
Priority to US17/078,944 priority patent/US11309279B2/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H01L21/3043—Making grooves, e.g. cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02372—Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1131—Manufacturing methods by local deposition of the material of the bump connector in liquid form
    • H01L2224/1132—Screen printing, i.e. using a stencil
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/11334—Manufacturing methods by local deposition of the material of the bump connector in solid form using preformed bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849—Reflowing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/83005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/83896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92222—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92224—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1431—Logic devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Definitions

  • the present invention relates to the field of semiconductor manufacturing, and in particular, to a wafer level system packaging method and a package structure.
  • the system package can combine multiple components of active components, passive components, micro-electromechanical systems (MEMS), optical components and other components into one unit to form a system or subsystem that provides multiple functions, allowing different Quality IC integration.
  • MEMS micro-electromechanical systems
  • SoC System on Chip
  • Wafer Level Package System in Package WLPSiP
  • traditional systems Wafer Level Package System in Package
  • the wafer-level system package completes the package integration process on the device wafer, which greatly reduces the area of the package structure, reduces manufacturing cost, optimizes electrical performance, batch manufacturing, etc., and can significantly reduce the workload and Equipment requirements.
  • the problem to be solved by the present invention is to provide a wafer level system packaging method and package structure to improve the performance and reliability of the package structure.
  • the present invention provides a wafer level system packaging method, including: providing a device wafer, the device wafer including a first front surface integrated with a plurality of first chips and opposite to the first front surface a first back surface; providing a plurality of second chips; forming a photolithographic adhesive layer on the first front surface of the device wafer; patterning the adhesive layer to form a plurality of exposed layers in the adhesive layer a first through hole of the first front surface; after the adhesive layer is patterned, the second chip is disposed on the remaining adhesive layer, and the second chip is in one-to-one correspondence with the first through hole Covering a top portion of the first via hole and bonding the device wafer and the second chip; etching a first back surface of the device wafer to form a through-the-device in the device wafer a second via hole penetrating through the first via hole, the second via hole and the first via hole forming a first conductive via; forming the same in the first conductive via hole
  • the present invention further provides a package structure, comprising: a device wafer, the device wafer including a first front surface integrated with a plurality of first chips; and a first back surface opposite to the first front surface; a first layer on the first front surface of the device wafer, the adhesive layer has a plurality of through holes exposing the first front surface; and a plurality of second chips bonded to the device wafer
  • the second chip is disposed on the adhesive layer, and the second chip is in one-to-one correspondence with the through hole and covers the top of the through hole.
  • the present invention forms an adhesive layer on the first front surface of the device wafer before the bonding of the device wafer and the second chip, and patterns the adhesive layer on the adhesive layer Forming a plurality of first through holes exposing the first front surface, the first through holes are in one-to-one correspondence with the second chip; and sequentially etching the first back surface of the device wafer and bonding a layer, in which a second via hole is formed in the device wafer, and a first via hole penetrating the second via hole is formed in the adhesive layer, the present invention is Forming a first through hole in the adhesive layer, and etching the first back surface to form a second through hole, can avoid the problem of serious lateral etching of the adhesive layer, thereby avoiding the first
  • the through hole opening size is larger than the size of the second through hole opening; correspondingly, when the first conductive post electrically connected to the second chip is formed in the first conductive through hole, the first step is facilitated Difficulty in forming the conductive pillars in the
  • the remaining adhesive layer covers the first front surface of the corresponding position of the second chip, and correspondingly, when subsequently forming the second chip on the first front surface
  • the encapsulation layer achieves good contact with the exposed first front surface of the second chip, thereby facilitating the function of improving insulation, sealing and moisture resistance of the encapsulation layer.
  • FIG. 4 are schematic structural diagrams corresponding to respective steps of a packaging method
  • FIG. 14 are schematic structural diagrams corresponding to respective steps in an embodiment of a wafer level system packaging method according to the present invention.
  • FIG. 17 are schematic structural diagrams corresponding to respective steps in another embodiment of the wafer level system packaging method of the present invention.
  • FIG. 18 is a schematic structural view of an embodiment of a package structure of the present invention.
  • Figure 19 is a schematic view showing the structure of another embodiment of the package structure of the present invention.
  • wafer level system packaging tends to result in a decrease in the performance and reliability of the package structure.
  • a wafer-level system packaging approach is now combined to analyze the reasons for its performance and reliability degradation.
  • 1 to 4 are schematic structural views corresponding to respective steps of a packaging method.
  • a first device wafer 10 is provided, the first device wafer 10 including a first front side 12 having a plurality of first chips 11 integrated therein and a first back side 13 opposite the first front side 12.
  • the first device wafer 10 is used as a wafer to be integrated in a packaging process. After the packaging process is completed, the first device wafer 10 is subjected to a package test and then cut to obtain a single finished chip.
  • a plurality of second chips 31 are provided, the second chip 31 including a second front surface (not labeled) having a semiconductor device and a second back surface (not labeled) opposite the second front surface, An adhesive layer 20 is formed on any of the second front surface and the second back surface.
  • the second chip 31 is used as a chip to be integrated in a packaging process, and a wafer level system package is realized by integrating a plurality of second chips 31 of different functions into one package structure.
  • the step of providing the second chip 31 includes: providing a plurality of second device wafers having different functions, each of the second device wafers including a third front surface integrated with the second chip 31 and a third front surface opposite to the front surface; an adhesive film formed on either one of the third front surface and the third back surface; and the plurality of second device wafers and the second device wafer The adhesive film is cut to obtain a plurality of second chips 31 having different functions and an adhesive layer 20 on either side of the second chips 31.
  • the adhesive layer 20 is fixed to the first front surface 12, and the adhesive bonding of the first device wafer 10 and the second chip 31 is achieved by the adhesive layer 20.
  • an encapsulation layer 40 covering the second chip 31 is formed on the first front surface 12 (shown in FIG. 2); after the encapsulation layer 40 is formed, the first back surface 13 is formed (FIG. 2). The first device wafer 10 is thinned.
  • the first back surface 13 and the adhesive layer 20 are sequentially etched by using a Through-Silicon Via (TSV) etching process to form a first via hole in the first device wafer 10.
  • TSV Through-Silicon Via
  • the wafer level system package mainly includes two important processes of physical connection and electrical connection.
  • the adhesive layer 20 is usually an organic material for realizing between the second chip 31 and the first device wafer 10 .
  • the process of the through-silicon via etching is usually a reactive ion dry etching (Reactive Ion Etching) process.
  • the opening size of the second via hole 25 is L2 (as shown in the figure). 4) and the topography are mainly determined according to the topography of the first through hole 15 and the etching process.
  • the adhesive layer 20 is an organic material, the etching gas is mainly O 2 , and most of the by-products generated in the dry etching process are gases, so the paste is etched In the process of the layer 20, the sidewall of the second via hole 25 is difficult to be protected, and the lateral etching is correspondingly severe; therefore, after the second via hole 25 is formed, the second via hole 25 is likely to have an opening.
  • the problem that the size L2 becomes large that is, the opening size L1 of the first through hole 15 (as shown in FIG. 4) is smaller than the opening size L2 of the second through hole 25.
  • the opening size L1 of the first through hole 15 refers to the dimension of the first through hole 15 along the second direction
  • the opening size L2 of the second through hole 25 refers to the second The size of the through hole 25 in the second direction.
  • a conductive pillar is further formed in the conductive via hole by a plating technique, since the opening size L1 of the first via hole 15 is smaller than the opening of the second via hole 25 a dimension L2, so that a gap is easily formed between the first device wafer 10 and the second chip 31 at a position close to the sidewall of the second via hole 25 (as shown by the dotted circle in FIG. 4), Correspondingly, the material of the conductive pillar is difficult to be well filled in the gap, and even the conductive pillar cannot be formed in the gap, thereby reducing the electrical connection performance of the conductive pillar, thereby leading to the performance of the package structure. And reliability is declining.
  • the present invention forms an adhesive layer on the first front surface of the device wafer and performs the bonding layer before the bonding of the device wafer and the second chip is realized.
  • the first back surface and the adhesive layer are formed by forming a second through hole in the device wafer and forming a first through hole penetrating the second through hole in the adhesive layer.
  • the present invention can avoid the occurrence of serious problem of lateral etching of the adhesive layer by forming a first through hole and then etching the first back surface to form a second through hole, thereby avoiding the first
  • the through hole opening size is larger than the size of the second through hole opening; correspondingly, when the first conductive post electrically connected to the second chip is formed in the first conductive through hole, the first step is facilitated
  • the formation of the conductive pillar in the first through hole is difficult, and the first conductive is improved Forming the first through hole quality, thereby improving the conductive pillars of the first electrical connection properties, to optimize the performance and reliability of the package structure.
  • FIG. 14 are schematic structural diagrams corresponding to respective steps in an embodiment of a wafer level system packaging method according to the present invention.
  • CMOS Wafer a device wafer 100 is provided, the device wafer 100 including a first front side 121 having a plurality of first chips 110 integrated therein and a first back side 122 opposite the first front side 121.
  • the device wafer 100 is a wafer fabricated to complete a device, and the device wafer 100 is used as a wafer to be integrated in a packaging process.
  • the device wafer 100 is adapted to implement a wafer level system package.
  • the wafer level system package refers to integrating a plurality of different functions of active components, passive components, MEMS, optical components and other components onto a device wafer, and then cutting to obtain a single package. technology.
  • Wafer-level system packaging has the advantages of high efficiency, high density, small size, high yield and excellent electrothermal performance, so it can meet the ever-increasing packaging process requirements.
  • the device wafer may also be adapted to implement a wafer level packaging process.
  • wafer level packaging refers to the technology of performing most or all of the package test procedures directly on the device wafer, and then cutting to obtain a single finished chip.
  • a photolithographic adhesive layer 200 is formed on the first front side 121 of the device wafer 100.
  • the adhesive layer 200 is a viscous material. After the subsequent patterning process, the remaining adhesive layer 200 is adapted to achieve the adhesive bonding of the device wafer 100 with the chip to be integrated.
  • the adhesive layer 200 is a lithographically viscous material, so that the adhesive layer 200 can be patterned by exposure and development, thereby avoiding the use of an additional etching process. Thereby, the process steps of subsequently patterning the adhesive layer 200 are simplified, which is advantageous for reducing the process cost and improving the packaging efficiency; moreover, by patterning the adhesive layer 200 by means of exposure and development, the adhesion can be avoided.
  • the viscosity of layer 200 has an effect.
  • the material of the adhesive layer 200 is a dry film.
  • the dry film is a viscous photoresist film used in the manufacture of a semiconductor chip package or a printed circuit board, and the dry film photoresist is manufactured by coating a solventless photoresist on the polyester.
  • a polyethylene film is further coated; when used, the polyethylene film is removed, and the solventless photoresist is pressed onto the substrate, and exposed and developed to be in the dry film photoresist. Form a graphic.
  • the material of the adhesive layer may also be polyimide (polyimide), polybenzoxazole (PBO) or benzocyclobutene (BCB).
  • the thickness T1 of the adhesive layer 200 should not be too small or too large. If the thickness T1 of the adhesive layer 200 is too small, the adhesive layer 200 is likely to be insufficient to achieve the adhesive bonding of the device wafer 100 with the chip to be integrated; if the thickness T1 of the adhesive layer 200 is excessive Large, correspondingly will increase the difficulty of the subsequent graphics process, and will also cause waste of process resources and time. Therefore, in the embodiment, the thickness T1 of the adhesive layer 200 is 5 ⁇ m to 100 ⁇ m according to actual process requirements.
  • the adhesive layer 200 is patterned, and a plurality of first through holes 201 exposing the first front surface 121 are formed in the adhesive layer 200.
  • the chip to be integrated is subsequently disposed on the remaining adhesive layer 200, and the first through hole 201 is used for subsequent formation and the chip to be integrated. Electrically connected conductive posts provide a spatial location.
  • the plurality of first through holes 201 are in one-to-one correspondence with the chip to be integrated.
  • the projection of the first through hole 201 on the first front surface 121 is located on one side of the first chip 110 to avoid the conductive pillar and the first chip electrically connected to the chip to be integrated.
  • the first through hole 201 is in one-to-one correspondence with the first chip 110 according to the actual process requirements, in order to achieve the normal use function of the package structure.
  • the one-to-one correspondence between the first through hole 201 and the first chip 110 means that the first through hole 201 is the same as the number of the first chip 110, and the first through hole 201 is
  • the first chip 110 has a preset relative positional relationship.
  • the extending direction of the first through hole 201 is a first direction
  • the second direction is perpendicular to the first direction and the normal direction of the first front surface 121 (see the BB1 direction in FIG. 6). Shown).
  • the material of the adhesive layer 200 is a dry film
  • the step of patterning the adhesive layer 200 includes: performing an exposure and development process on the adhesive layer 200.
  • the manner of patterning the adhesive layer 200 by an exposure development process is also advantageous for improving the accuracy of the opening size of the first through hole 201 in the second direction; moreover, after the exposure and development process, the remaining adhesive
  • the bonding layer 200 is still adhesive, so that the bonding of the device wafer 100 to the chip to be integrated can be achieved.
  • the remaining adhesive layer 200 only exposes the corresponding position of the first through hole 201.
  • a plurality of second chips 310 are provided.
  • the second chip 310 is used as a chip to be integrated in a wafer level system packaging process, and the plurality of second chips 310 have at least one type of function.
  • the function type of the second chip 310 is multiple, and the number of the second chips 310 is the same as the number of the first chips 110.
  • a wafer level system packaging scheme is realized by integrating a plurality of differently functioned second chips 310 into one package structure.
  • the functional types of the plurality of second chips may be the same, for example, when the device wafer is adapted to implement a wafer level packaging process.
  • the second chip 310 can be fabricated using integrated circuit fabrication techniques. Specifically, the second chip 310 may be a memory chip, a communication chip, a processor, or a logic chip. In other embodiments, the second chip may also be other functional chips.
  • the first through hole 201 is configured to provide a spatial position for subsequently forming a conductive pillar electrically connected to the second chip 310.
  • the second chip 310 and the first through hole 201 are respectively One-to-one correspondence.
  • the one-to-one correspondence between the second chip 310 and the first through hole 201 means that the first through hole 201 and the second chip 310 are the same in number, and the first through hole 201 is exposed.
  • a portion of the first front side 121 of the corresponding position of the second chip 310 (shown in FIG. 6).
  • the second chip 310 is disposed on the patterned remaining adhesive layer 200 , and the second chip 310 is in one-to-one correspondence with the first through hole 201 and covers the first through hole.
  • the adhesive layer 200 is a viscous material, and thus the device wafer 100 and the second chip can be realized by disposing the second chip 310 on the remaining adhesive layer 200. Bonding of 310, that is, bonding of the device wafer 100 and the second chip 310 is achieved by bonding.
  • the functions of the plurality of second chips 310 are different, so the plurality of second chips 310 can be obtained by cutting a plurality of device wafers with different functions, and the second chip 310 generally includes A semiconductor device such as an NMOS device or a PMOS device formed on a semiconductor substrate further includes a dielectric layer, a metal interconnection structure, and a pad.
  • the second chip 310 includes a second front surface (not labeled) having a device and a second back surface (not labeled) opposite the second front surface.
  • the second back surface refers to a bottom surface of the semiconductor substrate away from the side of the pad.
  • the second front surface or the second back surface of the second chip 310 may be disposed in the On the adhesive layer 200.
  • the second chip 310 covers the top of the first through hole 201, that is, the projection of the first through hole 201 on the second chip 310 is located on the second chip. 310, thereby providing a process basis for subsequently forming a conductive pillar electrically connected to the second chip 310, improving electrical connection performance of the conductive pillar.
  • the method further includes: forming an encapsulation layer 400 covering the second chip 310 on the first front surface 121 . .
  • the encapsulation layer 400 covers the second chip 310 to function as a seal and moisture proof, and can protect the second chip 310, thereby reducing the probability that the second chip 310 is damaged, contaminated or oxidized. In turn, it is advantageous to optimize the performance and reliability of the package structure formed after packaging.
  • the material of the encapsulation layer 400 is epoxy resin (Epoxy).
  • Epoxy resin has the advantages of low shrinkage, good adhesion, good corrosion resistance, excellent electrical properties and low cost, so it is widely used as packaging materials for electronic devices and integrated circuits.
  • the encapsulation layer may also be a photoresist, a prepreg or a Laser Activated Material.
  • the encapsulating layer 400 may be formed by a molding process using a liquid molding compound or a solid molding compound.
  • the filling performance of the injection molding process is better, and the molding compound can be better filled between the plurality of second chips 310, thereby improving the encapsulation effect of the encapsulation layer 400.
  • the injection molding process is a hot press injection molding process.
  • the encapsulation layer may also be formed using other processes.
  • the method further includes: performing a thinning process on the device wafer 100 through the first back surface 122 .
  • the process used in the thinning process may be one or more of a back grinding process, a chemical mechanical polishing (CMP) process, and a wet etching process.
  • CMP chemical mechanical polishing
  • the thinning process is performed after forming the encapsulation layer 400 as an example, so that the encapsulation layer 400 is in the thinning process to the second
  • the chip 310 functions as a fixing and supporting.
  • the encapsulation layer may also be formed after the thinning process. Specifically, after the second chip is disposed on the adhesive layer, the surface of the second chip facing away from the adhesive layer is temporarily bonded to the carrier wafer before the thinning process ( Carrier Wafer), the carrier wafer is temporarily fixed and supported to the plurality of second chips during the thinning process, and the probability of the second chip falling off is reduced; The method of bonding (Temporary Bonding) also facilitates subsequent separation of the second chip and the carrier wafer.
  • the second chip and the carrier wafer are subjected to a de-bonding process to remove the carrier wafer; after the debonding process, in the first An encapsulation layer covering the second chip is formed on the front side.
  • the first back surface 122 of the device wafer 100 is etched, and the device wafer 100 is formed in the device wafer 100.
  • the second through hole 101 through which the first through hole 201 penetrates, the second through hole 101 and the first through hole 201 constitute a first conductive through hole 151.
  • the first conductive via 151 is configured to provide a spatial position for subsequently forming a first conductive pillar electrically connected to the second chip 310.
  • the second via hole 201 is formed by a through silicon via (TSV) etching process, and the etching process may be one or two of dry etching and wet etching.
  • TSV through silicon via
  • the step of etching the device wafer 100 includes: etching a part of the device wafer 100 by a dry etching process; after the dry etching process, using a wet etching method The etch process etches the remaining thickness of the device wafer 100 to form a second via 101 through the device wafer 100.
  • the etching efficiency can be improved, and the etching loss of the adhesive layer 200 and the second chip 310 can be avoided, and the etching loss is also facilitated.
  • a small influence on the opening size of the first through hole 201 in the second direction (shown as BB1 direction in FIG. 6).
  • the adhesive layer 200 is patterned to form the first via hole 201, and the device wafer 100 is etched to form the second via hole 101, that is, Before the device wafer 100 is etched, the first via hole 201 is formed in the adhesive layer 200, and the first via hole 201 passes through the foregoing adhesive layer 200 along the opening size of the second direction.
  • the patterning process is set such that the opening size of the first via hole 201 along the second direction can meet the process requirement; therefore, sequentially etching the device wafer and the adhesive layer, respectively
  • the first through hole is formed in the device wafer, and the first through hole is formed in the adhesive layer to form a first through hole penetrating the second through hole.
  • the opening size of the 201 in the second direction is larger than the size of the opening of the second through hole 101 in the second direction, thereby avoiding a position close to the sidewall of the first through hole 201 (FIG. 10).
  • the imaginary coil shows a problem in which a gap is formed between the device wafer 100 and the second chip 310.
  • the performance of the package structure can be optimized by first forming the first via holes 201 to form the second via holes 101.
  • the wafer-level system packaging scheme is realized, which combines the wafer-level system packaging method with the traditional system packaging method, which completes the integration of multiple chips and realizes the packaging process on the device wafer. Manufacturing advantage.
  • the wafer level system packaging method further includes: etching a first back surface 122 of the device wafer 100, and forming a second conductive layer exposing the first chip 110 in the device wafer 100.
  • the via 152 is configured to provide a spatial position for subsequently forming a second conductive pillar electrically connected to the first chip 110.
  • the second via hole 101 and the second conductive via 152 are respectively formed in the device wafer 100 by different etching steps. It should be noted that, in this embodiment, the second through hole 101 is formed by forming the second conductive via 152 first.
  • a first back surface 122 above the first chip 110 is etched, a second conductive via 152 exposing the first chip 110 is formed in the device wafer 100, and a second conductive via is formed in the device wafer 100.
  • a filling layer (not shown) is formed in 152, the filling layer further covers the first back surface 122; a pattern layer (not shown) is formed on the filling layer, and the first layer is exposed in the pattern layer a pattern opening (not shown) of the filling layer above the via hole 201; the filling layer and the device wafer 100 are sequentially etched along the pattern opening by using the pattern layer as a mask, and the device wafer 100 is inside the device wafer 100 A second via hole 101 penetrating through the device wafer 100 and penetrating the first via hole 201 is formed; after the second via hole 101 is formed, the pattern layer and the filling layer are removed.
  • the second conductive via 152 has a small depth. By forming the second via 101 after forming the second conductive via 152, the filling in the second conductive via 152 can be reduced. The technical difficulty of the layer.
  • the second via hole may be formed after the second via hole is formed.
  • a first conductive pillar 510 electrically connected to the second chip 310 is formed in the first conductive via 151 (shown in FIG. 10).
  • the first conductive pillar 510 is used to implement electrical connection between the second chip 310 and other circuits.
  • a second conductive pillar electrically connected to the first chip 110 is also formed in the second conductive via 152 (shown in FIG. 10). 520.
  • the second conductive pillar 520 is electrically connected to the first chip 110 for realizing an electrical connection between the first chip 110 and other circuits.
  • the electrical connection between the second chip 310 and the first chip 110 can also be achieved by the first conductive pillar 510 and the second conductive pillar 520.
  • the materials of the first conductive pillar 510 and the second conductive pillar 520 are both copper. In other embodiments, the materials of the first conductive pillar and the second conductive pillar may also be conductive materials such as aluminum, tungsten, and titanium.
  • the first conductive via 151 and the second conductive via 152 are filled with a conductive material layer by using an electroplating process, and the conductive material layer further covers the first back surface 122 of the device wafer 100 (FIG. 10).
  • a planarization process is performed on the conductive material layer to remove the conductive material layer on the first back surface 122, and the conductive material in the first conductive via 151 is retained as the first conductive pillar 510.
  • the conductive material in the second conductive via 152 is retained as the second conductive pillar 520.
  • the second through hole 101 (shown in FIG. 10) is formed after the first through hole 201 (shown in FIG. 10) is formed, at a position close to the side wall of the first through hole 201 ( As shown by the dashed circle in FIG. 10, the probability of forming a gap between the device wafer 100 and the second chip 310 is low, and correspondingly, the filling effect of the conductive material in the first through hole 201 is The quality is better, thereby facilitating the improvement of the electrical connection performance of the first conductive pillar 510, thereby optimizing the performance and reliability of the package structure.
  • the method further includes: forming a first back surface 122 (shown in FIG. 10) of the device wafer 100.
  • a first pad 610 covering the first conductive pillar 510 and a second pad 620 covering the second conductive pillar 520 are covered.
  • the second chip 310 is electrically connected to other circuits through the first conductive pillar 510 and the first bonding pad 610, and the first chip 110 passes through the second conductive pillar 520 and the second bonding pad 620 and other The circuit is electrically connected.
  • the materials of the first pad 610 and the second pad 620 are all aluminum. In other embodiments, the material of the first pad and the second pad may also be a conductive material such as copper.
  • a passivation layer 700 is formed on the first back surface 122 (shown in FIG. 10), and the passivation layer 700 is formed.
  • the top of the first pad 610 and the second pad 620 are also covered; the passivation layer 700 is patterned to expose a portion of the first pad 610 and a portion of the second pad 620.
  • the passivation layer 700 covers the first back surface 122, thereby preventing external impurities (such as sodium ions), ionic charges, and moisture from affecting the device, thereby improving device performance and stability, and improving package structure performance and reliability.
  • external impurities such as sodium ions
  • ionic charges such as sodium ions
  • moisture from affecting the device, thereby improving device performance and stability, and improving package structure performance and reliability.
  • the material of the passivation layer 700 may be phosphorous silicon glass (PSG), silicon oxide, silicon nitride, silicon oxynitride or polyimide.
  • PSG phosphorous silicon glass
  • silicon oxide silicon oxide
  • silicon nitride silicon oxynitride
  • polyimide polyimide
  • the passivation layer 700 is patterned by an etching process, and a first opening 701 (shown in FIG. 14) and a second opening 702 are formed in the passivation layer 700 (as shown in FIG. 14).
  • the first opening 701 exposes a portion of the first pad 610
  • the second opening 702 exposes a portion of the second pad 620, so that the first pad 610 exposed through the first opening 701 can be exposed.
  • An electrical connection between the second chip 310 and other circuits is implemented, and the second pad 620 exposed through the second opening 702 realizes an electrical connection between the first chip 110 and other circuits, and further Electrical connection between the second chip 310 and the first chip 110 can be achieved by the exposed first pad 610 and second pad 620.
  • FIG. 15 to FIG. 17 are schematic structural diagrams corresponding to respective steps in another embodiment of the wafer level system packaging method of the present invention.
  • the same points of the embodiment are the same as those of the foregoing embodiment, and details are not described herein again.
  • the difference between this embodiment and the foregoing embodiment is that, after the adhesive layer 830 is patterned as shown in FIG. 17, the remaining adhesive layer 830 covers the first front surface 821 of the corresponding position of the second chip 910. A plurality of first through holes 801 are formed in the remaining adhesive layer 830 , and the first through holes 801 are in one-to-one correspondence with the second chip 910 .
  • the encapsulation layer 900 covers the first front surface 821 exposed by the second chip 910, so the encapsulation layer 900 can be
  • the first front side 821 achieves good contact, and the encapsulation layer 900 can better achieve insulation, sealing, and moisture resistance.
  • the remaining adhesive layer 830 covers the corresponding position of the second chip 910.
  • a front surface 801 and the first through hole 801 is in one-to-one correspondence with the second chip 910.
  • the first through hole 801 is configured to provide a spatial position for subsequently forming a conductive post electrically connected to the second chip 910. .
  • the one-to-one correspondence between the first through hole 801 and the second chip 910 means that the first through hole 801 and the second chip 910 are equal in number, and the first through hole 801 is exposed.
  • the second chip 910 corresponds to a portion of the first front side 821 of the location.
  • the remaining adhesive layer 830 covers at least a portion of the first chip 810, thereby reducing the corresponding first chip 810 and the second The spacing of the chip 910 in a direction parallel to the first front side 821, which in turn facilitates process integration.
  • the remaining adhesive layer may also be on the first front side of one side of the first chip.
  • the size of the remaining adhesive layer 830 along the direction parallel to the first front surface 821 depends on the size of the second chip 910 along the direction parallel to the first front surface 821, and may also The adjustment is performed according to the size of the first chip 810 in a direction parallel to the first front surface 821.
  • the present invention also provides a package structure.
  • FIG. 18 there is shown a block diagram of an embodiment of a package structure of the present invention.
  • the package structure includes: a device wafer 105, the device wafer 105 includes a first front surface 111 in which a plurality of first chips 205 are integrated, and a first back surface 112 opposite to the first front surface 111; an adhesive layer 305, located in the first front surface 111 of the device wafer 105, the adhesive layer 305 has a plurality of first vias 306 exposing the first front surface 111; bonding with the device wafer 105 a plurality of second chips 320, the second chip 320 is disposed on the adhesive layer 305, and the second chip 320 is in one-to-one correspondence with the first through holes 306 and covers the first through holes 306. top.
  • the device wafer 105 is a wafer fabricated to complete the device, and the device wafer 105 is used as a wafer to be integrated in a packaging process.
  • the device wafer 105 is adapted to implement a wafer level system package.
  • the wafer level system package refers to integrating a plurality of different functions of active components, passive components, MEMS, optical components and other components onto a device wafer, and then cutting to obtain a single package. technology.
  • Wafer-level system packaging has the advantages of high efficiency, high density, small size, high yield and excellent electrothermal performance, so it can meet the ever-increasing packaging process requirements.
  • the device wafer may also be adapted to implement a wafer level packaging process.
  • wafer level packaging refers to the technology of performing most or all of the package test procedures directly on the device wafer, and then cutting to obtain a single finished chip.
  • the adhesive layer 305 is made of a viscous material for bonding the device wafer 105 and the second chip 320, and the adhesive layer 305 has a plurality of exposed first front faces 111.
  • the first through hole 306 is configured to provide a spatial position for forming a conductive post electrically connected to the second chip 320.
  • the material of the adhesive layer 305 is a lithographic viscous material, so the first through hole 306 can be formed by a patterning method for exposing and developing the adhesive layer 305, which can be avoided accordingly.
  • the use of an additional etching process simplifies the process steps of forming the first via hole 306, which is advantageous for reducing the process cost and improving the packaging efficiency; moreover, the adhesive layer 305 can be avoided by exposure and development.
  • the viscosity has an effect.
  • the material of the adhesive layer 305 is a dry film.
  • the material of the adhesive layer may also be polyimide, polybenzoxazole or benzocyclobutene.
  • the thickness (not labeled) of the adhesive layer 305 should not be too small or too large. If the thickness of the adhesive layer 305 is too small, the adhesive layer 305 is likely to be insufficient to achieve the adhesive bonding of the device wafer 105 and the second chip 320; if the thickness of the adhesive layer 305 If it is too large, the process difficulty of forming the first through hole 306 is increased correspondingly, and waste of process resources and time is also caused. Therefore, in the embodiment, the thickness of the adhesive layer 305 is 5 ⁇ m to 100 ⁇ m according to actual process requirements.
  • the first through hole 306 is configured to provide a spatial position for forming a conductive pillar electrically connected to the second chip 320, so that the projection of the first through hole 306 at the first front surface 111 is located.
  • One side of the first chip 205 avoids bridging between the conductive post electrically connected to the second chip 320 and the first chip 205, and in order to realize the normal use function of the package structure, according to an actual process It is required that the first through holes 306 are in one-to-one correspondence with the first chip 205.
  • the one-to-one correspondence between the first through hole 306 and the first chip 205 means that the first through hole 306 is the same as the first chip 205, and the first through hole 306 is The first chip 205 has a preset relative positional relationship.
  • the adhesive layer 305 exposes only the first front surface 111 corresponding to the first through hole 306.
  • the extending direction of the first through hole 306 is a first direction
  • the second direction is perpendicular to the first direction and the normal direction of the first front surface 111 (such as the CC1 direction in FIG. 18). Shown).
  • the second chip 320 is used as a chip to be integrated in a wafer level system packaging process, and the plurality of second chips 320 have at least one type of function.
  • the plurality of second chips 320 have multiple types of functions, and the number of the second chips 320 is the same as the number of the first chips 205.
  • a wafer level system packaging scheme is realized by integrating a plurality of different functions of the second chip 320 into one package structure.
  • the functional types of the plurality of second chips may be the same, for example, when the device wafer is adapted to implement a wafer level packaging process.
  • the second chip 320 can be fabricated using integrated circuit fabrication techniques. Specifically, the second chip 320 may be a memory chip, a communication chip, a processor, or a logic chip. In other embodiments, the second chip may also be other functional chips.
  • the first through hole 306 is configured to provide a spatial position for forming a conductive pillar electrically connected to the second chip 320.
  • the second chip 320 and the first through hole 306 are A correspondence.
  • the one-to-one correspondence between the second chip 320 and the first through hole 306 means that the number of the second chip 320 and the first through hole 306 are equal, and the second chip 320 covers the same The top of the first through hole 306 is described.
  • the functions of the plurality of second chips 320 are different, so the plurality of second chips 320 can be obtained by cutting a plurality of device wafers with different functions, and the second chip 320 is also generally A device including an NMOS device or a PMOS device on a semiconductor substrate, and a structure including a dielectric layer, a metal interconnection structure, and a pad.
  • the second chip 320 includes a second front surface (not labeled) having a semiconductor device and a second back surface (not labeled) opposite the second front surface.
  • the second back surface refers to a bottom surface of the semiconductor substrate away from the side of the pad.
  • the second front surface or the second back surface of the second chip 320 is disposed on the adhesive layer 305 according to actual process requirements.
  • the package structure in order to enable electrical connection between the second chip 320 and other circuits, the package structure generally includes the device wafer 105 and the first via 306 and the The conductive process of the two chips 320 is electrically connected.
  • the packaging process of the package structure generally includes etching a first back surface 112 of the device wafer 105, and forming the first pass in the device wafer 105. a second through hole through which the hole 306 passes.
  • the first via hole 306 is formed first, and the device wafer 105 is etched to form the second via hole.
  • the opening size of the first through hole 306 along the second direction is set by a patterning process of the adhesive layer 305, so that the opening size of the first through hole 306 along the second direction is satisfied.
  • the package structure may be formed by using the packaging method described in the first embodiment, or may be formed by other packaging methods.
  • the package structure may be formed by using the packaging method described in the first embodiment, or may be formed by other packaging methods.
  • the package structure reference may be made to the corresponding description in the first embodiment, and the details are not described herein again.
  • FIG. 19 there is shown a block diagram of another embodiment of the package structure of the present invention.
  • the same points of the embodiment are the same as those of the foregoing embodiment, and details are not described herein again.
  • the embodiment is different from the previous embodiment in that the adhesive layer 705 covers the first front surface 411 of the corresponding position of the second chip 720, and the first through hole 706 in the adhesive layer 705 exposes the The second chip 720 corresponds to a portion of the first front side 411 of the location.
  • the package structure further includes an encapsulation layer covering the second chip 720
  • the encapsulation layer further covers the exposed first front surface 411 of the second chip 720, so the encapsulation layer can be
  • the first front side 411 achieves good contact, and the encapsulating layer can better achieve insulation, sealing and moisture resistance.
  • the adhesive layer 705 covers the first front surface 411 of the corresponding position of the second chip 720, and the first The through holes 706 are in one-to-one correspondence with the second chip 720, and the first through holes 706 are used to provide a spatial position for forming a conductive post electrically connected to the second chip 720.
  • the first through hole 706 and the second chip 720 are in one-to-one correspondence: the first through hole 706 and the second chip 720 are equal in number, and the second chip 720 covers the The top of the first through hole 706.
  • the adhesive layer 705 covers at least a portion of the first chip 605, thereby reducing the corresponding first chip 605 and second chip 720 in parallel with the first front surface 411.
  • the spacing of the directions helps to improve process integration.
  • the adhesive layer may also be on the first front side of one side of the first chip.
  • the size of the adhesive layer 705 in a direction parallel to the first front surface 411 is determined according to the size of the second chip 720 in a direction parallel to the first front surface 411, and may also be The first chip 605 is adjusted in a dimension parallel to the direction of the first front surface 411.
  • the package structure may be formed by using the packaging method described in the second embodiment, or may be formed by other packaging methods.
  • the specific description of the package structure may be combined with the corresponding descriptions in the first embodiment and the second embodiment, and the details are not described herein again.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Ceramic Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Dicing (AREA)
  • Micromachines (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

一种晶圆级系统封装方法及封装结构，方法包括：提供器件晶圆，包括集成有多个第一芯片（11）的第一正面（12）以及与第一正面（12）相背的第一背面（13）；提供多个第二芯片（31）；在第一正面形成粘合层；图形化粘合层，在粘合层内形成多个露出第一正面的第一通孔；将第二芯片设置于剩余粘合层上，第二芯片与第一通孔一一对应且覆盖第一通孔顶部，并使器件晶圆和第二芯片键合；刻蚀第一背面，在器件晶圆内形成与第一通孔相贯通的第二通孔，第二通孔和第一通孔构成第一导电通孔；在第一导电通孔内形成与第二芯片电连接的第一导电柱。通过先形成第一通孔再形成第二通孔，避免出现第一通孔开口尺寸大于第二通孔开口尺寸的问题，从而改善第一导电柱的电性连接性能。

Description

晶圆级系统封装方法及封装结构 技术领域
本发明涉及半导体制造领域，尤其涉及一种晶圆级系统封装方法及封装结构。
 背景技术
随着超大规模集成电路的发展趋势，集成电路特征尺寸持续减小，人们对集成电路的封装技术的要求相应也不断提高。现有的封装技术包括球栅阵列封装(Ball Grid Array，BGA)、芯片尺寸封装(Chip Scale Package，CSP)、晶圆级封装(Wafer Level Package ，WLP)、三维封装(3D) 和系统封装(SiP)等。
系统封装可以将多个不同功能的有源元件、无源元件、微机电系统（MEMS）、光学元件等其他元件组合到一个单元中，形成一个可提供多种功能的系统或子系统，允许异质IC集成。相比于系统级芯片（System on Chip，SoC），系统封装的集成相对简单，设计周期和面市周期更短，成本较低，可以实现更复杂的系统。
目前，为了满足集成电路封装的更低成本、更可靠、更快及更高密度的目标，先进的封装方法主要采用晶圆级系统封装（Wafer Level Package System in Package，WLPSiP），与传统的系统封装相比，晶圆级系统封装是在器件晶圆上完成封装集成制程，具有大幅减小封装结构的面积、降低制造成本、优化电性能、批次制造等优势，可明显的降低工作量与设备的需求。
但是，现有技术晶圆级系统封装容易导致封装结构的性能和可靠性下降。
 技术问题
本发明解决的问题是提供一种晶圆级系统封装方法及封装结构，提高封装结构的性能和可靠性。
 技术解决方案
为解决上述问题，本发明提供一种晶圆级系统封装方法，包括：提供器件晶圆，所述器件晶圆包括集成有多个第一芯片的第一正面以及与所述第一正面相背的第一背面；提供多个第二芯片；在所述器件晶圆的第一正面形成可光刻的粘合层；图形化所述粘合层，在所述粘合层内形成多个露出所述第一正面的第一通孔；图形化所述粘合层后，将所述第二芯片设置于剩余粘合层上，所述第二芯片与所述第一通孔一一对应且覆盖所述第一通孔的顶部，并使所述器件晶圆和所述第二芯片键合；刻蚀所述器件晶圆的第一背面，在所述器件晶圆内形成贯穿所述器件晶圆且与所述第一通孔相贯通的第二通孔，所述第二通孔和所述第一通孔构成第一导电通；在所述第一导电通孔内形成与所述第二芯片电连接的第一导电柱。
相应的，本发明还提供一种封装结构，包括：器件晶圆，所述器件晶圆包括集成有多个第一芯片的第一正面以及与所述第一正面相背的第一背面；粘合层，位于所述器件晶圆的第一正面，所述粘合层内具有多个露出所述第一正面的通孔；与所述器件晶圆相键合的多个第二芯片，所述第二芯片设置于所述粘合层上，所述第二芯片与所述通孔一一对应且覆盖所述通孔的顶部。
 有益效果
与现有技术相比，本发明的技术方案具有以下优点：
本发明在实现所述器件晶圆和所述第二芯片的键合之前，在所述器件晶圆的第一正面形成粘合层，并对所述粘合层进行图形化，在所述粘合层内形成多个露出所述第一正面的第一通孔，所述第一通孔与所述第二芯片一一对应；与依次刻蚀所述器件晶圆的第一背面和粘合层，先后在所述器件晶圆内形成第二通孔、在所述粘合层内形成与所述第二通孔相贯通的第一通孔的方案相比，本发明通过先在所述粘合层内形成第一通孔，再刻蚀所述第一背面以形成第二通孔的方案，能够避免出现所述粘合层的横向刻蚀严重的问题，从而避免出现所述第一通孔开口尺寸大于所述第二通孔开口尺寸的问题；相应的，后续在第一导电通孔内形成与所述第二芯片电连接的第一导电柱时，有利于降低所述第一导电柱在所述第一通孔内的形成难度、提高所述第一导电柱在所述第一通孔内的形成质量，从而改善所述第一导电柱的电性连接性能，进而优化封装结构的性能和可靠性。
可选方案中，图形化所述粘合层后，剩余粘合层覆盖所述第二芯片对应位置的第一正面，相应的，当后续在所述第一正面形成覆盖所述第二芯片的封装层时，所述封装层与所述第二芯片露出的第一正面实现良好的接触，从而有利于提高所述封装层的绝缘、密封及防潮的作用。
 附图说明
图1至图4是一种封装方法各步骤对应的结构示意图；
图5至图14是本发明晶圆级系统封装方法一实施例中各步骤对应的结构示意图；
图15至图17是本发明晶圆级系统封装方法另一实施例中各步骤对应的结构示意图；
图18是本发明封装结构一实施例的结构示意图；
图19是本发明封装结构另一实施例的结构示意图。
 本发明的实施方式
由背景技术可知，晶圆级系统封装容易导致封装结构的性能和可靠性下降。现结合一种晶圆级系统封装方法分析其性能和可靠性下降的原因。
图1至图4是一种封装方法各步骤对应的结构示意图。
参考图1，提供第一器件晶圆10，所述第一器件晶圆10包括集成有多个第一芯片11的第一正面12以及与所述第一正面12相背的第一背面13。
所述第一器件晶圆10用于作为封装工艺中的待集成晶圆，在完成封装制程后，对所述第一器件晶圆10进行封装测试后再进行切割以获得单个成品芯片。
参考图2，提供多个第二芯片31，所述第二芯片31包括具有半导体器件的第二正面（未标示）以及与所述第二正面相背的第二背面（未标示），所述第二正面和第二背面中的任一面上形成有粘合层20。
所述第二芯片31用于作为封装工艺中的待集成芯片，通过将多个不同功能的第二芯片31整合至一个封装结构中，以实现晶圆级系统封装。
目前，提供所述第二芯片31的步骤包括：提供多个功能不同的第二器件晶圆，每一个第二器件晶圆包括集成有所述第二芯片31的第三正面以及与所述第三正面相背的第三背面；在所述第三正面和第三背面中的任一面上形成粘合膜；对所述多个第二器件晶圆以及位于所述第二器件晶圆上的粘合膜进行切割，获得多个功能不同的第二芯片31以及位于所述第二芯片31任一面上的粘合层20。
继续参考图2，将所述粘合层20固定于所述第一正面12上，通过所述粘合层20实现所述第一器件晶圆10和所述第二芯片31的粘贴结合。
参考图3，在所述第一正面12（如图2所示）形成覆盖所述第二芯片31的封装层40；形成所述封装层40后，通过所述第一背面13（如图2所示）对所述第一器件晶圆10进行减薄处理。
参考图4，采用硅通孔（Through-Silicon Via，TSV）刻蚀工艺，依次刻蚀所述第一背面13和粘合层20，在所述第一器件晶圆10内形成第一通孔15，在所述粘合层20内形成与所述第一通孔15相贯通且露出所述第二芯片31的第二通孔25，所述第二通孔25和所述第一通孔15构成导电通孔；其中，所述导电通孔的延伸方向为第一方向，与所述第一方向以及所述第一正面12（如图2所示）法线方向相垂直的为第二方向（如图4中AA1方向所示）。
晶圆级系统封装主要包括物理连接和电性连接这两个重要工艺，所述粘合层20通常为有机材料，用于实现所述第二芯片31和所述第一器件晶圆10之间的物理连接，并通过硅通孔刻蚀和电镀技术实现所述第一芯片11和第二芯片31与其他电路之间的电性连接、以及所述第一芯片11和第二芯片31之间的电性连接。
硅通孔刻蚀所采用的工艺通常为反应离子干法刻蚀（Reactive Ion Etching）工艺，刻蚀形成所述第一通孔15后，所述第二通孔25的开口尺寸L2（如图4所示）和形貌主要根据所述第一通孔15的形貌和刻蚀制程而定。
其中，在干法刻蚀过程中会生成不和刻蚀气体反应的聚合物（Polymer）副产物，所述副产物容易附着于开口侧壁以阻止横向刻蚀（即沿所述第二方向的刻蚀），但是由于所述粘合层20为有机材料，所述刻蚀气体主要为O 2，且干法刻蚀过程中所生成的副产物大部分为气体，因此在刻蚀所述粘合层20的过程中，所述第二通孔25的侧壁难以得到保护，横向刻蚀相应较为严重；所以，形成所述第二通孔25后，所述第二通孔25容易出现开口尺寸L2变大的问题，即所述第一通孔15的开口尺寸L1（如图4所示）小于所述第二通孔25的开口尺寸L2。其中，所述第一通孔15的开口尺寸L1指的是所述第一通孔15沿所述第二方向的尺寸，所述第二通孔25的开口尺寸L2指的是所述第二通孔25沿所述第二方向的尺寸。
而且，当所述粘合层20的厚度较大时，所述第二通孔25出现开口尺寸L2变大的问题更为明显。
为了实现半导体器件之间的电性连接，后续还需通过电镀技术在所述导电通孔内形成导电柱，由于所述第一通孔15的开口尺寸L1小于所述第二通孔25的开口尺寸L2，因此在靠近所述第二通孔25侧壁的位置处，所述第一器件晶圆10和所述第二芯片31之间容易形成缝隙（如图4中虚线圈所示），相应的，所述导电柱的材料难以较好地填充于所述缝隙中，甚至所述缝隙中无法形成所述导电柱，从而降低所述导电柱的电性连接性能，进而导致封装结构的性能和可靠性下降。
为了解决所述技术问题，本发明在实现所述器件晶圆和所述第二芯片的键合之前，在所述器件晶圆的第一正面形成粘合层，并对所述粘合层进行图形化，在所述粘合层内形成多个露出所述第一正面的第一通孔，所述第一通孔与所述第二芯片一一对应；与依次刻蚀所述器件晶圆的第一背面和粘合层，先后在所述器件晶圆内形成第二通孔、在所述粘合层内形成与所述第二通孔相贯通的第一通孔的方案相比，本发明通过先形成第一通孔，再刻蚀所述第一背面以形成第二通孔的方案，能够避免出现所述粘合层的横向刻蚀严重的问题，从而避免出现所述第一通孔开口尺寸大于所述第二通孔开口尺寸的问题；相应的，后续在第一导电通孔内形成与所述第二芯片电连接的第一导电柱时，有利于降低所述第一导电柱在所述第一通孔内的形成难度、提高所述第一导电柱在所述第一通孔内的形成质量，从而改善所述第一导电柱的电性连接性能，进而优化封装结构的性能和可靠性。
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
图5至图14是本发明晶圆级系统封装方法一实施例中各步骤对应的结构示意图。
参考图5，提供器件晶圆（CMOS Wafer）100，所述器件晶圆100包括集成有多个第一芯片110的第一正面121以及与所述第一正面121相背的第一背面122。
所述器件晶圆100为完成器件制作的晶圆，所述器件晶圆100用于作为封装工艺中的待集成晶圆。
本实施例中，所述器件晶圆100适于实现晶圆级系统封装。其中，晶圆级系统封装指的是将多个不同功能的有源元件、无源元件、微机电系统、光学元件等其他元件集成至一个器件晶圆上，再进行切割以获得单个封装体的技术。晶圆级系统封装具有高效率、高密度、体积小、成品率高和电热性能优良等优点，因此能够满足不断提高的封装工艺要求。
在其他实施例中，所述器件晶圆还可适于实现晶圆级封装工艺。其中，晶圆级封装指的是直接在器件晶圆上进行大部分或全部的封装测试程序，再进行切割以获得单个成品芯片的技术。
继续参考图5，在所述器件晶圆100的第一正面121形成可光刻的粘合层200。
所述粘合层200为粘性材料，经后续的图形化工艺后，剩余粘合层200适于实现所述器件晶圆100与待集成芯片的粘贴结合。
本实施例中，所述粘合层200为可光刻的粘性材料，因此后续通过曝光显影的方式即可对所述粘合层200进行图形化处理，相应可以避免额外刻蚀工艺的采用，从而简化了后续图形化所述粘合层200的工艺步骤，有利于降低工艺成本、提高封装效率；而且，通过曝光显影的方式图形化所述粘合层200，还能够避免对所述粘合层200的粘性产生影响。
为此，本实施例中，所述粘合层200的材料为干膜（Dry film）。其中，干膜是一种用于半导体芯片封装或印刷电路板制造时所采用的具有粘性的光致抗蚀膜，干膜光刻胶的制造是将无溶剂型光致抗蚀剂涂在涤纶片基上，再覆上聚乙烯薄膜；使用时揭去聚乙烯薄膜，把无溶剂型光致抗蚀剂压于基版上，经曝光显影处理，即可在所述干膜光刻胶内形成图形。
在其他实施例中，所述粘合层的材料还可以为聚酰亚胺（Polyimide）、聚苯并恶唑(PBO)或苯并环丁烯(BCB)。
需要说明的是，所述粘合层200的厚度T1不宜过小，也不宜过大。如果所述粘合层200的厚度T1过小，则容易导致所述粘合层200不足以实现所述器件晶圆100与待集成芯片的粘贴结合；如果所述粘合层200的厚度T1过大，相应会增加后续图形化工艺的难度，且还会造成工艺资源和时间的浪费。为此，本实施例中，根据实际工艺需求，所述粘合层200的厚度T1为5μm至100μm。
参考图6，图形化所述粘合层200，在所述粘合层200内形成多个露出所述第一正面121的第一通孔201。
为了实现所述器件晶圆100与待集成芯片的粘贴结合，后续将所述待集成芯片设置于剩余粘合层200上，所述第一通孔201用于为后续形成与所述待集成芯片电连接的导电柱提供空间位置。相应的，后续将所述待集成芯片设置于剩余粘合层200上后，所述多个第一通孔201与所述待集成芯片一一对应。
本实施例中，所述第一通孔201在所述第一正面121的投影位于所述第一芯片110的一侧，以免与所述待集成芯片电连接的导电柱与所述第一芯片110发生桥接，且为了实现所述封装结构的正常使用功能，根据实际工艺需求，所述第一通孔201与所述第一芯片110一一对应。其中，所述第一通孔201与所述第一芯片110一一对应指的是：所述第一通孔201与所述第一芯片110的数量相同，所述第一通孔201与所述第一芯片110具有预设相对位置关系。
本实施例中，所述第一通孔201的延伸方向为第一方向，与所述第一方向以及所述第一正面121法线方向相垂直的为第二方向（如图6中BB1方向所示）。
具体地，所述粘合层200的材料为干膜，相应的，图形化所述粘合层200的步骤包括：对所述粘合层200进行曝光显影工艺。通过曝光显影工艺图形化所述粘合层200的方式，还有利于提高所述第一通孔201在所述第二方向的开口尺寸的精度；而且，在所述曝光显影工艺后，剩余粘合层200仍具有粘性，从而能够实现所述器件晶圆100与所述待集成芯片的粘贴结合。
本实施例中，为了降低图形化所述粘合层200的工艺难度和工艺成本，图形化所述粘合层200后，剩余粘合层200仅露出所述第一通孔201对应位置的第一正面121。
参考图7，提供多个第二芯片310。
所述第二芯片310用于作为晶圆级系统封装工艺中的待集成芯片，所述多个第二芯片310的功能类型至少为一种。
本实施例中，所述第二芯片310的功能类型为多种，且所述第二芯片310的数量与所述第一芯片110的数量相同。通过将多个不同功能的第二芯片310整合至一个封装结构中，从而实现了晶圆级系统封装方案。
在其他实施例中，例如当所述器件晶圆适于实现晶圆级封装工艺时，所述多个第二芯片的功能类型还可以相同。
所述第二芯片310可以采用集成电路制作技术所制成。具体地，所述第二芯片310可以为存储芯片、通讯芯片、处理器或逻辑芯片。在其他实施例中，所述第二芯片还可以是其他功能芯片。
本实施例中，所述第一通孔201用于为后续形成与所述第二芯片310电连接的导电柱提供空间位置，相应的，所述第二芯片310与所述第一通孔201一一对应。其中，所述第二芯片310与所述第一通孔201一一对应指的是：所述第一通孔201与所述第二芯片310的数量相同，所述第一通孔201露出所述第二芯片310对应位置的部分第一正面121（如图6所示）。
继续参考图7，将所述第二芯片310设置于图形化后的剩余粘合层200上，所述第二芯片310与所述第一通孔201一一对应且覆盖所述第一通孔201的顶部，并使所述器件晶圆100和所述第二芯片310实现键合。
本实施例中，所述粘合层200为粘性材料，因此通过将所述第二芯片310设置于所述剩余粘合层200上，即可实现所述器件晶圆100和所述第二芯片310的粘贴结合，即采用粘贴结合的方式实现所述器件晶圆100和所述第二芯片310的键合。
需要说明的是，所述多个第二芯片310的功能不同，因此所述多个第二芯片310可以通过对不同功能的多个器件晶圆进行切割所获得，所述第二芯片310通常包括形成于半导体衬底上的NMOS器件或PMOS器件等半导体器件，还包括介质层、金属互连结构和焊盘等结构。
本实施例中，所述第二芯片310包括具有器件的第二正面（未标示）以及与所述第二正面相背的第二背面（未标示）。其中，所述第二背面指的是远离所述焊盘一侧的半导体衬底的底部表面。
相应的，将所述第二芯片310设置于所述剩余粘合层200上的步骤中，根据实际工艺需求，可以将所述第二芯片310的第二正面或所述第二背面设置于所述粘合层200上。
还需要说明的是，所述第二芯片310覆盖所述第一通孔201的顶部，也就是说，所述第一通孔201在所述第二芯片310上的投影位于所述第二芯片310内，从而为后续形成与所述第二芯片310电连接的导电柱提供工艺基础，提高所述导电柱的电连接性能。
结合参考图8，本实施例中，使所述器件晶圆100和所述第二芯片310键合后，还包括：在所述第一正面121形成覆盖所述第二芯片310的封装层400。
所述封装层400覆盖所述第二芯片310，从而起到密封和防潮的作用，能够保护所述第二芯片310，从而降低所述第二芯片310发生受损、被污染或被氧化的概率，进而有利于优化封装后所形成封装结构的性能和可靠性。
本实施例中，所述封装层400的材料为环氧树脂(Epoxy)。环氧树脂具有收缩率低、粘结性好、耐腐蚀性好、电性能优异及成本较低等优点，因此广泛用作电子器件和集成电路的封装材料。
在其他实施例中，所述封装层还可以为光刻胶、压合片(Prepreg)或激光活化材料(Laser Activated Material)。
本实施例中，可以通过注塑工艺，使用液体的塑封料或者固体的塑封料，以形成所述封装层400。注塑工艺的填充性能较好，可以使所述塑封料较好地填充于多个第二芯片310之间，从而提高所述封装层400的封装效果。
具体地，所述注塑工艺为热压注塑成型工艺。在其他实施例中，还可以采用其他工艺形成所述封装层。
结合参考图9，形成所述封装层400后，还包括：通过所述第一背面122，对所述器件晶圆100进行减薄处理。
通过对所述器件晶圆100进行减薄处理，以减小所述器件晶圆100的厚度，从而改善所述器件晶圆100的散热效果，且有利于进行后续的封装工艺以及减小封装后所获得封装结构的整体厚度。
本实施例中，所述减薄处理所采用的工艺可以为背部研磨工艺、化学机械抛光 (Chemical Mechanical Polishing，CMP)工艺和湿法刻蚀工艺中的一种或多种。
需要说明的是，本实施例中，以先形成所述封装层400后进行所述减薄处理为例进行说明，从而使所述封装层400在所述减薄处理过程中对所述第二芯片310起到固定和支撑作用。
在其他实施例中，还可以在所述减薄处理后形成所述封装层。具体地，将所述第二芯片设置于所述粘合层上后，在所述减薄处理之前，将所述第二芯片背向所述粘合层的表面临时键合于载体晶圆（Carrier Wafer）上，使所述载体晶圆在所述减薄处理过程中对所述多个第二芯片起到临时固定和支撑的作用，降低所述第二芯片发生脱落的概率；而且通过临时键合（Temporary Bonding）的方式，还便于后续将所述第二芯片和所述载体晶圆进行分离。
相应的，在所述减薄处理后，对所述第二芯片和载体晶圆进行解键合（De-bonding）处理，以去除所述载体晶圆；在所述解键合处理后，在所述第一正面形成覆盖所述第二芯片的封装层。
参考图10，形成所述封装层400并完成减薄处理后，刻蚀所述器件晶圆100的第一背面122，在所述器件晶圆100内形成贯穿所述器件晶圆100且与所述第一通孔201相贯通的第二通孔101，所述第二通孔101和所述第一通孔201构成第一导电通孔151。
所述第一导电通孔151用于为后续形成与所述第二芯片310电连接的第一导电柱提供空间位置。
具体地，采用硅穿孔（Through Silicon Via，TSV）刻蚀工艺形成所述第二通孔201，所述刻蚀工艺可以为干法刻蚀和湿法刻蚀中的一种或两种。
本实施例中，刻蚀所述器件晶圆100的步骤包括：采用干法刻蚀工艺，刻蚀部分厚度的所述器件晶圆100；在所述干法刻蚀工艺后，采用湿法刻蚀工艺刻蚀剩余厚度的所述器件晶圆100，以形成贯穿所述器件晶圆100的第二通孔101。
通过先采用干法刻蚀工艺再采用湿法刻蚀工艺的方案，能够在提高刻蚀效率的同时，避免对所述粘合层200和第二芯片310造成刻蚀损耗，且还有利于减小对所述第一通孔201沿所述第二方向（如图6中BB1方向所示）的开口尺寸造成的影响。
需要说明的是，本实施例中，先图形化所述粘合层200以形成所述第一通孔201，再刻蚀所述器件晶圆100以形成所述第二通孔101，即在刻蚀所述器件晶圆100之前，所述粘合层200内已形成有所述第一通孔201，所述第一通孔201沿所述第二方向的开口尺寸通过前述粘合层200的图形化工艺进行设定，从而使所述第一通孔201沿所述第二方向的开口尺寸能够满足工艺需求；因此，与依次刻蚀所述器件晶圆和粘合层，先后在所述器件晶圆内形成第二通孔、在所述粘合层内形成与所述第二通孔相贯通的第一通孔的方案相比，本实施例能够避免出现所述第一通孔201沿所述第二方向的开口尺寸大于所述第二通孔101沿所述第二方向的开口尺寸的问题，从而避免在靠近所述第一通孔201侧壁的位置处（如图10中虚线圈所示），所述器件晶圆100和第二芯片310之间形成缝隙的问题。
还需要说明的是，由于所述多个第二芯片310的功能不同，因此通过先形成所述第一通孔201再形成所述第二通孔101的方案，可以在优化封装结构的性能和可靠性的同时，实现了晶圆级系统封装方案，使晶圆级系统封装方法与传统系统封装方法相结合，既完成了多种芯片的集成，又实现了在器件晶圆上完成封装制程等制造优势。
本实施例中，所述晶圆级系统封装方法还包括：刻蚀所述器件晶圆100的第一背面122，在所述器件晶圆100内形成露出所述第一芯片110的第二导电通孔152，所述第二导电通孔152用于为后续形成与所述第一芯片110电连接的第二导电柱提供空间位置。
本实施例中，通过不同的刻蚀步骤分别在所述器件晶圆100内形成所述第二通孔101和所述第二导电通孔152。需要说明的是，本实施例以先形成所述第二导电通孔152后形成所述第二通孔101为例进行说明。
具体地，刻蚀所述第一芯片110上方的第一背面122，在所述器件晶圆100内形成露出所述第一芯片110的第二导电通孔152；在所述第二导电通孔152内形成填充层（图未示），所述填充层还覆盖所述第一背面122；在所述填充层上形成图形层（图未示），所述图形层内具有露出所述第一通孔201上方填充层的图形开口（图未示）；以所述图形层为掩膜，沿所述图形开口依次刻蚀所述填充层和器件晶圆100，在所述器件晶圆100内形成贯穿所述器件晶圆100且与所述第一通孔201相贯通的第二通孔101；形成所述第二通孔101后，去除所述图形层和填充层。
所述第二导电通孔152的深度较小，通过先形成所述第二导电通孔152后形成所述第二通孔101的方式，能够降低去除所述第二导电通孔152中的填充层的工艺难度。
在其他实施例中，还可以先形成所述第二通孔后形成所述第二导电通孔。
参考图11，在所述第一导电通孔151（如图10所示）内形成与所述第二芯片310电连接的第一导电柱510。
所述第一导电柱510用于实现所述第二芯片310与其他电路之间的电性连接。
需要说明的是，形成所述第一导电柱510的步骤中，还在所述第二导电通孔152（如图10所示）内形成与所述第一芯片110电连接的第二导电柱520。所述第二导电柱520与所述第一芯片110电连接，用于实现所述第一芯片110与其他电路之间的电性连接。而且，通过所述第一导电柱510和第二导电柱520，还能实现所述第二芯片310和第一芯片110之间的电连接。
本实施例中，所述第一导电柱510和第二导电柱520的材料均为铜。在其他实施例中，所述第一导电柱和第二导电柱的材料还可以为铝、钨和钛等导电材料。
具体地，采用电镀工艺在所述第一导电通孔151和第二导电通孔152内填充导电材料层，所述导电材料层还覆盖所述器件晶圆100的第一背面122（如图10所示）；对所述导电材料层进行平坦化工艺，去除所述第一背面122上的导电材料层，保留所述第一导电通孔151内的导电材料作为所述第一导电柱510，保留所述第二导电通孔152内的导电材料作为所述第二导电柱520。
因为在形成所述第一通孔201（如图10所示）之后形成所述第二通孔101（如图10所示），因此在靠近所述第一通孔201侧壁的位置处（如图10中虚线圈所示），所述器件晶圆100和第二芯片310之间形成缝隙的概率较低，相应的，所述导电材料在所述第一通孔201内的填充效果和质量较好，从而有利于改善所述第一导电柱510的电性连接性能，进而优化封装结构的性能和可靠性。
结合参考图12，还需要说明的是，形成所述第一导电柱510和第二导电柱520后，还包括：在所述器件晶圆100的第一背面122（如图10所示）形成覆盖所述第一导电柱510的第一焊垫610以及覆盖所述第二导电柱520的第二焊垫620。
所述第二芯片310通过所述第一导电柱510和第一焊垫610与其他电路实现电性连接，所述第一芯片110通过所述第二导电柱520和第二焊垫620与其他电路实现电性连接。
本实施例中，所述第一焊垫610和第二焊垫620的材料均为铝。在其他实施例中，所述第一焊垫和第二焊垫的材料还可以是铜等导电材料。
结合参考图13和图14，形成所述第一焊垫610和第二焊垫620后，在所述第一背面122（如图10所示）形成钝化层700，所述钝化层700还覆盖所述第一焊垫610和第二焊垫620顶部；图形化所述钝化层700，露出部分所述第一焊垫610和部分所述第二焊垫620。
所述钝化层700覆盖所述第一背面122，从而能够防止外界杂质(如钠离子)、离子电荷和水汽等对器件产生影响，进而提高器件的性能和稳定性，提高封装结构的性能和可靠性。
本实施例中，所述钝化层700的材料可以为磷硅玻璃 (PSG)、氧化硅、氮化硅、氮氧化硅或聚酰亚胺。
本实施例中，通过刻蚀工艺以图形化所述钝化层700，在所述钝化层700内形成第一开口701（如图14所示）和第二开口702（如图14所示），所述第一开口701露出部分所述第一焊垫610，所述第二开口702露出部分所述第二焊垫620，从而能够通过所述第一开口701露出的第一焊垫610实现所述第二芯片310与其他电路之间的电性连接，通过所述第二开口702露出的第二焊垫620实现所述第一芯片110与其他电路之间的电性连接，且还可以通过所述露出的第一焊垫610和第二焊垫620实现所述第二芯片310和第一芯片110之间的电连接。
图15至图17是本发明晶圆级系统封装方法另一实施例中各步骤对应的结构示意图。
本实施例与前述实施例的相同之处，在此不再赘述。本实施例与前述实施例的不同之处在于：如图17所示，图形化所述粘合层830后，剩余粘合层830覆盖所述第二芯片910对应位置的第一正面821，所述剩余粘合层830内形成有多个第一通孔801，且所述第一通孔801与所述第二芯片910一一对应。
相应的，当后续形成覆盖所述第二芯片910的封装层900后，所述封装层900覆盖所述第二芯片910露出的所述第一正面821，因此所述封装层900能够与所述第一正面821实现良好的接触，所述封装层900可以更好地实现绝缘、密封及防潮的作用。
本实施例中，为了实现所述器件晶圆800和所述第二芯片910的粘贴结合，图形化所述粘合层830后，剩余粘合层830覆盖所述第二芯片910对应位置的第一正面821，且所述第一通孔801与所述第二芯片910一一对应，所述第一通孔801用于为后续形成与所述第二芯片910电连接的导电柱提供空间位置。
其中，所述第一通孔801与所述第二芯片910一一对应指的是：所述第一通孔801与所述第二芯片910的数量相等，且所述第一通孔801露出所述第二芯片910对应位置的部分第一正面821。
需要说明的是，本实施例中，图形化所述粘合层830后，所述剩余粘合层830至少覆盖部分所述第一芯片810，从而减小相对应的第一芯片810与第二芯片910在平行于所述第一正面821方向的间距，进而有利于提高工艺集成度。在其他实施例中，所述剩余粘合层也可以位于所述第一芯片一侧的第一正面上。
还需要说明的是，所述剩余粘合层830沿平行于所述第一正面821方向的尺寸根据所述第二芯片910沿平行于所述第一正面821方向的尺寸而定，且还可以根据所述第一芯片810沿平行于所述第一正面821方向的尺寸进行调节。
对本实施例所述制造方法的具体描述，可参考前述实施例中的相应描述，本实施例在此不再赘述。
相应的，本发明还提供一种封装结构。
参考图18，示出了本发明封装结构一实施例的结构示意图。
所述封装结构包括：器件晶圆105，所述器件晶圆105包括集成有多个第一芯片205的第一正面111以及与所述第一正面111相背的第一背面112；粘合层305，位于所述器件晶圆105的第一正面111，所述粘合层305内具有多个露出所述第一正面111的第一通孔306；与所述器件晶圆105相键合的多个第二芯片320，所述第二芯片320设置于所述粘合层305上，所述第二芯片320与所述第一通孔306一一对应且覆盖所述第一通孔306的顶部。
所述器件晶圆105为完成器件制作的晶圆，所述器件晶圆105用于作为封装工艺中的待集成晶圆。
本实施例中，所述器件晶圆105适于实现晶圆级系统封装。其中，晶圆级系统封装指的是将多个不同功能的有源元件、无源元件、微机电系统、光学元件等其他元件集成至一个器件晶圆上，再进行切割以获得单个封装体的技术。晶圆级系统封装具有高效率、高密度、体积小、成品率高和电热性能优良等优点，因此能够满足不断提高的封装工艺要求。
在其他实施例中，所述器件晶圆还可适于实现晶圆级封装工艺。其中，晶圆级封装指的是直接在器件晶圆上进行大部分或全部的封装测试程序，再进行切割以获得单个成品芯片的技术。
所述粘合层305的材料为粘性材料，用于实现所述器件晶圆105与所述第二芯片320的粘贴结合，且所述粘合层305内具有多个露出所述第一正面111的第一通孔306，所述第一通孔306用于为形成与所述第二芯片320电连接的导电柱提供空间位置。
本实施例中，所述粘合层305的材料为可光刻的粘性材料，因此所述第一通孔306可以通过对所述粘合层305进行曝光显影的图形化方式形成，相应可以避免额外刻蚀工艺的采用，从而简化了形成所述第一通孔306的工艺步骤，有利于降低工艺成本、提高封装效率；而且，通过曝光显影的方式，还能够避免对所述粘合层305的粘性产生影响。
为此，本实施例中，所述粘合层305的材料为干膜。在其他实施例中，所述粘合层的材料还可以为聚酰亚胺、聚苯并恶唑或苯并环丁烯。
需要说明的是，所述粘合层305的厚度（未标示）不宜过小，也不宜过大。如果所述粘合层305的厚度过小，则容易导致所述粘合层305不足以实现所述器件晶圆105与所述第二芯片320的粘贴结合；如果所述粘合层305的厚度过大，相应会增加形成所述第一通孔306的工艺难度，且还会造成工艺资源和时间的浪费。为此，本实施例中，根据实际工艺需求，所述粘合层305的厚度为5μm至100μm。
本实施例中，所述第一通孔306用于为形成与所述第二芯片320电连接的导电柱提供空间位置，因此所述第一通孔306在所述第一正面111的投影位于所述第一芯片205的一侧，以免与所述第二芯片320电连接的导电柱和所述第一芯片205之间发生桥接，且为了实现所述封装结构的正常使用功能，根据实际工艺需求，所述第一通孔306与所述第一芯片205一一对应。其中，所述第一通孔306与所述第一芯片205一一对应指的是：所述第一通孔306与所述第一芯片205的数量相同，所述第一通孔306与所述第一芯片205具有预设相对位置关系。
本实施例中，为了降低对所述粘合层305进行图形化的工艺难度和工艺成本，所述粘合层305仅露出所述第一通孔306对应位置的第一正面111。
本实施例中，所述第一通孔306的延伸方向为第一方向，与所述第一方向以及所述第一正面111法线方向相垂直的为第二方向（如图18中CC1方向所示）。
所述第二芯片320用于作为晶圆级系统封装工艺中的待集成芯片，所述多个第二芯片320的功能类型至少为一种。
本实施例中，所述多个第二芯片320的功能类型为多种，且所述第二芯片320的数量与所述第一芯片205的数量相同。通过将多个不同功能的第二芯片320整合至一个封装结构中，从而实现了晶圆级系统封装方案。
在其他实施例中，例如当所述器件晶圆适于实现晶圆级封装工艺时，所述多个第二芯片的功能类型还可以相同。
所述第二芯片320可以采用集成电路制作技术所制成。具体地，所述第二芯片320可以为存储芯片、通讯芯片、处理器或逻辑芯片。在其他实施例中，所述第二芯片还可以是其他功能芯片。
本实施例中，所述第一通孔306用于为形成与所述第二芯片320电连接的导电柱提供空间位置，相应的，所述第二芯片320与所述第一通孔306一一对应。其中，所述第二芯片320与所述第一通孔306一一对应指的是：所述第二芯片320与所述第一通孔306的数量相等，且所述第二芯片320覆盖所述第一通孔306的顶部。
需要说明的是，所述多个第二芯片320的功能不同，因此所述多个第二芯片320可以通过对不同功能的多个器件晶圆进行切割所获得，所述第二芯片320通常也包括位于半导体衬底上的NMOS器件或PMOS器件等器件，还包括介质层、金属互连结构和焊盘等结构。
本实施例中，所述第二芯片320包括具有半导体器件的第二正面（未标示）以及与所述第二正面相背的第二背面（未标示）。其中，所述第二背面指的是远离所述焊盘一侧的半导体衬底的底部表面。
相应的，根据实际工艺需求，所述第二芯片320的第二正面或第二背面设置于所述粘合层305上。
还需要说明的是，为了能够实现所述第二芯片320与其他电路之间的电性连接，所述封装结构通常包括位于所述器件晶圆105和第一通孔306内且与所述第二芯片320电连接的导电柱，相应的，所述封装结构的封装制程通常包括刻蚀所述器件晶圆105的第一背面112，在所述器件晶圆105内形成与所述第一通孔306相贯通的第二通孔。
其中，根据本实施例所述封装结构，在所述封装结构的封装制程中，先形成所述第一通孔306，再刻蚀所述器件晶圆105以形成所述第二通孔，因此所述第一通孔306沿所述第二方向的开口尺寸通过所述粘合层305的图形化工艺进行设定，从而使所述第一通孔306沿所述第二方向的开口尺寸满足工艺需求；与依次刻蚀器件晶圆和粘合层，先后在所述器件晶圆内形成第二通孔、再在所述粘合层内形成第一通孔的方案相比，本实施例能够避免出现所述第一通孔306的横向刻蚀严重的问题，以免出现所述第一通孔306沿所述第二方向开口尺寸大于第二通孔沿所述第二方向开口尺寸的问题，从而提高所述导电柱在所述第一通孔306内的形成质量，进而有利于改善所述导电柱对所述第二芯片320的电性连接性能，相应优化了封装结构的性能和可靠性。
所述封装结构可以采用第一实施例所述的封装方法所形成，也可以采用其他封装方法所形成。本实施例中，对所述封装结构的具体描述，可参考第一实施例中的相应描述，本实施例在此不再赘述。
参考图19，示出了本发明封装结构另一实施例的结构示意图。
本实施例与前述实施例的相同之处，在此不再赘述。本实施例与前述实施例的不同之处在于：所述粘合层705覆盖所述第二芯片720对应位置的第一正面411，所述粘合层705内的第一通孔706露出所述第二芯片720对应位置的部分第一正面411。
相应的，当所述封装结构还包括覆盖所述第二芯片720的封装层时，所述封装层还覆盖所述第二芯片720露出的第一正面411，因此所述封装层能够与所述第一正面411实现良好的接触，所述封装层可以更好地实现绝缘、密封及防潮的作用。
本实施例中，为了实现所述器件晶圆405和所述第二芯片720的粘贴结合，所述粘合层705覆盖所述第二芯片720对应位置的第一正面411，且所述第一通孔706与所述第二芯片720一一对应，所述第一通孔706用于为形成与所述第二芯片720电连接的导电柱提供空间位置。
其中，所述第一通孔706与所述第二芯片720一一对应指的是：所述第一通孔706与所述第二芯片720的数量相等，所述第二芯片720覆盖所述第一通孔706的顶部。
需要说明的是，本实施例中，所述粘合层705至少覆盖部分所述第一芯片605，从而减小相对应的第一芯片605与第二芯片720在平行于所述第一正面411方向的间距，进而有利于提高工艺集成度。在其他实施例中，所述粘合层也可以位于所述第一芯片一侧的第一正面上。
还需要说明的是，所述粘合层705沿平行于所述第一正面411方向的尺寸根据所述第二芯片720沿平行于所述第一正面411方向的尺寸而定，且还可以根据所述第一芯片605沿平行于所述第一正面411方向的尺寸进行调节。
所述封装结构可以采用第二实施例所述的封装方法所形成，也可以采用其他封装方法所形成。本实施例中，对所述封装结构的具体描述，可结合参考第一实施例和第二实施例中的相应描述，本实施例在此不再赘述。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (15)

  1. 一种晶圆级系统封装方法，其特征在于，包括：
    提供器件晶圆，所述器件晶圆包括集成有多个第一芯片的第一正面以及与所述第一正面相背的第一背面；
    提供多个第二芯片；
    在所述器件晶圆的第一正面形成可光刻的粘合层；
    图形化所述粘合层，在所述粘合层内形成多个露出所述第一正面的第一通孔；
    图形化所述粘合层后，将所述第二芯片设置于剩余粘合层上，所述第二芯片与所述第一通孔一一对应且覆盖所述第一通孔的顶部，并使所述器件晶圆和所述第二芯片键合；
    刻蚀所述器件晶圆的第一背面，在所述器件晶圆内形成贯穿所述器件晶圆且与所述第一通孔相贯通的第二通孔，所述第二通孔和所述第一通孔构成第一导电通孔；
    在所述第一导电通孔内形成与所述第二芯片电连接的第一导电柱。
  2. 如权利要求1所述的晶圆级系统封装方法，其特征在于，使所述器件晶圆和所述第二芯片键合后，刻蚀所述器件晶圆的第一背面之前，还包括：在所述第一正面形成覆盖所述第二芯片的封装层；
    通过所述第一背面对所述器件晶圆进行减薄处理。
  3. 如权利要求1所述的晶圆级系统封装方法，其特征在于，使所述器件晶圆和所述第二芯片键合后，在所述第一导电通孔内形成与所述第二芯片电连接的第一导电柱之前，还包括：刻蚀所述器件晶圆的第一背面，在所述器件晶圆内形成露出所述第一芯片的第二导电通孔；
    形成所述第一导电柱的步骤中，还在所述第二导电通孔内形成与所述第一芯片电连接的第二导电柱。
  4. 如权利要求3所述的晶圆级系统封装方法，其特征在于，形成所述第一导电柱和第二导电柱后，还包括：在所述器件晶圆的第一背面形成覆盖所述第一导电柱的第一焊垫以及覆盖所述第二导电柱的第二焊垫；
    在所述第一背面形成钝化层，所述钝化层还覆盖所述第一焊垫和第二焊垫顶部；
    图形化所述钝化层，露出部分所述第一焊垫和部分所述第二焊垫。
  5. 如权利要求1所述的晶圆级系统封装方法，其特征在于，所述第二芯片包括形成有半导体器件的第二正面以及与所述第二正面相背的第二背面；
    将所述第二正面或第二背面设置于剩余粘合层上。
  6. 如权利要求1所述的晶圆级系统封装方法，其特征在于，图形化所述粘合层后，剩余粘合层仅露出所述第一通孔对应位置的第一正面；
    或者，
    剩余粘合层覆盖所述第二芯片对应位置的第一正面。
  7. 如权利要求1所述的晶圆级系统封装方法，其特征在于，所述粘合层的材料为干膜、聚酰亚胺、聚苯并恶唑或苯并环丁烯。
  8. 如权利要求1所述的晶圆级系统封装方法，其特征在于，图形化所述粘合层的步骤包括：对所述粘合层进行曝光显影工艺。
  9. 如权利要求1所述的晶圆级系统封装方法，其特征在于，刻蚀所述器件晶圆的工艺为干法刻蚀和湿法刻蚀中的一种或两种。
  10. 如权利要求1所述的晶圆级系统封装方法，其特征在于，所述多个第二芯片的功能类型至少为一种。
  11. 一种封装结构，其特征在于，包括：
    器件晶圆，所述器件晶圆包括集成有多个第一芯片的第一正面以及与所述第一正面相背的第一背面；
    粘合层，位于所述器件晶圆的第一正面，所述粘合层内具有多个露出所述第一正面的通孔；
    与所述器件晶圆相键合的多个第二芯片，所述第二芯片设置于所述粘合层上，所述第二芯片与所述通孔一一对应且覆盖所述通孔的顶部。
  12. 如权利要求11所述的封装结构，其特征在于，所述第二芯片包括具有半导体器件的第二正面以及与所述第二正面相背的第二背面；所述第二芯片的第二正面或第二背面设置于所述粘合层上。
  13. 如权利要求11所述的封装结构，其特征在于，所述粘合层的材料为干膜、聚酰亚胺、聚苯并恶唑或苯并环丁烯。
  14. 如权利要求11所述的封装结构，其特征在于，所述粘合层仅露出所述通孔对应位置的第一正面；
    或者，
    所述粘合层覆盖所述第二芯片对应位置的第一正面。
  15. 如权利要求11所述的封装结构，其特征在于，所述多个第二芯片的功能类型至少为一种。
PCT/CN2018/101763 2017-09-30 2018-08-22 晶圆级系统封装方法及封装结构 WO2019210617A1 (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1020207022047A KR102400264B1 (ko) 2017-09-30 2018-08-22 웨이퍼 레벨 시스템 패키지 방법 및 패키지 구조
JP2020562809A JP7027577B2 (ja) 2017-09-30 2018-08-22 ウェーハレベルシステムインパッケージ方法及びパッケージ構造
US16/206,037 US10861821B2 (en) 2018-05-03 2018-11-30 Packaging method and package structure of wafer-level system-in-package
US17/078,944 US11309279B2 (en) 2018-05-03 2020-10-23 Package structure of wafer-level system-in-package

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
CN201710917071 2017-09-30
CN201710919199 2017-09-30
CN201810416799.0 2018-05-03
CN201810416799.0A CN108666264B (zh) 2017-09-30 2018-05-03 晶圆级系统封装方法及封装结构

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US16/206,037 Continuation US10861821B2 (en) 2018-05-03 2018-11-30 Packaging method and package structure of wafer-level system-in-package

Publications (1)

Publication Number Publication Date
WO2019210617A1 true WO2019210617A1 (zh) 2019-11-07

Family

ID=62925660

Family Applications (4)

Application Number Title Priority Date Filing Date
PCT/CN2018/093684 WO2019062238A1 (zh) 2017-09-30 2018-06-29 一种晶圆级系统封装方法以及封装结构
PCT/CN2018/093769 WO2019062240A1 (zh) 2017-09-30 2018-06-29 一种晶圆级系统封装结构和电子装置
PCT/CN2018/093770 WO2019062241A1 (zh) 2017-09-30 2018-06-29 一种晶圆级系统封装方法以及封装结构
PCT/CN2018/101763 WO2019210617A1 (zh) 2017-09-30 2018-08-22 晶圆级系统封装方法及封装结构

Family Applications Before (3)

Application Number Title Priority Date Filing Date
PCT/CN2018/093684 WO2019062238A1 (zh) 2017-09-30 2018-06-29 一种晶圆级系统封装方法以及封装结构
PCT/CN2018/093769 WO2019062240A1 (zh) 2017-09-30 2018-06-29 一种晶圆级系统封装结构和电子装置
PCT/CN2018/093770 WO2019062241A1 (zh) 2017-09-30 2018-06-29 一种晶圆级系统封装方法以及封装结构

Country Status (5)

Country Link
US (3) US10811385B2 (zh)
JP (1) JP7027577B2 (zh)
KR (1) KR102400264B1 (zh)
CN (6) CN108335986B (zh)
WO (4) WO2019062238A1 (zh)

Families Citing this family (53)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108335986B (zh) * 2017-09-30 2021-04-06 中芯集成电路（宁波）有限公司 一种晶圆级系统封装方法
CN114050113A (zh) * 2018-08-06 2022-02-15 中芯集成电路（宁波）有限公司 封装方法
JP7106753B2 (ja) 2018-09-04 2022-07-26 中芯集成電路（寧波）有限公司 ウェハレベルパッケージング方法及びパッケージング構造
CN110875268A (zh) 2018-09-04 2020-03-10 中芯集成电路（宁波）有限公司 晶圆级封装方法及封装结构
CN110875193B (zh) * 2018-09-04 2021-08-10 中芯集成电路（宁波）有限公司 晶圆级封装方法及封装结构
CN110875207B (zh) * 2018-09-04 2021-05-07 中芯集成电路（宁波）有限公司 晶圆级封装方法及封装结构
CN110875200B (zh) * 2018-09-04 2021-09-14 中芯集成电路（宁波）有限公司 晶圆级封装方法及封装结构
CN110875192A (zh) * 2018-09-04 2020-03-10 中芯集成电路（宁波）有限公司 晶圆级封装方法及封装结构
JP2021535613A (ja) * 2018-09-04 2021-12-16 中芯集成電路（寧波）有限公司 ウェハレベルパッケージ方法及びパッケージ構造
CN110875205B (zh) * 2018-09-04 2021-07-09 中芯集成电路（宁波）有限公司 晶圆级封装方法及封装结构
CN110875231A (zh) * 2018-09-04 2020-03-10 中芯集成电路（宁波）有限公司 晶圆级封装方法及封装结构
JP7102609B2 (ja) * 2018-09-04 2022-07-19 中芯集成電路（寧波）有限公司 ウェハレベルシステムパッケージング方法及びパッケージング構造
CN110875232A (zh) * 2018-09-04 2020-03-10 中芯集成电路（宁波）有限公司 晶圆级封装方法及封装结构
US10755979B2 (en) 2018-10-31 2020-08-25 Ningbo Semiconductor International Corporation Wafer-level packaging methods using a photolithographic bonding material
CN111128749A (zh) * 2018-10-31 2020-05-08 中芯集成电路（宁波）有限公司 使用可光刻键合材料的晶圆级封装方法
WO2020088205A1 (en) 2018-11-01 2020-05-07 Changxin Memory Technologies, Inc. Wafer stacking method and wafer stacking structure
CN111128974A (zh) * 2018-11-01 2020-05-08 长鑫存储技术有限公司 晶圆堆叠方法与晶圆堆叠结构
CN109411473A (zh) * 2018-11-05 2019-03-01 长江存储科技有限责任公司 一种dram存储芯片及其制造方法
CN111180382A (zh) * 2018-11-13 2020-05-19 中芯集成电路（宁波）有限公司 一种晶圆级器件集成方法及集成结构
CN111200702B (zh) * 2018-11-20 2022-03-15 中芯集成电路（宁波）有限公司 摄像组件及其封装方法、镜头模组、电子设备
US10680633B1 (en) * 2018-12-21 2020-06-09 Analog Devices International Unlimited Compnay Data acquisition system-in-package
CN109659267B (zh) * 2018-12-21 2021-04-23 中芯集成电路（宁波）有限公司 半导体器件制作方法
CN109860064B (zh) * 2018-12-21 2021-04-06 中芯集成电路（宁波）有限公司 一种晶圆级系统封装方法以及封装结构
CN111370431B (zh) * 2018-12-26 2023-04-18 中芯集成电路（宁波）有限公司 光电传感集成系统的封装方法
CN111377392B (zh) * 2018-12-27 2023-08-25 中芯集成电路（宁波）有限公司上海分公司 Mems封装结构及其制作方法
CN111377393B (zh) * 2018-12-27 2023-08-25 中芯集成电路（宁波）有限公司上海分公司 Mems封装结构及其制作方法
CN111377394B (zh) * 2018-12-27 2023-08-25 中芯集成电路（宁波）有限公司上海分公司 Mems封装结构及其制作方法
CN111377391B (zh) * 2018-12-27 2023-08-25 中芯集成电路（宁波）有限公司上海分公司 Mems封装结构及其制作方法
CN111377390B (zh) * 2018-12-27 2023-04-07 中芯集成电路（宁波）有限公司上海分公司 Mems封装结构及其制作方法
CN111377395B (zh) * 2018-12-27 2023-09-08 中芯集成电路（宁波）有限公司上海分公司 Mems封装结构及其制作方法
CN109585402A (zh) * 2018-12-28 2019-04-05 华进半导体封装先导技术研发中心有限公司 一种芯片扇出型封装结构及封装方法
CN111627939B (zh) * 2019-02-27 2023-04-18 中芯集成电路（宁波）有限公司 Cmos图像传感器封装模块及其形成方法、摄像装置
CN110379767B (zh) * 2019-07-16 2022-02-08 中芯集成电路（宁波）有限公司 晶圆级封装芯片通孔互连的方法以及芯片的测试方法
KR102612976B1 (ko) * 2019-10-12 2023-12-13 양쯔 메모리 테크놀로지스 씨오., 엘티디. 다이-대-다이 접합을 위한 방법들 및 구조체들
WO2021092777A1 (zh) * 2019-11-12 2021-05-20 深圳市汇顶科技股份有限公司 堆叠式的芯片、制造方法、图像传感器和电子设备
CN111180438B (zh) * 2019-12-31 2022-06-10 中芯集成电路（宁波）有限公司 晶圆级封装方法及晶圆级封装结构
CN111162054B (zh) * 2019-12-31 2022-01-11 中芯集成电路（宁波）有限公司 一种晶圆级芯片封装方法及封装结构
CN111293078B (zh) * 2020-03-17 2022-05-27 浙江大学 一种转接板正反两面空腔嵌入芯片的方法
CN111505477A (zh) * 2020-04-29 2020-08-07 江苏七维测试技术有限公司 传感器晶圆级测试方法
CN111524467B (zh) * 2020-06-11 2022-06-21 厦门通富微电子有限公司 一种显示装置及其制备方法
CN111725153A (zh) * 2020-06-16 2020-09-29 杰群电子科技（东莞）有限公司 一种无基板系统级封装结构、方法及电子产品
CN111952198B (zh) * 2020-08-25 2022-09-13 嘉兴启创科技咨询有限公司 一种半导体封装及其制备方法
US11335657B2 (en) * 2020-09-16 2022-05-17 International Business Machines Corporation Wafer scale supercomputer
CN112802760B (zh) * 2021-01-07 2022-05-06 湖南中科存储科技有限公司 一种多芯片半导体封装及其形成方法
WO2022161249A1 (zh) * 2021-01-29 2022-08-04 中芯集成电路（宁波）有限公司 一种晶圆级封装结构及其制造方法
JP2023531029A (ja) * 2021-02-05 2023-07-20 長江存儲科技有限責任公司 フリップチップスタッキング構造体およびそれを形成するための方法
CN113223999A (zh) * 2021-04-01 2021-08-06 光华临港工程应用技术研发(上海)有限公司 晶圆键合方法及晶圆键合结构
CN113224005A (zh) * 2021-04-08 2021-08-06 深圳市德明利光电有限公司 一种芯片切割道工艺方法
CN113539853B (zh) * 2021-07-16 2023-01-13 芯知微(上海)电子科技有限公司 一种晶圆级封装方法及其封装结构
CN113539855A (zh) * 2021-07-16 2021-10-22 芯知微(上海)电子科技有限公司 一种系统级封装方法及封装结构
US11637087B2 (en) * 2021-08-27 2023-04-25 Taiwan Semiconductor Manufacturing Company Limited Multi-chip device and method of formation
WO2023104095A1 (en) * 2021-12-08 2023-06-15 Tongfu Microelectronics Co., Ltd. Fan-out packaging method and packaging structure of stacked chips thereof
CN116682743B (zh) * 2023-05-15 2024-01-23 珠海妙存科技有限公司 一种内存芯片封装方法、内存芯片以及集成电路系统

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080079152A1 (en) * 2006-09-28 2008-04-03 Renesas Technology Corp. Semiconductor wafer and method of manufacturing the same and method of manufacturing semiconductor device
CN101840871A (zh) * 2009-03-20 2010-09-22 昆山西钛微电子科技有限公司 晶圆级芯片尺寸封装法
CN202394963U (zh) * 2011-12-28 2012-08-22 日月光半导体制造股份有限公司 多芯片晶圆级半导体封装构造
CN104600058A (zh) * 2015-02-03 2015-05-06 华天科技（昆山）电子有限公司 多芯片半导体封装结构及制作方法
CN105140213A (zh) * 2015-09-24 2015-12-09 中芯长电半导体（江阴）有限公司 一种芯片封装结构及封装方法
CN105977222A (zh) * 2016-06-15 2016-09-28 苏州晶方半导体科技股份有限公司 半导体芯片封装结构及封装方法

Family Cites Families (56)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5227338A (en) * 1990-04-30 1993-07-13 International Business Machines Corporation Three-dimensional memory card structure with internal direct chip attachment
US5723907A (en) * 1996-06-25 1998-03-03 Micron Technology, Inc. Loc simm
US5811879A (en) * 1996-06-26 1998-09-22 Micron Technology, Inc. Stacked leads-over-chip multi-chip module
US5994166A (en) * 1997-03-10 1999-11-30 Micron Technology, Inc. Method of constructing stacked packages
US5998860A (en) * 1997-12-19 1999-12-07 Texas Instruments Incorporated Double sided single inline memory module
US6656827B1 (en) * 2002-10-17 2003-12-02 Taiwan Semiconductor Manufacturing Co., Ltd. Electrical performance enhanced wafer level chip scale package with ground
KR100497111B1 (ko) * 2003-03-25 2005-06-28 삼성전자주식회사 웨이퍼 레벨 칩 스케일 패키지, 그를 적층한 적층 패키지및 그 제조 방법
DE10334575B4 (de) * 2003-07-28 2007-10-04 Infineon Technologies Ag Elektronisches Bauteil und Nutzen sowie Verfahren zur Herstellung derselben
US7528494B2 (en) * 2005-11-03 2009-05-05 International Business Machines Corporation Accessible chip stack and process of manufacturing thereof
US20080191310A1 (en) * 2007-02-12 2008-08-14 Weng-Jin Wu By-product removal for wafer bonding process
US7951647B2 (en) * 2008-06-17 2011-05-31 Taiwan Semiconductor Manufacturing Company, Ltd. Performing die-to-wafer stacking by filling gaps between dies
US8063475B2 (en) * 2008-09-26 2011-11-22 Stats Chippac Ltd. Semiconductor package system with through silicon via interposer
CN101740421B (zh) * 2008-11-17 2011-08-17 中芯国际集成电路制造(上海)有限公司 晶圆及制作方法、系统级封装结构及封装方法
GB0821158D0 (en) * 2008-11-20 2008-12-24 Durham Scient Crystals Ltd Semiconductor device connection
JP5543125B2 (ja) * 2009-04-08 2014-07-09 ピーエスフォー ルクスコ エスエイアールエル 半導体装置および半導体装置の製造方法
US8263434B2 (en) * 2009-07-31 2012-09-11 Stats Chippac, Ltd. Semiconductor device and method of mounting die with TSV in cavity of substrate for electrical interconnect of Fi-PoP
US8841777B2 (en) * 2010-01-12 2014-09-23 International Business Machines Corporation Bonded structure employing metal semiconductor alloy bonding
US9219023B2 (en) * 2010-01-19 2015-12-22 Globalfoundries Inc. 3D chip stack having encapsulated chip-in-chip
US8519538B2 (en) * 2010-04-28 2013-08-27 Taiwan Semiconductor Manufacturing Company, Ltd. Laser etch via formation
JP2011243596A (ja) * 2010-05-14 2011-12-01 Panasonic Corp パッケージ部品の製造方法およびパッケージ部品
KR101692955B1 (ko) * 2010-10-06 2017-01-05 삼성전자 주식회사 반도체 패키지 및 그 제조 방법
CN102024782B (zh) * 2010-10-12 2012-07-25 北京大学 三维垂直互联结构及其制作方法
US20120142136A1 (en) * 2010-12-01 2012-06-07 Honeywell International Inc. Wafer level packaging process for mems devices
US8674518B2 (en) * 2011-01-03 2014-03-18 Shu-Ming Chang Chip package and method for forming the same
JP5853389B2 (ja) * 2011-03-28 2016-02-09 ソニー株式会社 半導体装置及び半導体装置の製造方法。
US8575758B2 (en) * 2011-08-04 2013-11-05 Texas Instruments Incorporated Laser-assisted cleaving of a reconstituted wafer for stacked die assemblies
US9190391B2 (en) * 2011-10-26 2015-11-17 Maxim Integrated Products, Inc. Three-dimensional chip-to-wafer integration
US8772929B2 (en) * 2011-11-16 2014-07-08 Taiwan Semiconductor Manufacturing Company, Ltd. Package for three dimensional integrated circuit
KR101831938B1 (ko) * 2011-12-09 2018-02-23 삼성전자주식회사 팬 아웃 웨이퍼 레벨 패키지의 제조 방법 및 이에 의해 제조된 팬 아웃 웨이퍼 레벨 패키지
US8748232B2 (en) * 2012-01-03 2014-06-10 Maxim Integrated Products, Inc. Semiconductor device having a through-substrate via
CN103681535B (zh) * 2012-09-01 2016-10-19 万国半导体股份有限公司 带有厚底部基座的晶圆级封装器件及其制备方法
KR20140147613A (ko) * 2013-06-20 2014-12-30 삼성전기주식회사 웨이퍼 레벨 반도체 패키지 및 그 제조방법
KR102111739B1 (ko) * 2013-07-23 2020-05-15 삼성전자주식회사 반도체 패키지 및 그 제조방법
US9059039B2 (en) * 2013-09-06 2015-06-16 International Business Machines Corporation Reducing wafer bonding misalignment by varying thermal treatment prior to bonding
US9570421B2 (en) * 2013-11-14 2017-02-14 Taiwan Semiconductor Manufacturing Co., Ltd. Stacking of multiple dies for forming three dimensional integrated circuit (3DIC) structure
TWI556381B (zh) * 2014-02-20 2016-11-01 矽品精密工業股份有限公司 半導體封裝件及其製法
KR102167599B1 (ko) * 2014-03-04 2020-10-19 에스케이하이닉스 주식회사 칩 스택 임베디드 패키지
CN103887279B (zh) * 2014-04-02 2017-02-01 华进半导体封装先导技术研发中心有限公司 三维扇出型晶圆级封装结构及制造工艺
CN104009014B (zh) * 2014-04-26 2017-04-12 华进半导体封装先导技术研发中心有限公司 集成无源器件晶圆级封装三维堆叠结构及制作方法
US9449837B2 (en) * 2014-05-09 2016-09-20 Taiwan Semiconductor Manufacturing Company, Ltd. 3D chip-on-wafer-on-substrate structure with via last process
CN204179071U (zh) * 2014-09-12 2015-02-25 苏州晶方半导体科技股份有限公司 晶圆级指纹识别芯片封装结构
US9502344B2 (en) * 2014-10-06 2016-11-22 Viagan Ltd. Wafer level packaging of electronic device
KR102352237B1 (ko) * 2014-10-23 2022-01-18 삼성전자주식회사 팬 아웃 웨이퍼 레벨 패키지의 제조 방법 및 그의 구조
CN104392958A (zh) * 2014-11-23 2015-03-04 北京工业大学 晶圆级含硅通孔的半导体封装方法
CN104835808A (zh) * 2015-03-16 2015-08-12 苏州晶方半导体科技股份有限公司 芯片封装方法及芯片封装结构
US10269767B2 (en) * 2015-07-31 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-chip packages with multi-fan-out scheme and methods of manufacturing the same
TWI604565B (zh) * 2015-08-04 2017-11-01 精材科技股份有限公司 一種感測晶片封裝體及其製造方法
CN205177812U (zh) * 2015-10-23 2016-04-20 宁波芯健半导体有限公司 侧壁及背面带有绝缘保护的芯片封装结构
US11037904B2 (en) * 2015-11-24 2021-06-15 Taiwan Semiconductor Manufacturing Company, Ltd. Singulation and bonding methods and structures formed thereby
US20170207194A1 (en) * 2016-01-19 2017-07-20 Xintec Inc. Chip package and method for forming the same
CN105621345B (zh) * 2016-03-11 2018-06-29 华天科技（昆山）电子有限公司 Mems芯片集成的封装结构及封装方法
CN105870024B (zh) * 2016-06-15 2018-07-27 通富微电子股份有限公司 系统级封装方法
CN105938804A (zh) * 2016-06-28 2016-09-14 中芯长电半导体（江阴）有限公司 一种晶圆级芯片封装方法及封装件
CN107068629B (zh) * 2017-04-24 2019-11-26 华天科技（昆山）电子有限公司 晶圆级芯片封装结构及其制作方法
CN107176586A (zh) * 2017-07-06 2017-09-19 苏州晶方半导体科技股份有限公司 一种mems芯片与asic的封装结构及封装方法
CN108335986B (zh) * 2017-09-30 2021-04-06 中芯集成电路（宁波）有限公司 一种晶圆级系统封装方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080079152A1 (en) * 2006-09-28 2008-04-03 Renesas Technology Corp. Semiconductor wafer and method of manufacturing the same and method of manufacturing semiconductor device
CN101840871A (zh) * 2009-03-20 2010-09-22 昆山西钛微电子科技有限公司 晶圆级芯片尺寸封装法
CN202394963U (zh) * 2011-12-28 2012-08-22 日月光半导体制造股份有限公司 多芯片晶圆级半导体封装构造
CN104600058A (zh) * 2015-02-03 2015-05-06 华天科技（昆山）电子有限公司 多芯片半导体封装结构及制作方法
CN105140213A (zh) * 2015-09-24 2015-12-09 中芯长电半导体（江阴）有限公司 一种芯片封装结构及封装方法
CN105977222A (zh) * 2016-06-15 2016-09-28 苏州晶方半导体科技股份有限公司 半导体芯片封装结构及封装方法

Also Published As

Publication number Publication date
CN108666264B (zh) 2021-08-10
CN108666264A (zh) 2018-10-16
WO2019062238A1 (zh) 2019-04-04
WO2019062240A1 (zh) 2019-04-04
CN108346588A (zh) 2018-07-31
CN108346639B (zh) 2020-04-03
KR102400264B1 (ko) 2022-05-23
JP2021512506A (ja) 2021-05-13
CN108597998A (zh) 2018-09-28
US10930617B2 (en) 2021-02-23
US10811385B2 (en) 2020-10-20
CN108346588B (zh) 2020-12-04
WO2019062241A1 (zh) 2019-04-04
US20190115316A1 (en) 2019-04-18
CN108335986B (zh) 2021-04-06
JP7027577B2 (ja) 2022-03-01
US20190103332A1 (en) 2019-04-04
US10756056B2 (en) 2020-08-25
CN108336037B (zh) 2022-02-11
CN108597998B (zh) 2022-04-08
CN108335986A (zh) 2018-07-27
CN108346639A (zh) 2018-07-31
CN108336037A (zh) 2018-07-27
KR20200106055A (ko) 2020-09-10
US20190115314A1 (en) 2019-04-18

Similar Documents

Publication Publication Date Title
WO2019210617A1 (zh) 晶圆级系统封装方法及封装结构
US9461018B1 (en) Fan-out PoP structure with inconsecutive polymer layer
KR101822236B1 (ko) 반도체 디바이스 및 제조 방법
US11380620B2 (en) Semiconductor package including cavity-mounted device
TWI718606B (zh) 半導體元件及其形成方法
US10163807B2 (en) Alignment pattern for package singulation
TWI579966B (zh) 半導體封裝系統及方法
US9686870B2 (en) Method of forming a microelectronic device package
KR20170037480A (ko) 반도체 장치 및 제조 방법
CN113539980B (zh) 半导体器件及其制造方法
US11309279B2 (en) Package structure of wafer-level system-in-package
CN108470722B (zh) 半导体结构及其形成方法
KR102450735B1 (ko) 반도체 디바이스 및 제조 방법
KR20220106653A (ko) 반도체 패키징 및 그 형성 방법
CN220873580U (zh) 封装件
US11133283B2 (en) Integrated fan-out device
US20230223357A1 (en) Interconnect Structure of Semiconductor Package and Method of Forming the Same
KR20210142527A (ko) 집적 회로 패키지에 대한 재배선 구조체 및 그 형성 방법

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18917527

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 20207022047

Country of ref document: KR

Kind code of ref document: A

Ref document number: 2020562809

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 18917527

Country of ref document: EP

Kind code of ref document: A1