WO2022161249A1 - 一种晶圆级封装结构及其制造方法 - Google Patents

一种晶圆级封装结构及其制造方法 Download PDF

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Publication number
WO2022161249A1
WO2022161249A1 PCT/CN2022/072999 CN2022072999W WO2022161249A1 WO 2022161249 A1 WO2022161249 A1 WO 2022161249A1 CN 2022072999 W CN2022072999 W CN 2022072999W WO 2022161249 A1 WO2022161249 A1 WO 2022161249A1
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WO
WIPO (PCT)
Prior art keywords
chip
pad
substrate
bonding
wafer
Prior art date
Application number
PCT/CN2022/072999
Other languages
English (en)
French (fr)
Inventor
黄河
刘孟彬
向阳辉
Original Assignee
中芯集成电路（宁波）有限公司
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Publication date
Priority claimed from CN202110129182.2A external-priority patent/CN114823380A/zh
Priority claimed from CN202110130747.9A external-priority patent/CN114823493A/zh
Priority claimed from CN202110129193.0A external-priority patent/CN114823383A/zh
Application filed by 中芯集成电路（宁波）有限公司 filed Critical 中芯集成电路（宁波）有限公司
Publication of WO2022161249A1 publication Critical patent/WO2022161249A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the invention relates to the field of semiconductor packaging, in particular to a wafer-level packaging structure and a manufacturing method thereof.
  • wafer-level system packaging is a Completing the packaging integration process on the wafer has the advantages of greatly reducing the area of the packaging structure, reducing manufacturing costs, optimizing electrical performance, and batch manufacturing, which can significantly reduce workload and equipment requirements.
  • the Silicon Interposer in Interposer is a circuit board-like device made of silicon wafers, but its line width and node spacing are smaller than those of a circuit board. Chips with different functions, such as CPU, DRAM, etc., can be connected to the same silicon interposer, and many operations and data exchanges can be completed through the silicon interposer, which saves power and increases bandwidth. Similar to PCB, Silicon Interposer generally has copper-filled through-holes (through-silicon holes), and the results of joint operations between different chips are transmitted to the package substrate connected to it through the through-silicon hole, and the package substrate is connected to the circuit board. So Silicon Interposer and package substrate are equivalent to bridges between multiple chips and the same circuit board.
  • Silicon Interposer's TSV production the traditional process is complex, the diameter of the silicon hole is limited, usually controlled within 30 microns; if the silicon hole is made larger, the metal filled in the silicon hole will be thermally expanded during later use, resulting in silicon Hole or insulation cracked. Therefore, the silicon hole can only be made smaller; but the deposition of insulating substances, barrier layer/seed layer deposition, and filling metal in the small silicon hole will become very difficult, so the process control is more difficult, and the yield is also relatively high In addition, the multi-layer structure is stacked vertically on the circuit board, which is not conducive to the miniaturization of the package.
  • the invention discloses a wafer-level packaging structure and a manufacturing method thereof, which can solve the problems of low yield and vertical multi-layer stacking.
  • the present invention provides a manufacturing method of a wafer level packaging structure, including: providing an electrical adapter board and at least one chip, wherein the upper surface of the electrical adapter board has a bare first pad, the chip The lower surface of the chip is provided with a second pad; the chip is physically connected and electrically connected with the electrical transfer board; wherein, the physical connection includes: bonding the chip on the electrical transfer board through a bonding process; the electrical connection includes: forming through an electroplating process
  • the conductive bump makes the first bonding pad and the second bonding pad electrically connected through the conductive bump.
  • the invention also provides a wafer-level packaging structure, comprising: an electrical adapter board, the electrical adapter board includes opposite upper and lower surfaces, the upper surface at least exposes a part of the surface of the first bonding pad; at least one chip, the chip and the A second bonding pad is provided on the opposite surface of the electrical adapter board; the first bonding pad and the second bonding pad are electrically connected through conductive bumps, and the conductive bumps are formed by an electroplating process.
  • the beneficial effect of the present invention is that: different chips are electrically connected to the circuit board through an electrical adapter board, and conductive bumps are formed between the chips and the electrical adapter board through an electroplating process, and the entire electrical adapter board can be formed at the same time.
  • Conductive bumps improve efficiency, and are compatible with the front-end process of semiconductors, so that the front-end process can be used to complete wafer-level system integration, which greatly improves the process efficiency of the entire system integration and saves the transition between the front-end process and the packaging process. .
  • the problem of vertical multi-layer stacking is solved, which is beneficial to the miniaturization of the package.
  • connection between the electrical adapter board and the chip may be physically connected first and then electrically connected, or may be electrically connected first and then physically connected.
  • first physical connection a gap is formed between the first pad of the electrical adapter board and the second pad of the chip, and the conductive bump is formed in the gap to improve the bonding strength.
  • the electrical connection between the first bonding pad and the second bonding pad can be realized, and no other auxiliary process for realizing the electrical connection is required, thereby simplifying the process flow.
  • first solder pad and the second solder pad adopt a dislocation design in the direction perpendicular to the surface of the electrical adapter board, and the area of the overlapping area is greater than half of the area of the first solder pad or the second solder pad, and the dislocation design can prevent electroplating.
  • the conductive bumps do not fill the voids.
  • the dislocation design ensures a certain bonding strength on the basis of ensuring that the conductive bumps fill the gaps.
  • the electroplating process adopts electroless palladium immersion gold or electroless nickel gold, and an appropriate electroplating time is selected according to the size of the conductive bump.
  • the photolithographic bonding material when its projection is centered on the center of the chip, and the coverage area is greater than 10% of the chip area, preferably covering the entire lower surface of the chip (except the area where the second pad is located), so that ,
  • the plastic encapsulation layer is formed in the subsequent process, it is ensured that there is no gap under the chip, so as to improve the bonding strength and improve the yield.
  • the dry film is used to bond the chip and the electrical adapter.
  • the dry film is a photoresistable material, which can be used to form a desired pattern through a semiconductor process.
  • the process is simple and compatible with the semiconductor process, and can be mass-produced.
  • the elastic modulus of the dry film is relatively small, which can be easily deformed without being damaged when subjected to thermal stress, thereby reducing the bonding stress between the chip and the device wafer.
  • the dry film of the surrounding wall structure can be reserved around the area where the conductive bumps are pre-formed, so that when the conductive bumps are formed, due to the blocking of the dry film, the conductive bumps of the expected shape can be formed to prevent the conductive bumps. Horizontal spillover.
  • the electrical adapter board by first bonding multiple chips on the electrical adapter board, pre-alignment is achieved for multiple chips, so multiple chips and conductive bumps can be thermally bonded at the same time.
  • the sequential bonding of chips and conductive bumps greatly improves manufacturing efficiency.
  • the area of the overlapping area of the second bonding pad and the conductive bump in the direction perpendicular to the surface of the electrical adapter board is larger than half of the area of the second bonding pad, so as to improve the bonding strength of the two.
  • the electrical adapter board can be a dielectric layer, the lower solder balls are located on the lower surface of the dielectric layer, and the lower part of the dielectric layer can also include a substrate, the substrate is formed with a through silicon via structure, and the lower solder balls are located on the lower surface of the substrate.
  • the through silicon via structure can be formed in different process stages according to the actual situation.
  • FIGS. 1 to 6 are schematic diagrams of structures corresponding to different steps in a wafer-level packaging method according to Embodiment 1 of the present invention.
  • FIG. 7 and FIG. 8 show schematic structural diagrams corresponding to different steps in a wafer-level packaging method according to Embodiment 2 of the present invention.
  • FIGS. 9 to 12 are schematic diagrams showing corresponding structures in different steps in a wafer-level packaging method according to Embodiment 3 of the present invention.
  • the term "and/or" includes any and all combinations of the associated listed items. If a method herein includes a series of steps, the order of the steps presented herein is not necessarily the only order in which the steps may be performed, and some of the steps may be omitted and/or some other steps not described herein may be added to this method. If the components in a certain drawing are the same as the components in other drawings, although these components can be easily identified in all the drawings, in order to make the description of the drawings clearer, this specification will not refer to all the same components. Numbers are attached to each figure.
  • the present embodiment 1 provides a method for manufacturing a wafer-level packaging structure, comprising the following steps:
  • the physical connection includes: bonding the chip on the electrical transfer board through a bonding process; the electrical connection includes: forming a conductive bump through an electroplating process, so that the first bonding pad and the second bonding pad are electrically connected through the conductive bump.
  • the second pad of the chip is rearranged through the electrical adapter board.
  • the connection between the electrical adapter board and the chip may be physically connected first and then electrically connected, or may be electrically connected first and then physically connected.
  • the electrical adapter plate can be formed by various methods, and one method is used as an example for description below.
  • a substrate 10 is provided, and a through silicon via structure 11 is formed inside an upper surface of the substrate 10 .
  • the material of the substrate 10 includes semiconductor materials, such as silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbon (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs) ), indium phosphide (InP), or other III/V compound semiconductors, etc.
  • the TSV structure 11 is only formed inside the upper surface of the substrate 10 and does not penetrate through the lower surface of the substrate 10 .
  • the TSV structure 11 is a well-known structure in the art.
  • the formation method is to form a through hole first, form an insulating layer on the inner wall of the through hole, and form a conductive material inside the insulating layer.
  • a conductive material is formed on the sidewall of the hole.
  • the conductive material fills the through hole, and the insulating layer also covers the upper surface of the substrate 10 .
  • a dielectric material layer 200 and an interconnect structure penetrating the dielectric material layer 200 and connecting the TSV structure 11 are formed on the substrate 10 .
  • the dielectric material layer 200 is a multi-layer structure, and the formation method is as follows: forming each layer of dielectric material in sequence; Interconnect 210 of plug 22 .
  • three layers of dielectric materials are shown, which are a first dielectric material 201, a second dielectric material 202, and a third dielectric material 203 in order from bottom to top.
  • a conductive plug 22 penetrating the dielectric material is formed in the dielectric material.
  • the conductive plug 22 can pass through one layer of dielectric material or through two or more layers of dielectric material.
  • the layout of the conductive plug is set according to the specific requirements of circuit connection, and interconnect lines 210 are formed at both ends of the conductive plug 22. Interconnection pads 21 are formed over the hole structure 11 . Both the conductive plugs 22 and the interconnection pads 21 are conductive materials, such as aluminum, copper, gold, titanium, or tungsten.
  • the interconnect structure includes conductive plugs 22 , interconnect lines 210 and interconnect pads 21 .
  • Materials of the first dielectric material 201 , the second dielectric material 202 and the third dielectric material 203 include silicon oxide, silicon nitride, etc., and may be formed by a deposition process.
  • grooves are formed on the upper surface of the third dielectric material 203 to expose a part of the surface of the uppermost interconnect pad, and the grooves can provide space in the subsequent steps of forming conductive bumps.
  • the uppermost interconnect pad is defined as the first pad 23 .
  • the surface of the first pad 23 may also be flush with the upper surface of the dielectric layer or protrude from the upper surface of the dielectric layer.
  • an adhesive layer 32 is formed on the upper surface of the electrical adapter board, and the adhesive layer 32 is used to bond the chip to the upper surface of the electrical adapter board in a later process.
  • the adhesive layer 32 includes a film-like dry film or a liquid dry film.
  • Film-like dry film is to coat the solvent-free photoresist on the polyester film base, and then cover the polyethylene film; when using, remove the polyethylene film, and press the solvent-free photoresist on the base plate , After exposure and development, graphics can be formed in the dry film.
  • Liquid dry film means that the components in the film-like dry film exist in liquid form.
  • Dry film is a permanently bonded film with high bond strength.
  • the film-like dry film can be formed on the electrical transfer board by sticking a film, and the liquid dry film is coated on the electrical transfer board by a spin coating process, and then the liquid dry film is cured.
  • the chip and the electrical adapter are bonded by dry film.
  • the dry film is a photolithographic material, which can be used to form the desired pattern through the semiconductor process. The process is simple and compatible with the semiconductor process, and can be mass-produced. Moreover, the elastic modulus of the dry film is relatively small, which can be easily deformed without being damaged when subjected to thermal stress, thereby reducing the bonding stress between the chip and the electrical adapter board.
  • the method further includes: patterning the adhesive layer 32 , forming an opening 33 in the adhesive layer 32 , and the depth of the opening 33 is equal to or less than the thickness of the adhesive layer 32 (The opening may not be formed in the adhesive layer 32).
  • the area where the opening 33 is formed corresponds to the working area of the chip 30.
  • a cavity is formed, and the cavity is used as the working cavity of the chip (eg, a thermal isolation cavity).
  • the openings 33 are used for heat insulation, so the depth of the openings 33 is not limited. Part of the thickness (the depth of the opening is smaller than the thickness of the adhesive layer 32). In other embodiments, if the depth of the opening needs to be defined, a suitable thickness is formed when forming the photolithographic bonding material.
  • fbar cavity-type bulk acoustic wave resonators
  • SAW surface acoustic wave resonators
  • a lower cavity is provided below the main resonance area, a cover is formed above, and an upper cavity is formed between the cover and the main resonance area.
  • the cavity in the embodiment can be either an upper cavity or a lower cavity.
  • an upper cavity is formed above and between the covers, and the cavity in this embodiment can be used as the upper cavity.
  • the cavity in this embodiment can be used as the upper cavity.
  • a thermal insulation cavity for thermal insulation is provided below the functional area, and the cavity formed in this embodiment can be used as a thermal insulation cavity.
  • the ultrasonic sensor the membrane-shaped vibrating part is suspended in the air, the upper surface is used to receive ultrasonic waves, and the lower surface covers the cavity.
  • the cavity in this embodiment can be used as the lower cavity of the ultrasonic sensor.
  • the adhesive layer 32 is formed on the surface of the electrical adapter board. In another embodiment, the adhesive layer 32 can also be formed on the surface of the chip 30 . The formation of the adhesive layer 32 on the lower surface of the chip 30 does not affect the formation of the openings 33 . In an optional embodiment, after the adhesive layer is formed, the method further includes: patterning the adhesive layer, and forming a surrounding wall structure around the area where the conductive bumps are pre-formed. The interior enclosed by the enclosure wall structure is an area where conductive bumps are formed, the enclosure wall structure is preferably a closed annular structure, and the enclosed space is cylindrical.
  • the adhesive layer of the wall structure is reserved around the area where the conductive bumps are pre-formed, so that when the conductive bumps are formed, due to the barrier of the walls, the conductive bumps of the expected shape can be formed, preventing the conductive bumps. Horizontal spillover.
  • the thickness of the formed adhesive layer 32 is 5-200 ⁇ m, such as 15 ⁇ m, 30 ⁇ m, 80 ⁇ m, 150 ⁇ m, and the like.
  • the projection of the adhesive layer 32 on the surface of the electrical adapter board is centered on the center of the chip, and covers at least 10% of the area of the chip.
  • the thickness of the adhesive layer 32 is related to the height of the conductive bumps formed in the later process. The correlation between the two will be described in detail later when the conductive bumps are formed.
  • the adhesive layer 32 covers at least 10% of the area of the chip, and covers the center of the chip.
  • the adhesive layer 32 and the plastic encapsulation layer in the subsequent process work together to seal the chip.
  • the adhesive layer 32 covers the entire lower surface of the chip (except the area where the second pad is located), so that when the plastic sealing layer is formed in the subsequent process, it is ensured that there is no gap under the chip, the bonding strength is improved, and the yield is improved.
  • conductive bumps 24 are formed on the first pads 11 through an electroplating process.
  • the material of the conductive bump includes any one of copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc or chromium.
  • the height of the formed conductive bumps 24 is related to the height of the dry film and the structure of the chip. When the second pad of the chip is equal to the lower surface of the chip, the height of the conductive bumps 24 and the height of the dry film are approximately the same height, In this way, when the chip and the dry film are bonded, the second pads 31 are just in contact with the conductive bumps 24 .
  • the height of the conductive bumps 24 is equal to the depth of the recess + the dry film thickness + the depth of the lower surface of the chip 20 being recessed downward.
  • the height of the conductive bump is 5-200 ⁇ m. Such as 10 ⁇ m, 50 ⁇ m, 100 ⁇ m.
  • the electroplating process includes electroless palladium immersion gold (ENEPIG) or electroless nickel gold (ENIG), wherein the process parameters of ENEPIG or ENIG can refer to Table 1.
  • the surface of the pad can be cleaned first to remove the natural oxide layer on the surface of the pad and improve the surface wettability of the pad; after that, activation can be performed process to promote the nucleation and growth of the coating metal on the metal to be plated.
  • the settings of the first pad and the second pad also need to meet certain requirements.
  • the exposed area of the first pad is 5-200 square microns.
  • the pads can be in sufficient contact with the plating solution to avoid insufficient contact between the pads and the plating solution, which will affect the contact between the conductive bumps and the pads.
  • it can also ensure that the contact area will not be too large to reduce the plating efficiency and will not occupy too much surface.
  • the cross-sectional area of the formed conductive bumps is greater than 10 square micrometers, which can not only ensure that the area occupied by the conductive bumps is not too large, but also ensure the bonding strength between the conductive bumps and the bonding pads.
  • the material of the conductive bump is the same as the material of the first bonding pad, which makes it easier to form the conductive bump.
  • the material of the first pad can be different from the material of the conductive bump.
  • a material layer can be formed on the first pad first.
  • the material of the material layer is the same as the material of the conductive bump.
  • the method of forming the material layer may be a deposition process.
  • the chip 30 may be a chip made of a silicon wafer, or a chip formed of other materials.
  • the chip 30 is made by an integrated circuit manufacturing technology, and can be a memory chip, a communication chip, a processor or a logic chip.
  • the second bonding pads 31 are located on the lower surface of the chip 30 and are used to realize electrical connection between the chip 30 and other devices.
  • the second pad 31 may be a pad.
  • the material of the second pad 31 includes any one of copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc or chromium.
  • the second pad and the conductive bump The material combinations include gold-gold, copper-copper, copper-tin or gold-tin.
  • the multiple first chips may be chips with the same function; the multiple first chips may also include at least two chips with different functions; the first chips are passive devices or active devices.
  • the first chip may be a sensor module chip, a MEMS chip, a filter chip, a logic chip, a memory chip, a capacitor, an inductor, etc., and the capacitor may be an MLCC capacitor.
  • the sensor module chip includes a module chip for sensing at least one of radio frequency signals, infrared radiation signals, visible light signals, acoustic wave signals, and electromagnetic wave signals; the filter chip includes at least one of surface acoustic wave resonators and bulk acoustic wave resonators.
  • the first chip may be an encapsulated chip, and a subsequent plastic encapsulation process is not required.
  • the first chip may also be a bare chip, and the first chip may also be a chip with a shielding layer on the top surface.
  • the materials of the second pads 31 and the conductive bumps 24 are metal, and the second pads 31 and the conductive bumps 24 are electrically connected through a thermocompression bonding process.
  • Each second bonding pad 31 and each conductive bump 24 are thermally bonded one by one; or a plurality of second bonding pads 31 and a plurality of conductive bumps 24 are thermally bonded simultaneously.
  • the area of the first bonding pad 23 or the second bonding pad 31 is 5-200 square micrometers; the area of the overlapping area of the second bonding pad 31 and the conductive bump 24 in the direction perpendicular to the surface of the electrical adapter board is larger than Half of the area of the second pads 31 to improve the bonding strength of the two.
  • the conductive bumps 24 and the second pads 31 face each other, that is, in the direction perpendicular to the surface of the electrical adapter board, the two overlap to the greatest extent possible.
  • the cross-sectional area of the conductive bump is greater than 10 square micrometers to ensure structural strength.
  • a plurality of chips 30 are bonded to the surface of the electrical adapter board one by one.
  • the surface of the chip 30 with the second pads 31 is the front side, and the side opposite to the front side is the back side.
  • the backside of the chip 30 is temporarily bonded to the substrate; after the chip is bonded to the electrical adapter board, the substrate is debonded.
  • the substrate may be a carrier wafer for temporarily fixing the plurality of chips 30 , and the substrate is also used for supporting the chips 30 during the bonding process of the chips 30 and the electrical adapter board, thereby improving the bonding reliability.
  • the chip 30 is temporarily bonded to the substrate by an adhesive layer or electrostatic bonding.
  • Electrostatic bonding technology is a method to achieve bonding without any adhesive.
  • the chip and the substrate to be bonded are connected to different electrodes respectively, and the surface of the chip and the substrate is charged under the action of voltage, and the surface charges of the chip and the substrate are electrically different, so that during the bonding process of the chip and the substrate A large electrostatic attraction is generated to realize the physical connection between the two.
  • the substrate and the chip can be separated by chemical method or mechanical peeling.
  • the method further includes: forming a plastic sealing layer 40 , and the plastic sealing layer 40 is filled at least between adjacent chips.
  • the plastic sealing layer may not be formed.
  • the encapsulation layer 40 covers the surface of the electrical adapter board and the chip 30, that is to say, the encapsulation layer 40 fills the gap between the chips 30 and covers the chip 30.
  • the plastic encapsulation layer seals the chip, thereby Better isolation of air and moisture, which in turn improves encapsulation.
  • the encapsulation layer 40 may be formed through an injection molding process.
  • the method further includes: thinning the lower surface of the substrate 10 to expose the TSV structure 11 , and forming solder balls connecting the TSV structure 11 50.
  • the lower surface of the substrate 10 can be thinned by a grinding process to expose the lower end of the TSV structure 11. Since the lower end of the TSV structure 11 has an insulating layer, the insulating layer also needs to be removed, and then an electroplating process or a deposition process can be used. Solder balls 50 are formed.
  • the electrical transfer board includes a substrate 10, a through silicon via structure 11 disposed in the substrate 10, a multilayer dielectric material above the substrate 10, and conductive plugs 22 and interconnection pads 21 located in the dielectric material, The first solder pad 23 and the solder ball 50 .
  • the overall thickness of the electrical adapter plate is 5-200 microns, such as 10 microns, 20 microns, 50 microns, 100 microns, etc.
  • the first solder pad realizes re-layout and is electrically connected to the electrical connection terminals on the PCB board, and different chips are electrically connected to the circuit board through the electrical adapter board, which solves the problem of vertical multi-layer stacking and is beneficial to the small package size. change.
  • the thickness of the electrical adapter plate is reduced, thereby improving the heat dissipation effect of the electrical adapter plate; in addition, reducing the thickness of the electrical adapter plate is also conducive to reducing the package structure after encapsulation The overall thickness of the package, thereby improving the performance of the package structure.
  • the process used in the thinning treatment may be a back grinding process, chemical mechanical polishing One or more of a (Chemical Mechanical Polishing, CMP) process and a wet etching process.
  • CMP Chemical Mechanical Polishing
  • a deep trench isolation structure for defining the stop position is usually formed in the substrate, so that the thinning process stops at the bottom of the deep trench isolation structure.
  • neutral doping ions such as one or both of oxygen ions and nitrogen ions
  • the bottom substrate layer of the semiconductor substrate may also be thinned, so that it can better stop at the bottom of the insulator layer .
  • the method further includes: providing a capping substrate 60 , the first surface of the capping substrate 60 includes a cavity, and bonding the capping substrate 60 with a cavity.
  • the first surface is connected to the electrical transfer board, and the cavity covers at least a part of the chip 30 .
  • the material of the capping substrate 60 may be: semiconductor materials such as silicon, germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, or a dielectric material.
  • the cavity may be larger, and one cavity covers multiple chips 30 at the same time.
  • the cavity is a plurality of smaller cavities, each of which accommodates one or more chips 30 .
  • a small cavity of the cover substrate can also accommodate only a part of a chip.
  • the chip needs to be formed with a cavity structure, Moreover, the cavity structure corresponds to the functional area of the chip structure, and the entire chip is not included in the cavity.
  • the chip needs to be formed with a cavity structure, and the cavity structure corresponds to the functional area of the chip structure, rather than including the entire chip in the cavity.
  • the bulk acoustic wave resonator (BAW), the surface acoustic wave resonator (SAW) and the solidly mounted bulk acoustic wave resonator (SMR) are provided with an upper cavity above the main resonance region, the cavity in this embodiment can be used as the upper cavity,
  • a thermal insulation cavity for thermal insulation is provided under the functional area.
  • the cavity formed in this embodiment can be used as a thermal insulation cavity.
  • the lower surface covers the cavity, and the cavity in this embodiment can be used as the lower cavity of the ultrasonic sensor.
  • the formed cavity is a sealed cavity, which can prevent the external environment from contaminating the devices in the cavity (moisture, dust, grease, etc.).
  • an electrical connection structure is formed on the capping substrate to lead out the electrical properties of the chip.
  • the chip and the electrical adapter in this embodiment are first physically connected and then electrically connected.
  • Embodiment 2 and Embodiment 1 are briefly described below.
  • the electrical adapter board and the chip are physically bonded so that the first pad 23 and the second pad 31 are opposite to each other. , and a gap is formed between the first pad 23 and the second pad 31; referring to FIG. 8 , a conductive bump is formed in the gap by an electroplating process, and the first pad and the second pad are electrically connected through the conductive bump .
  • at least one chip 30 (a plurality of chips in this embodiment) is provided.
  • the surface of the chip 30 is higher than the surface of the second bonding pad 31 , that is, the second bonding pad 31 is recessed inward relative to the lower surface of the chip 30 .
  • the surface of the second bonding pad 31 may also be flush with the bottom surface of the chip or protrude from the surface of the chip.
  • the chip 30 is adhered to the upper surface of the dielectric layer (also the upper surface of the electrical adapter board) through the photolithographic bonding material 32 . In this embodiment, no opening is formed in the photolithographic bonding material 32.
  • an opening may be formed in the photolithographic bonding material 32, so that the opening is disposed opposite to the functional area of the device .
  • the chip 30 may also be adhered to the upper surface of the dielectric layer with structural adhesive. It should be noted that, in this embodiment, when the chip 30 is adhered to the surface of the dielectric layer, the second bonding pad 23 and the first bonding pad 31 are opposite to each other, and the second bonding pad 23 and the first bonding pad 31 are formed between void.
  • the projections of the second pads 23 and the first pads 31 in the direction perpendicular to the surface of the electrical adapter board are staggered, and the area of the projected overlapping area is larger than the area of the second pads 23 or the first pads 31 half of .
  • the first bonding pad 31 and the second bonding pad 23 adopt a dislocation design in the direction perpendicular to the surface of the electrical adapter board.
  • the dislocation design can prevent the conductive bumps 24 from filling the gaps when the conductive bumps 24 are electroplated.
  • the dislocation design ensures a certain bonding strength on the basis of ensuring that the conductive bumps 24 fill the voids.
  • the surface of the electrical adapter board is higher than the surface of the first bonding pad 23
  • the surface of the chip 30 is higher than the surface of the second bonding pad 31 .
  • only the surface of the electrical adapter board may be higher than the surface of the first bonding pad 23, or only the surface of the chip 30 may be higher than the surface of the second bonding pad 31, or other structural forms, as long as the first A gap may be formed between the first pad 23 and the second pad 31 .
  • an electroplating process is used to fill the gaps to form conductive bumps 24 , so that the first pads 23 and the second pads 31 are electrically connected through the conductive bumps 24 .
  • Embodiment 1 lies in the method for forming the electrical transfer board. Please refer to FIG. 8 to FIG. 11 for a brief description of each step.
  • a substrate 10 is provided, a dielectric material layer 200 and conductive plugs 22 penetrating the dielectric material layer 200 are formed on the substrate 10 , and the conductive plugs 22 are connected and exposed to the first pads 23 on the top surface of the dielectric material layer 200 .
  • the structure, material and forming method of the dielectric material layer 200 , the conductive plug 22 penetrating the dielectric material layer 200 and the first pad 23 refer to Embodiment 1, which will not be repeated here.
  • the TSV structure does not need to be formed, but solder balls also need to be formed at a later stage of the process, so interconnection pads 21 are formed on the upper surface of the substrate 10 for connecting the solder balls.
  • the conductive bumps 24 are formed according to the method of Embodiment 1 or 2, and the chip 30 is adhered to the upper surface of the electrical adapter board, and a plastic sealing layer 40 is formed on the upper surface of the electrical adapter board, and the plastic sealing layer 40 is sealed The conductive bumps 24 and fill the gaps between the chips 30 .
  • the specific details of the above steps refer to Embodiment 1.
  • the lower surface of the substrate is thinned, and a TSV structure 11 is formed from the thinned lower surface.
  • the upper end of the TSV structure 11 is connected to the interconnect pad 21 , and the lower end is formed with solder balls 50 .
  • the TSV structure may also not be formed.
  • the substrate is removed to expose the lower surfaces of the interconnect pads 21 at the bottom layer, and solder balls 50 are formed on the lower surfaces of the interconnect pads 21 .
  • the structure of the electrical transfer board is the same as that of Embodiment 1, but the formation method is different.
  • the electrical transfer board includes a substrate and a dielectric material layer on the upper surface of the substrate, and an interconnection structure is formed in the dielectric material layer, The interconnection structure is electrically connected to the first pad, and after bonding the chip, a through silicon via structure is formed from the lower surface of the substrate, and a solder ball connected to the through silicon via structure is formed on the lower surface of the substrate, and the other end of the through silicon via structure is electrically connected. Connect the interconnect structure.
  • the dielectric material of each layer of the electrical connection board in the above embodiments includes insulating materials such as silicon dioxide, silicon nitride, or silicon oxynitride, which are formed by a semiconductor deposition process.
  • the interconnect structures located in the dielectric material layer such as interconnect lines and conductive plugs, are also formed by semiconductor deposition and etching processes.
  • the materials of the interconnect structures are all conductive materials, such as copper, titanium, aluminum, gold, and nickel. , iron, tin, silver, zinc or chromium and other metals.
  • the base material is generally a semiconductor material, such as silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbon (SiC), silicon germanium carbon (SiGeC), Indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III/V compound semiconductors, etc.
  • the electrical adapter plate of the present invention is formed on a substrate, the substrate is a wafer, and the electrical adapter plate is at the wafer level.
  • Embodiment 4 provides a wafer-level packaging structure.
  • FIG. 4A shows a schematic diagram of the wafer-level packaging structure of this embodiment.
  • the wafer-level packaging structure includes: an electrical adapter board, and the electrical adapter board includes The opposite upper and lower surfaces, the upper surface exposes at least part of the surface of the first bonding pad 23; at least one chip 30, the chip 30 has a second bonding pad 31 on the surface opposite to the electrical adapter board;
  • the two bonding pads 31 are electrically connected through conductive bumps 24, and the conductive bumps 24 are formed by an electroplating process.
  • the electrical adapter board includes, from bottom to top, a base 10 , and the material of the base 10 is referred to above.
  • a through silicon via structure 11 is formed in the substrate 10 , the lower end of the through silicon via structure 11 is provided with solder balls 50 , and the upper end of the through silicon via structure 11 is connected with the interconnection pad 21 .
  • a dielectric material layer 200 is formed on the upper surface of the substrate 10.
  • the dielectric material layer 200 is a multi-layer structure. The figure shows three layers of dielectric materials, which are the first dielectric material 201 and the second dielectric material from bottom to top.
  • the material 202 and the third dielectric material 203 are formed with conductive plugs 22 penetrating the dielectric material.
  • the conductive plugs 22 can pass through one layer of dielectric material or two or more layers of dielectric materials.
  • the layout is set according to the specific requirements of circuit connection, and interconnect lines 210 are formed at both ends of the conductive plug 22 .
  • the interconnection pad located on the uppermost layer of the electrical transfer board is defined as the first bonding pad 23 .
  • the thickness of the electrical adapter plate is 5-200 microns.
  • a chip 30 is adhered to the upper surface of the electrical transfer board.
  • the chip 30 and the electrical transfer board are bonded by dry film. In other embodiments, it can also be bonded by structural glue.
  • the chip 30 has a second bonding pad 31 on the surface opposite to the electrical adapter board. The type of the chip 30 is referred to above.
  • the lower surface of the chip 30 is higher than the surface of the second bonding pad 31, that is, the second bonding pad 31 is recessed inward relative to the lower surface of the chip 30, and the upper surface of the electrical adapter board is higher than the surface of the first bonding pad 23;
  • the two bonding pads 31 are disposed opposite to the first bonding pad 23 , and the conductive bumps 24 are columnar and connect the second bonding pad 31 and the first bonding pad 23 .
  • the conductive bumps 24 are formed by an electroplating process.
  • the height of the conductive bump 24 and the thickness of the electrical adapter board refer to the above.
  • a plastic encapsulation layer 40 is further provided, and the plastic encapsulation layer 40 covers the electrical adapter board and is filled at least between adjacent chips.
  • the plastic sealing layer 40 seals the conductive bumps 24 to fill the gaps between the chips, and the top surface of the plastic sealing layer 40 is higher than the top surface of the chip or flush with the top surface of the highest chip.
  • the electrical adapter board includes: a dielectric material layer 200 , the surface of the dielectric material layer 200 is higher than the surface of the first pad 23 and exposes part of the first pad 23 ; the dielectric material is embedded
  • the conductive interconnect structure of layer 200 includes conductive plugs 22 penetrating through a single or multi-layer dielectric material layer and interconnect lines 210 connecting the conductive plugs.
  • the bottom surface of the dielectric material layer is provided with solder balls 50, and the solder balls 50 are connected to the interconnection pads 21 of the bottom layer.
  • the structure of this embodiment needs to be electrically connected to the circuit board in the later stage, and the circuit board is provided with a plurality of electrical connection terminals (such as pads) with fixed positions.
  • the pads can be rearranged and connected to the electrical connection terminals on the circuit board.
  • Conductive bumps are formed between the chip and the electrical adapter board through the electroplating process, which solves the problem of vertical multi-layer stacking and facilitates the miniaturization of the package.
  • the main structure of the electrical transfer board can be a dielectric layer, the lower solder balls are located on the lower surface of the dielectric layer, the lower part of the dielectric layer can also include a substrate, the substrate is formed with a through-silicon via structure, and the solder balls are located on the lower surface of the substrate. .
  • the difference between the package structure of this embodiment and the package structure of Example 4B is that the chip 30 is bonded to the electrical adapter board through an adhesive layer 32 , an opening 33 is formed in the adhesive layer, and the chip 30 covers the opening 33 A cavity is formed, and the cavity serves as a working cavity of the chip 30 .
  • the material and thickness of the adhesive layer 32 , the position and structure of the opening, etc. refer to Embodiment 1.

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Abstract

本发明提供了一种晶圆级封装结构及其制造方法，其中，制造方法包括：提供电转接板和至少一个芯片，其中所述电转接板的上表面具有裸露的第一焊垫，所述芯片的下表面具有第二焊垫；物理连接并电连接所述芯片与所述电转接板；其中，所述物理连接包括：通过键合工艺将所述芯片键合在所述电转接板上；所述电连接包括：通过电镀工艺形成导电凸块，使所述第一焊垫和所述第二焊垫通过所述导电凸块电连接。本发明采用电镀工艺形成导电凸块，可以提高良率，满足小型化的要求。

Description

一种晶圆级封装结构及其制造方法 技术领域
本发明涉及半导体封装领域，尤其涉及一种晶圆级封装结构及其制造方法。
 背景技术
目前，为了满足集成电路封装的更低成本、更可靠、更快及更高密度的目标，先进的封装方法主要采用晶圆级系统封装，与传统的系统封装相比，晶圆级系统封装是在晶圆上完成封装集成制程，具有大幅减小封装结构的面积、降低制造成本、优化电性能、批次制造等优势，可明显的降低工作量与设备的需求。
 技术问题
Interposer 中的Silicon Interposer是用硅片做的类似电路板的器件，但其线宽、节点间距等都比电路板小。不同功能的芯片，比如CPU、DRAM等可以连到同一silicon interposer 上面，通过Silicon Interposer完成很多运算和数据交流，这样做比较省电，增加带宽。 类似于PCB，Silicon Interposer一般都有灌铜的通孔(硅通孔)，不同芯片之间联合运算的结果，通过硅通孔传到与之连接的package substrate上，package substrate连接电路板。 所以Silicon Interposer 和package substrate相当于连接多个芯片和同一电路板之间的桥梁。Silicon Interposer的硅通孔制作，传统工艺复杂，硅孔的直径受到限制，通常控制在30微米以内；如果将硅孔做得比较大，硅孔内填充的金属在后期使用时受热膨胀，导致硅孔或绝缘层破裂。因此，只能将硅孔做得较小；但小硅孔内的绝缘物质沉积、阻挡层/种子层沉积、以及填充金属又会变得很困难，因此，工艺控制比较难，良率也比较低，另外电路板上纵向堆叠多层结构，不利于封装的小型化。
因此，期待一种新的晶圆级封装结构及其制造方法。可以提高良率，满足小型化的要求。
 技术解决方案
本发明揭示了一种晶圆级封装结构及其制造方法，能够解决良率低，纵向多层堆叠的问题。为解决上述技术问题，本发明提供了一种晶圆级封装结构的制造方法，包括：提供电转接板和至少一个芯片，其中电转接板的上表面具有裸露的第一焊垫，芯片的下表面具有第二焊垫；物理连接并电连接芯片与电转接板；其中，物理连接包括：通过键合工艺将芯片键合在电转接板上；电连接包括：通过电镀工艺形成导电凸块，使第一焊垫和第二焊垫通过导电凸块电连接。
本发明还提供了一种晶圆级封装结构，包括：电转接板，电转接板包括相对的上、下表面，上表面至少暴露第一焊垫的部分表面；至少一个芯片，芯片与电转接板相对的表面上具有第二焊垫；第一焊垫与第二焊垫之间通过导电凸块电连接，导电凸块通过电镀工艺形成。
 有益效果
本发明的有益效果在于：通过电转接板将不同的芯片与电路板进行电连接，通过电镀工艺在芯片与电转接板之间形成导电凸块，可以同时形成整个电转接板上的导电凸块，提高效率，而且，与半导体的前段工艺兼容，从而可以利用前段工艺完成晶圆级系统集成，使整个系统集成的工艺效率大大提升，节省了前段工艺与封装工艺之间的转接。同时解决了纵向多层堆叠的问题，利于封装的小型化。
进一步地，电转接板与芯片的连接可以先物理连接后电连接，也可以先电连接后物理连接。对于先物理连接的情况，电转接板的第一焊垫和芯片的第二焊垫之间形成空隙，导电凸块形成在空隙中，提高结合强度。且形成完导电凸块后，即可实现第一焊垫和第二焊垫之间电连接，无需其他辅助实现电连接的工艺，简化工艺流程。
进一步地，第一焊垫与第二焊垫在垂直于电转接板表面方向上采用错位设计，重叠区域的面积大于第一焊垫或第二焊垫面积的一半，错位设计可以防止电镀导电凸块时，导电凸块填充不满空隙。错位设计在保证导电凸块填满空隙的基础上，同时保证一定的结合强度。
进一步地，对第二焊垫、第一焊垫的面积、空隙的高度和宽度做出合理的限定，综合衡量导电凸块的形成质量、工艺时间和工艺复杂程度。
进一步地，电镀工艺采用化学镀钯浸金或化学镍金，根据导电凸块的尺寸，选择合适的电镀时间。
进一步地，形成可光刻的键合材料时，其投影以芯片的中心为中心，覆盖面积大于芯片面积的10%，优选覆盖芯片的全部下表面（除第二焊垫所在的区域），这样，在后续工艺形成塑封层时，保证芯片下方没有空隙，提高结合强度，提高成品率。
进一步地，通过干膜键合芯片和电转接板，一方面干膜是可光刻材料，可以通过半导体工艺形成所需的图案样式，工艺简单且与半导体工艺兼容，可批量化生产。而且干膜的弹性模量比较小，在受到热应力时可以很容易变形而不至于破损，减小芯片与器件晶圆的结合应力。光刻干膜时，可以在预形成导电凸块的区域外周保留围墙结构的干膜，这样在形成导电凸块时，由于干膜的阻挡，可以形成预期形状的导电凸块，防止导电凸块横向外溢。当芯片的下方需要形成空腔时，通过在粘合层中形成空腔，可以节省工艺步骤（否则需要在制造芯片时形成空腔）。
进一步地，通过将多个芯片先键合在电转接板上，对多个芯片实现了预对准，因此多个芯片与导电凸块可以同时进行热压键合，相较于将每个芯片和导电凸块依次键合大幅度提高了制造效率。进一步地，第二焊垫与导电凸块在垂直于电转接板表面方向上重叠区域的面积大于第二焊垫面积的一半，以提高两者的结合强度。
进一步地，电转接板可以为介质层，下焊球位于介质层的下表面，介质层的下方也可以包括基板，基板中形成有硅通孔结构，下焊球位于基板的下表面。可以根据实际情况在不同的工艺阶段形成硅通孔结构。
 附图说明
通过结合附图对本发明示例性实施例进行更详细的描述，本发明的上述以及其它目的、特征和优势将变得更加明显，在本发明示例性实施例中，相同的参考标号通常代表相同部件。
图1至图6示出了根据本发明实施例1的一种晶圆级封装方法中不同步骤中对应的结构示意图。
图7和图8示出了根据本发明实施例2的一种晶圆级封装方法中不同步骤中对应的结构示意图。
图9至图12示出了根据本发明实施例3的一种晶圆级封装方法中不同步骤中对应的结构示意图。
附图标记说明：10-基底；11-硅通孔结构；200-介质材料层；201-第一介质材料；202-第二介质材料；203-第三介质材料；21-互连垫；210-互连线；22-导电插塞；23-第一焊垫； 24-导电凸块；30-芯片；31-第二焊垫；32-可光刻的键合材料；33-开口；40-塑封层；50-焊球；60-封盖基板。
 本发明的实施方式
以下结合附图和具体实施例对本发明作进一步详细说明。根据下面的说明和附图，本发明的优点和特征将更清楚，然而，需说明的是，本发明技术方案的构思可按照多种不同的形式实施，并不局限于在此阐述的特定实施例。附图均采用非常简化的形式且均使用非精准的比例，仅用以方便、明晰地辅助说明本发明实施例的目的。应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本发明教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。在此使用时，单数形式的“一”、“一个”和“/该” 也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。如果本文的方法包括一系列步骤，且本文所呈现的这些步骤的顺序并非必须是可执行这些步骤的唯一顺序，且一些的步骤可被省略和/或一些本文未描述的其他步骤可被添加到该方法。若某附图中的构件与其他附图中的构件相同，虽然在所有附图中都可轻易辨认出这些构件，但为了使附图的说明更为清楚，本说明书不会将所有相同构件的标号标于每一图中。
实施例 1
本实施例1提供了一种晶圆级封装结构的制造方法，包括以下步骤：
提供电转接板和至少一个芯片，其中电转接板的上表面具有裸露的第一焊垫，芯片的下表面具有第二焊垫；物理连接并电连接芯片与电转接板；其中，物理连接包括：通过键合工艺将芯片键合在电转接板上；电连接包括：通过电镀工艺形成导电凸块，使第一焊垫和第二焊垫通过导电凸块电连接。芯片的第二焊垫通过电转接板实现重新布局。电转接板与芯片的连接可以先物理连接后电连接，也可以先电连接后物理连接。下面以先电连接后物理连接为例，详细说明各步骤，请参考图1至图6。本发明中可以通过多种方法形成电转接板，下面以一种方法为例进行说明。
参考图1，提供基底10，在基底10的上表面内部形成硅通孔结构11。基底10的材料包括半导体材料，如硅(Si)、锗(Ge)、锗硅 (SiGe)、碳硅(SiC)、碳锗硅(SiGeC)、砷化铟(InAs)、砷化镓(GaAs)、磷化铟(InP)或者其它III/V化合物半导体等。硅通孔结构11仅形成在基底10的上表面内部，没有贯穿基底10的下表面。硅通孔结构11为本领域公知的结构，形成方法为先形成通孔，在通孔的内壁形成绝缘层，在绝缘层的内部形成导电材料，导电材料可以填充满通孔也可以只在通孔的侧壁形成导电材料，本实施例中，导电材料填充满通孔，绝缘层也覆盖了基底10的上表面。
参考图2，在基底10上形成介质材料层200以及贯穿介质材料层200并连接硅通孔结构11的互连结构。本实施例中介质材料层200为多层结构，形成方法为：依次形成每一层介质材料；并形成贯穿单层或多层介质材料的导电插塞22；形成位于介质材料之间、连接导电插塞22的互连线210。本实施例中，示出了3层介质材料，从下至上依次为第一介质材料201、第二介质材料202和第三介质材料203，在介质材料中形成贯穿介质材料的导电插塞22，导电插塞22可以贯穿一层介质材料也可以贯穿两层或者多层介质材料，导电插塞的布局根据电路连接的具体要求设置，在导电插塞22的两端形成互连线210，硅通孔结构11上方形成互连垫21。导电插塞22和互连垫21均为导电材料，如铝、铜、金、钛或者钨等。本实施例中，互连结构包括导电插塞22、互连线210和互连垫21。第一介质材料201、第二介质材料202和第三介质材料203的材料包括氧化硅、氮化硅等，可以通过沉积工艺形成。本实施例中，第三介质材料203的上表面形成有凹槽，暴露出最上层互连垫的一部分表面，凹槽可以在后续形成导电凸块的步骤中提供空间。本文将最上层的互连垫的定义为第一焊垫23。在其他实施例中，第一焊垫23的表面也可以与介质层的上表面齐平或者突出于介质层的上表面。
参考图3A，在电转接板的上表面形成粘合层32，粘合层32用于在后期工艺中将芯片粘合在电转接板的上表面。本实施例中，粘合层32包括膜状干膜或液态干膜，在其他实施例中，也可以选择其他光敏粘合材料。膜状干膜是将无溶剂型光致抗蚀剂涂在涤纶片基上，再覆上聚乙烯薄膜；使用时揭去聚乙烯薄膜，把无溶剂型光致抗蚀剂压于基版上，经曝光显影处理，即可在干膜内形成图形。液态干膜指的是膜状干膜中的成分以液态的形式存在。干膜是一种永久键合膜，粘结强度较高。膜状干膜可以通过贴膜的方式形成在电转接板上，液态干膜通过旋涂工艺涂布在电转接板上，之后对液态干膜进行固化处理。通过干膜键合芯片和电转接板，一方面干膜是可光刻材料，可以通过半导体工艺形成所需的图案样式，工艺简单且与半导体工艺兼容，可批量化生产。而且干膜的弹性模量比较小，在受到热应力时可以很容易变形而不至于破损，减小芯片与电转接板的结合应力。
参考图3B，本实施例中，形成完粘合层32后，还包括：图形化粘合层32，在粘合层32中形成开口33，开口33的深度等于或小于粘合层32的厚度（粘合层32中也可以不形成开口）。形成开口33的区域对应芯片30的工作区域，后期工艺键合芯片后，形成空腔，此空腔作为芯片的工作腔（如热隔离空腔）。当芯片30的下方需要形成空腔时，通过在粘合层32中形成开口33，可以节省工艺步骤（否则需要在制造芯片时形成空腔）。本实施例中，开口33用于隔热，因此对于开口33的深度并不做限定，开口可以贯穿粘合层32（开口深度与粘合层32厚度相同）也可以只贯穿粘合层32的一部分厚度（开口深度小于粘合层32的厚度）。在其他实施例中，如果需要对开口的深度进行限定，则在形成可光刻的键合材料时，形成合适的厚度。对于空腔型体声波谐振器（fbar）和表声波谐振器（SAW）在主体谐振区下方设置有下空腔，上方形成有封盖，封盖和主体谐振区之间形成了上空腔，本实施例中的空腔可以即可以作为上空腔也可以作为下空腔。对于牢固安置型体声波谐振器（SMR），其上方也封盖之间形成有上空腔，本实施例中的空腔可以作为上空腔。对于红外热电堆传感器，其功能区下方设置有用于隔热的隔热空腔，本实施例形成的空腔可以作为隔热空腔。对于超声波传感器，膜状的振动部悬空设置，上表面用于接收超声波，下表面遮盖空腔，本实施例的空腔可以作为超声波传感器的下空腔。
本实施例中，粘合层32形成在电转接板的表面，在另一个实施例中，粘合层32也可以形成在芯片30的表面。粘合层32形成在芯片30的下表面并不影响形成开口33。在一个可选的实施例中，形成完粘合层后，还包括：图形化粘合层，在预形成导电凸块的区域外周形成围墙结构。围墙结构围成的内部为形成导电凸块的区域，围墙结构优选为封闭的环形结构，围成的空间为柱形。光刻粘合层时，在预形成导电凸块的区域外周保留围墙结构的粘合层，这样在形成导电凸块时，由于围墙的阻挡，可以形成预期形状的导电凸块，防止导电凸块横向外溢。
本实施例中，形成的粘合层32的厚度为5-200μm，如15μm、30μm、80μm、150μm等。且粘合层32在电转接板表面方向上的投影以芯片的中心为中心，并至少覆盖芯片面积的10%。具体为，粘合层32的厚度和后期工艺中形成的导电凸块的高度相关。两者的相关性在后面形成导电凸块的时候进行详细介绍。本实施例中，粘合层32至少覆盖芯片面积的10%，其覆盖在芯片的中央位置。因为在后续工艺中形成塑封层时，塑封层不容易填充至芯片的中间位置（因为距离芯片的边缘较远），本方案的粘合层32不但起到粘合的作用，还起到了提前密封的作用，粘合层32和后续工艺中的塑封层共同起到密封芯片的作用。可选方案中，粘合层32覆盖芯片的全部下表面（除第二焊垫所在的区域），这样，在后续工艺形成塑封层时，保证芯片下方没有空隙，提高结合强度，提高成品率。
继续参考图3A和图3B，通过电镀工艺在第一焊垫11上形成导电凸块24。导电凸块的材料包括：铜、钛、铝、金、镍、铁、锡、银、锌或铬中的任意一种。形成的导电凸块24的高度和干膜的高度以及芯片的结构有关系，当芯片的第二焊垫与芯片的下表面相平时，导电凸块24的高度和干膜的高度大致等高，这样芯片和干膜粘合的同时，第二焊垫31与导电凸块24正好相接触。当第二焊垫31相对于芯片20的下表面向下凹陷时，导电凸块24的高度等于凹陷的深度+干膜厚度+芯片20的下表面向下凹陷的深度。可选实施例中，导电凸块的高度为5-200μm。如10μm、50μm、100μm。
电镀工艺包括化学镀钯浸金（ENEPIG）或化学镍金（ENIG），其中ENEPIG或ENIG的工艺参数可以参照表1。
表1
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后期工艺中通过电转接板将不同的芯片与电路板进行电连接，通过电镀工艺在芯片与电转接板之间形成导电凸块，解决了纵向多层堆叠的问题，利于封装的小型化。在进行化学镀之前，为了更好的完成电镀工艺，可以先对焊垫的表面进行清洁，以去除焊垫表面的自然氧化层、提高焊垫的表面湿润度（wetabilities）；之后，可以进行活化工艺，促进镀层金属在待镀金属上的形核生长。为了更好的实现电镀，形成比较完善的导电凸块，第一焊垫、第二焊垫的设置也需要满足一定的要求，比如：第一焊垫暴露出面积为5-200平方微米，在该范围内，焊垫可以与电镀液较充分的接触，避免焊垫与镀液不充分接触而影响导电凸块与焊垫的接触，比如接触面积过小影响电阻，或者，无法接触造成电接触不良；而且，也可以保证接触面积不会过大而降低电镀效率及不会占用过多的面。形成的导电凸块的横截面积大于10平方微米，既可以保证导电凸块占用的面积不会太大，也可以保证导电凸块与焊垫之间的结合强度。可选方案中，导电凸块的材料与第一焊垫的材料相同，这样更容易形成导电凸块。当然，第一焊垫的材料可以与导电凸块的材料不同，为了后续更容易形成导电凸块，可以在第一焊垫上先形成材料层，该材料层的材料与导电凸块的材料相同，形成材料层的方法可以为沉积工艺。
参考图4A和图4B，提供至少一个芯片30，芯片30的下表面具有第二焊垫31。芯片30可以是硅晶圆制成的芯片，也可以是其他材质形成的芯片。芯片30采用集成电路制作技术所制成，可以为存储芯片、通讯芯片、处理器或逻辑芯片。第二焊垫31位于芯片30的下表面，用于实现芯片30与其他器件的电性连接。具体地，第二焊垫31可以是焊盘（Pad）。本实施例中，第二焊垫31的材料包括铜、钛、铝、金、镍、铁、锡、银、锌或铬中的任意一种，优选方案中，第二焊垫和导电凸块的材料组合包括金-金、铜-铜、铜-锡或金-锡。多个第一芯片可以为同功能芯片；多个第一芯片也可以至少包括两种不同功能的芯片；第一芯片为无源器件或者有源器件。第一芯片可以是传感器模组芯片、MEMS芯片、滤波器芯片、逻辑芯片、存储芯片、电容、电感等，电容可以是MLCC电容。传感器模组芯片包括至少传感射频信号、红外辐射信号、可见光信号、声波信号、电磁波信号其中之一的模组芯片；滤波器芯片包括：表面声波谐振器、体声波谐振器至少其中之一。第一芯片可以是经过封装的芯片，则后续无需进行塑封工艺。第一芯片也可以是经过裸芯片，第一芯片也可以是顶面有屏蔽层的芯片。
本实施例中，第二焊垫31和导电凸块24的材料为金属，通过热压键合工艺将第二焊垫31与导电凸块24电连接。每个第二焊垫31与每个导电凸块24逐一进行热压键合；或者多个第二焊垫31与多个导电凸块24同时进行热压键合。通过将多个芯片30先键合在电转接板上，对多个芯片30实现了预对准，因此多个芯片30与导电凸块24可以同时进行热压键合，相较于将每个芯片30和导电凸块24依次键合大幅度提高了制造效率。
本实施例中，第一焊垫23或第二焊垫31的面积为5-200平方微米；第二焊垫31与导电凸块24在垂直于电转接板表面方向上重叠区域的面积大于第二焊垫31面积的一半，以提高两者的结合强度，可选方案中，导电凸块24和第二焊垫31相互正对，即在垂直于电转接板表面方向上，两者最大程度上相互重叠。在可选方案中，导电凸块的横截面积大于10平方微米，以保证结构强度。
本实施例中，多个芯片30逐一键合在电转接板的表面，在另一个实施例中，芯片30具有第二焊垫31的面为正面，与正面相背的面为背面，芯片30键合于电转接板之前，将芯片30的背面临时键合于基板上；将芯片键合在电转接板上后，解键合基板。基板可以是载体晶圆，用于临时固定多个芯片30，基板还用于在芯片30与电转接板键合的过程中，为芯片30起到支撑作用，从而提高键合的可靠性。芯片30通过粘合层或静电键合临时键合于基板上。静电键合技术是不用任何粘结剂实现键合的一种方法。在键合过程中，将要键合的芯片和基板分别连接不同的电极，在电压作用下使芯片和基板表面形成电荷，且芯片与基板表面电荷电性不同，从而在芯片与基板键合过程中产生较大的静电引力，实现两者的物理连接。相应地，在解键合的过程中，可以通过化学方法或机械剥离的方式使基板与芯片相分离。
参考图5，本实施例中（以粘合层中形成有开口33为例），键合芯片20后还包括：形成塑封层40，塑封层40至少填充于相邻的芯片之间。其他实施例中，也可以不形成塑封层。本实施例中，封装层40覆盖电转接板的表面及芯片30，也就是说，封装层40填充于芯片30之间的间隙且覆盖在芯片30上.塑封层实现对芯片的密封，从而更好地隔绝空气和水分，进而提高了封装效果。具体地，可以通过注塑工艺形成封装层40。注塑工艺的填充性能较好，可以使注塑剂较好地填充在多个芯片30之间，从而使芯片30具有良好的封装效果。在其他实施例中，还可以采用其他工艺形成封装层。另外，根据芯片的不同性能，芯片的上表面也可以暴露在塑封层的外部。继续参考图5，本实施例中，形成塑封层40后，本方法还包括：对基底10的下表面进行减薄，暴露出硅通孔结构11，并形成连接硅通孔结构11的焊球50。可以通过研磨工艺对基底10的下表面进行减薄，暴露出硅通孔结构11的下端，由于硅通孔结构11的下端有绝缘层，也需要去掉绝缘层，之后可以通过电镀工艺或沉积工艺形成焊球50。
本实施例中，电转接板包括基底10，设置于基底10中的硅通孔结构11，基底10上方的多层介质材料，以及位于介质材料中的导电插塞22、互连垫21，第一焊垫23、焊球50。电转接板的整体厚度为5-200微米，如10微米、20微米、50微米、100微米等。以上步骤完成后，需要将上述结构电连接到PCB板上，PCB板上设有位置固定的多个电连接端（如焊盘），本实施例中，通过电转接板实现了将芯片的第一焊垫实现重新布局，与PCB板上的电连接端进行匹配电连接，通过电转接板将不同的芯片与电路板进行电连接，解决了纵向多层堆叠的问题，利于封装的小型化。通过对基底10的背面进行减薄处理，以减小电转接板的厚度，从而改善电转接板的散热效果；此外，减小电转接板的厚度还有利于减小封装后封装结构的整体厚度，进而提高封装结构的性能。本实施例中，减薄处理所采用的工艺可以为背部研磨工艺、化学机械抛光 (Chemical Mechanical Polishing，CMP)工艺和湿法刻蚀工艺中的一种或多种。为了有效控制减薄处理的停止位置，通常在基底内形成用于限定停止位置的深沟槽隔离结构，从而使减薄处理停止于深沟槽隔离结构的底部。在另一实施例中，还可以在电转接板的制造工艺中，采用中性掺杂离子（例如氧离子和氮离子中的一种或两种）在基底内形成停止区，从而使减薄处理停止于停止区的底部。在其他实施例中，当基底为绝缘体上的硅衬底或者绝缘体上的锗衬底时，还可以对半导体衬底的底部衬底层进行减薄处理，从而能够较好地停止于绝缘体层的底部。
参考图6，在一个实施例中，键合芯片30后（图4B之后），方法还包括：提供封盖基板60，封盖基板60的第一表面包含空腔，键合封盖基板60的第一表面与电转接板，并使空腔至少遮盖芯片30的一部分。封盖基板60的材料可以为：可以为硅、锗、锗化硅、碳化硅、砷化镓或镓化铟等半导体材料，也可以是介质材料。参考图6，空腔可以较大，一个空腔同时覆盖多个芯片30。其他实例中，空腔为多个较小的小空腔，每个小空腔容纳一个或多个芯片30。在可选的实施例中，封盖基板的一个小空腔也可以只容纳一个芯片的一部分，如对于体声波谐振器或者表声波谐振器或者红外热堆传感器，芯片需要形成有空腔结构，并且空腔结构对应芯片结构的功能区，并不是将整个芯片包括在空腔中。如对于体声波谐振器或者表声波谐振器或者红外热堆传感器，芯片需要形成有空腔结构，并且空腔结构对应芯片结构的功能区，并不是将整个芯片包括在空腔中。如对于体声波谐振器（BAW）和表声波谐振器（SAW）以及牢固安置型体声波谐振器（SMR）在主体谐振区上方设置有上空腔，本实施例中的空腔可以作为上空腔，对于红外热电堆传感器，其功能区下方设置有用于隔热的隔热空腔，本实施例形成的空腔可以作为隔热空腔，对于超声波传感器，膜状的振动部悬空设置，上表面用于接收超声波，下表面遮盖空腔，本实施例的空腔可以作为超声波传感器的下空腔。可选实施例中，封盖基板键合在电转接板上后，形成的空腔为密封的空腔，可以防止外界环境对空腔内器件的污染（水分、灰尘、油脂等）。在一个实施例中，在封盖基板上形成电连接结构，将芯片的电性引出。
实施例 2
本实施例的芯片与电转接板先进行物理连接后进行电连接，下面简要说明实施例2与实施例1的不同之处。
依次参照图1、图2和图7，按照实施例1的方式准备好电转接板和芯片后，物理粘结电转接板和芯片，使第一焊垫23和第二焊垫31相对，且第一焊垫23与第二焊垫31之间形成空隙；参照图8，采用电镀工艺在空隙中形成导电凸块，第一焊垫与第二焊垫之间通过导电凸块电连接。具体地，提供至少一个芯片30（本实施例中为多个芯片）。本实施例中，芯片30的表面高于第二焊垫31的表面，即第二焊垫31相对于芯片30的下表面向内凹陷。在其他实施例中，第二焊垫31的表面也可以和芯片的底面齐平或者凸出于芯片的表面。值得说明的是，本实施例中，通过可光刻的键合材料32将芯片30粘合在介质层的上表面（也为电转接板的上表面）。本实施例中，可光刻的键合材料32中没有形成开口，其他实例中，根据器件的类型，可以在可光刻的键合材料32中形成开口，使开口与器件的功能区相对设置。可光刻的键合材料的选材、厚度，形成位置参照实施例1，此处不再赘述。在其他实施例中，也可以用结构胶将芯片30粘合在介质层的上表面。需要说明的是，本实施例中，将芯片30粘合在介质层表面时，使第二焊垫23和第一焊垫31相对，且第二焊垫23与第一焊垫31之间形成空隙。本实施例中，第二焊垫23与第一焊垫31在垂直于电转接板表面方向上的投影相互交错，且投影重叠区域的面积大于第二焊垫23或第一焊垫31面积的一半。第一焊垫31与第二焊垫23在垂直于电转接板表面方向上采用错位设计，错位设计可以防止电镀导电凸块24时，导电凸块24填充不满空隙。错位设计在保证导电凸块24填满空隙的基础上，同时保证一定的结合强度。
本实施例是通过电转接板的表面高于第一焊垫23的表面，芯片30的表面高于第二焊垫31的表面形成的空隙。在其他实施例中，也可以只是电转接板的表面高于第一焊垫23的表面，或者只是芯片30的表面高于第二焊垫31的表面，还可以是其他结构形式，只要第一焊垫23和第二焊垫31之间形成空隙即可。最后采用电镀工艺填充空隙，形成导电凸块24，使第一焊垫23与第二焊垫31之间通过导电凸块24电连接。
实施例 3
本实施例与实施例1的区别在于形成电转接板的方法不同。请参考图8至图11，简略说明各步骤。
参考图9，提供基底10，在基底10上形成介质材料层200以及贯穿介质材料层200的导电插塞22，连接导电插塞22并暴露于介质材料层200顶面的第一焊垫23。本实施例中，介质材料层200以及贯穿介质材料层200的导电插塞22以及第一焊垫23的结构和材料和形成方法参照实施例1，此处不再赘述，需要说明书的是，虽然本实施例不需要形成硅通孔结构，但是在工艺的后期也需要形成焊球，因此在基底10的上表面形成了互连垫21，用于连接焊球。
参考图10，按照实施例1或2的方法形成导电凸块24，并将芯片30粘合在电转接板的上表面，在电转接板的上表面形成塑封层40，塑封层40密封导电凸块24并填满芯片30之间的空隙。上述步骤的具体细节参照实施例1。
参考图11，对基底的下表面做减薄处理，并从减薄后的下表面形成硅通孔结构11，硅通孔结构11上端连接互连垫21，下端形成焊球50。也可以不形成硅通孔结构，参考图11，去除基底，暴露出底层的互连垫21的下表面，在互连垫21的下表面形成焊球50。在另一个实施例中，电转接板的结构与实施例1相同，但是形成方法不同，电转接板包括基底以及位于基底上表面的介质材料层，介质材料层中形成有互连结构，互连结构电连接第一焊垫，键合芯片后，从基底的下表面形成硅通孔结构，并在基底的下表面形成连接硅通孔结构的焊球，硅通孔结构的另一端电连接互连结构。
以上实施例的电转接板的每层介质材料包括二氧化硅、氮化硅或氮氧化硅等绝缘材料，其通过半导体沉积工艺形成。位于介质材料层中的互连结构，如互连线和导电插塞也均是通过半导体沉积、刻蚀工艺形成，互连结构的材料均为导电材料，如铜、钛、铝、金、镍、铁、锡、银、锌或铬等金属。对于可选中包括基底的电转接板，其基底的材料一般为半导体材料，如硅(Si)、锗(Ge)、锗硅 (SiGe)、碳硅(SiC)、碳锗硅(SiGeC)、砷化铟(InAs)、砷化镓(GaAs)、磷化铟(InP)或者其它III/V化合物半导体等。
需要说明的是，本发明的电转接板形成在基底上，基底为晶圆，电转接板为晶圆级。
实施例 4
实施例4提供了一种晶圆级封装结构，图4A示出了本实施例的晶圆级封装结构示意图，参考图4A，晶圆级封装结构包括：电转接板，电转接板包括相对的上、下表面，上表面至少暴露第一焊垫23的部分表面；至少一个芯片30，芯片30与电转接板相对的表面上具有第二焊垫31；第一焊垫23与第二焊垫31之间通过导电凸块24电连接，导电凸块24通过电镀工艺形成。
参考图6，本实施例中，电转接板从下至上包括：基底10，基底10的材料参照上文。基板10中形成有硅通孔结构11，硅通孔结构11的下端设有焊球50，硅通孔结构11的上端连接有互连垫21。基底10的上表面形成有介质材料层200，本实施例中，介质材料层200为多层结构，图中示出了3层介质材料，从下至上依次为第一介质材料201、第二介质材料202和第三介质材料203，在介质材料中形成有贯穿介质材料的导电插塞22，导电插塞22可以贯穿一层介质材料也可以贯穿两层或者多层介质材料，导电插塞22的布局根据电路连接的具体要求设置，导电插塞22的两端形成有互连线210。其中位于电转接板最上层的互连垫定义为第一焊垫23。电转接板的厚度为5-200微米。
电转接板的上表面粘合有芯片30，本实施例中，芯片30与电转接板通过干膜粘合。在其他实施例中，也可以通过结构胶粘合。芯片30与电转接板相对的表面上具有第二焊垫31。芯片30的种类参照前文。芯片30的下表面高于第二焊垫31的表面，即第二焊垫31相对于芯片30的下表面向内凹陷，电转接板的上表面高于第一焊垫23的表面；第二焊垫31与第一焊垫23相对设置，导电凸块24为柱状，连接第二焊垫31与第一焊垫23。导电凸块24通过电镀工艺形成。导电凸块24的高度，电转接板的厚度参照前文。本实施例中，还设有塑封层40，塑封层40覆盖电转接板，且至少填充于相邻的芯片之间。可选实施例中，塑封层40密封导电凸块24，填满芯片之间的空隙，塑封层40的顶面高于芯片的顶面或与芯片中最高者的顶面齐平。
在另一个实施例中，参考图11，电转接板包括：介质材料层200，介质材料层200的表面高于第一焊垫23的表面，并暴露部分第一焊垫23；嵌入介质材料层200的导电互连结构，导电互连结构包括贯穿单层或多层介质材料层的导电插塞22以及连接导电插塞的互连线210。介质材料层的底面设有焊球50，焊球50连接底层的互连垫21。
本实施例的结构后期需要电连接到电路板上，电路板上设有位置固定的多个电连接端（如焊盘），本实施例中，通过电转接板实现了将芯片的第二焊垫实现重新布局，与电路板上的电连接端进行匹配电连接，通过电镀工艺在芯片与电转接板之间形成导电凸块，解决了纵向多层堆叠的问题，利于封装的小型化。进一步地，电转接板的主体结构可以为介质层，下焊球位于介质层的下表面，介质层的下方也可以包括基底，基底中形成有硅通孔结构，焊球位于基底的下表面。
实施例 5
参照图4B，本实施例的封装结构与实施例4B封装结构的区别为，芯片30通过粘合层32粘结在电转接板上，粘合层中形成有开口33，芯片30遮盖开口33形成空腔，空腔作为芯片30的工作腔。粘合层32的材料、厚度，开口的位置结构等参照实施例1。
需要说明的是，本说明书中的各个实施例均采用相关的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于结构实施例而言，由于其基本相似于方法实施例，所以描述的比较简单，相关之处参见方法实施例的部分说明即可。上述描述仅是对本发明较佳实施例的描述，并非对本发明范围的任何限定，本发明领域的普通技术人员根据上述揭示内容做的任何变更、修饰，均属于权利要求书的保护范围。

Claims (20)

  1. 一种晶圆级封装结构的制造方法，其特征在于，包括：提供电转接板和至少一个芯片，其中所述电转接板的上表面具有裸露的第一焊垫，所述芯片的下表面具有第二焊垫；物理连接并电连接所述芯片与所述电转接板；其中，所述物理连接包括：通过键合工艺将所述芯片键合在所述电转接板上；所述电连接包括：通过电镀工艺形成导电凸块，使所述第一焊垫和所述第二焊垫通过所述导电凸块电连接。
  2. 如权利要求1所述的晶圆级封装结构的制造方法，其特征在于，所述物理连接并电连接所述芯片与所述电转接板包括：通过电镀工艺在所述第一焊垫上形成所述导电凸块；形成所述导电凸块后，将所述芯片键合在所述电转接板上，并使所述芯片的所述第二焊垫与所述导电凸块电连接；或者，粘结所述电转接板和所述芯片，使所述第一焊垫和所述第二焊垫相对，且所述第一焊垫与所述第二焊垫之间形成空隙；采用电镀工艺在所述空隙中形成导电凸块，所述第一焊垫与所述第二焊垫之间通过所述导电凸块电连接。
  3. 如权利要求1所述的晶圆级封装结构的制造方法，其特征在于，所述物理连接并电连接所述芯片与所述电转接板包括：通过电镀工艺在所述第一焊垫上形成所述导电凸块；形成所述导电凸块后，在所述芯片的下表面或所述电转接板的上表面形成粘合层；并在所述粘合层中形成开口；通过所述粘合层将所述芯片键合在所述电转接板上，所述芯片遮盖所述开口形成空腔，所述空腔作为所述芯片的工作腔；并使所述芯片的第一焊垫与所述导电凸块电连接。
  4. 如权利要求1所述的晶圆级封装结构的制造方法，其特征在于，所述物理连接包括：通过可光刻的键合材料将所述芯片粘合在所述电转接板上。
  5. 根据权利要求4所述的晶圆级封装方法，其特征在于，所述可光刻的键合材料包括：膜状干膜或液态干膜。
  6. 根据权利要求1所述的晶圆级封装方法，其特征在于，所述电镀工艺包括：化学镀钯浸金，其中化学镍的时间为30-50分钟，化学金的时间为4-40分钟，化学钯的时间为7-32分钟；或，所述电镀工艺包括化学镍金，其中化学镍的时间为30-50分钟，化学金的时间为4-40分钟。
  7. 根据权利要求1所述的晶圆级封装方法，其特征在于，所述第一焊垫或所述第二焊垫的面积为5-200平方微米；和/或，所述导电凸块的横截面积大于10平方微米；和/或所述导电凸块的高度为5-200微米。
  8. 根据权利要求2所述的晶圆级封装方法，其特征在于，所述第二焊垫和所述导电凸块的材料为金属，通过热压键合工艺将所述第二焊垫与所述导电凸块电连接。
  9. 根据权利要求8所述的晶圆级封装方法，其特征在于，每个所述第二焊垫与每个所述导电凸块逐一进行热压键合；或者多个所述第二焊垫与多个所述导电凸块同时进行热压键合。
  10. 根据权利要求1所述的晶圆级封装方法，其特征在于，所述第二焊垫与所述导电凸块的材料组合包括金-金、铜-铜、铜-锡或金-锡。
  11. 根据权利要求1所述的晶圆级封装方法，其特征在于，所述第一焊垫与所述第二焊垫在垂直于所述电转接板表面方向上的投影相互交错，且所述投影重叠区域的面积大于所述第一焊垫或所述第二焊垫面积的一半。
  12. 根据权利要求3所述的晶圆级封装方法，其特征在于，所述粘合层在所述电转接板表面方向上的投影以所述芯片的中心为中心，并至少覆盖所述芯片面积的10%。
  13. 如权利要求1所述的晶圆级封装结构的制造方法，其特征在于，形成所述电转接板包括：提供基底，在所述基底上形成介质材料层以及位于所述介质材料层中的互连结构；形成连接所述互连结构并暴露于所述介质材料层顶面的所述第一焊垫；
    去除所述基底，在所述介质材料层的下表面形成连接所述互连结构的下焊球；
    或，提供基底，在所述基底的上表面内部形成硅通孔结构，在所述基底上形成介质材料层以及位于所述介质材料层中、并连接所述硅通孔结构的互连结构；形成所述导电凸块后，对所述基底的下表面进行减薄，暴露出所述硅通孔结构，并形成连接所述硅通孔结构的下焊球；或，所述电转接板包括基底以及位于所述基底上表面的介质材料层，所述介质材料层中形成有互连结构，所述互连结构电连接所述第一焊垫，形成所述导电凸块后，从所述基底的下表面形成硅通孔结构，并在所述基底的下表面形成连接所述硅通孔结构的下焊球，所述硅通孔结构的另一端电连接所述互连结构。
  14. 根据权利要求1所述的晶圆级封装方法，其特征在于，所述芯片具有第二焊垫的面为正面，与正面相背的面为背面，所述芯片键合于所述电转接板之前，将所述芯片的背面临时键合于基板上；将所述芯片键合在所述电转接板上后，解键合所述基板。
  15. 根据权利要求14所述的晶圆级封装方法，其特征在于，所述芯片通过键合层或静电键合临时键合于所述基板上。
  16. 根据权利要求1所述的晶圆级封装方法，其特征在于，物理连接并电连接所述芯片与所述电转接板后，所述方法还包括：提供封盖基板，所述封盖基板的第一表面包含空腔，键合所述封盖基板的第一表面与所述电转接板，并使所述空腔至少遮盖所述芯片的一部分；或者，形成塑封层，所述塑封层至少填充于相邻的所述芯片之间。
  17. 根据权利要求3所述的晶圆级封装方法，其特征在于，形成完所述粘合层后，所述方法还包括：图形化所述粘合层，在预形成所述导电凸块的区域外周形成围墙结构。
  18. 一种晶圆级封装结构，其特征在于，包括：电转接板，所述电转接板包括相对的上、下表面，上表面至少暴露第一焊垫的部分表面；至少一个芯片，所述芯片与所述电转接板相对的表面上具有第二焊垫；所述第一焊垫与所述第二焊垫之间通过导电凸块电连接，所述导电凸块通过电镀工艺形成。
  19. 如权利要求18所述的晶圆级封装结构，其特征在于，所述电转接板包括：介质材料层，所述介质材料层的表面高于所述第一焊垫的表面，并暴露部分所述第一焊垫；嵌入所述介质材料层的导电互连结构，所述导电互连结构包括贯穿单层或多层所述介质材料层的导电插塞以及位于所述导电插塞两端的互连垫，所述介质材料层的底面设有焊球，所述焊球连接底层的所述互连垫；或者，所述电转接板包括：基底，所述基底中设有贯穿所述基底的硅通孔结构；介质材料层，设置于所述基底的上表面，所述介质材料层的表面高于所述第一焊垫的表面，并暴露部分所述第一焊垫；嵌入所述介质材料层的导电互连结构，所述导电互连结构包括贯穿单层或多层所述介质材料层的导电插塞以及位于所述导电插塞两端的互连垫；焊球，位于所述基底的底面，所述硅通孔结构一端连接于底层的所述互连垫，另一端连接于所述焊球。
  20. 如权利要求18所述的晶圆级封装结构，其特征在于，所述芯片通过粘合层粘结在所述电转接板上，所述粘合层中形成有开口，所述芯片遮盖所述开口形成空腔，所述空腔作为所述芯片的工作腔。
PCT/CN2022/072999 2021-01-29 2022-01-20 一种晶圆级封装结构及其制造方法 WO2022161249A1 (zh)

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