CN108666264A - 晶圆级系统封装方法及封装结构 - Google Patents

晶圆级系统封装方法及封装结构 Download PDF

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Publication number
CN108666264A
CN108666264A CN201810416799.0A CN201810416799A CN108666264A CN 108666264 A CN108666264 A CN 108666264A CN 201810416799 A CN201810416799 A CN 201810416799A CN 108666264 A CN108666264 A CN 108666264A
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China
Prior art keywords
hole
chip
adhesive layer
device wafers
back side
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CN201810416799.0A
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CN108666264B (zh
Inventor
刘孟彬
罗海龙
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China Core Integrated Circuit Ningbo Co Ltd
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China Core Integrated Circuit Ningbo Co Ltd
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Priority to KR1020207022047A priority Critical patent/KR102400264B1/ko
Priority to PCT/CN2018/101763 priority patent/WO2019210617A1/zh
Priority to JP2020562809A priority patent/JP7027577B2/ja
Publication of CN108666264A publication Critical patent/CN108666264A/zh
Priority to US16/206,037 priority patent/US10861821B2/en
Priority to US17/078,944 priority patent/US11309279B2/en
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Publication of CN108666264B publication Critical patent/CN108666264B/zh
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Abstract

一种晶圆级系统封装方法及封装结构，方法包括：提供器件晶圆，包括集成有多个第一芯片的第一正面以及与第一正面相背的第一背面；提供多个第二芯片；在第一正面形成粘合层；图形化粘合层，在粘合层内形成多个露出第一正面的第一通孔；将第二芯片设置于剩余粘合层上，第二芯片与第一通孔一一对应且覆盖第一通孔顶部，并使器件晶圆和第二芯片键合；刻蚀第一背面，在器件晶圆内形成与第一通孔相贯通的第二通孔，第二通孔和第一通孔构成第一导电通孔；在第一导电通孔内形成与第二芯片电连接的第一导电柱。本发明通过先形成第一通孔再形成第二通孔，避免出现第一通孔开口尺寸大于第二通孔开口尺寸的问题，从而改善第一导电柱的电性连接性能。

Description

晶圆级系统封装方法及封装结构
技术领域
本发明涉及半导体制造领域，尤其涉及一种晶圆级系统封装方法及封装结构。
背景技术
随着超大规模集成电路的发展趋势，集成电路特征尺寸持续减小，人们对集成电路的封装技术的要求相应也不断提高。现有的封装技术包括球栅阵列封装(Ball GridArray，BGA)、芯片尺寸封装(Chip Scale Package，CSP)、晶圆级封装(Wafer LevelPackage，WLP)、三维封装(3D)和系统封装(SiP)等。
系统封装可以将多个不同功能的有源元件、无源元件、微机电系统(MEMS)、光学元件等其他元件组合到一个单元中，形成一个可提供多种功能的系统或子系统，允许异质IC集成。相比于系统级芯片(System on Chip，SoC)，系统封装的集成相对简单，设计周期和面市周期更短，成本较低，可以实现更复杂的系统。
目前，为了满足集成电路封装的更低成本、更可靠、更快及更高密度的目标，先进的封装方法主要采用晶圆级系统封装(Wafer Level Package System in Package，WLPSiP)，与传统的系统封装相比，晶圆级系统封装是在器件晶圆上完成封装集成制程，具有大幅减小封装结构的面积、降低制造成本、优化电性能、批次制造等优势，可明显的降低工作量与设备的需求。
但是，现有技术晶圆级系统封装容易导致封装结构的性能和可靠性下降。
发明内容
本发明解决的问题是提供一种晶圆级系统封装方法及封装结构，提高封装结构的性能和可靠性。
为解决上述问题，本发明提供一种晶圆级系统封装方法，包括：提供器件晶圆，所述器件晶圆包括集成有多个第一芯片的第一正面以及与所述第一正面相背的第一背面；提供多个第二芯片；在所述器件晶圆的第一正面形成可光刻的粘合层；图形化所述粘合层，在所述粘合层内形成多个露出所述第一正面的第一通孔；图形化所述粘合层后，将所述第二芯片设置于剩余粘合层上，所述第二芯片与所述第一通孔一一对应且覆盖所述第一通孔的顶部，并使所述器件晶圆和所述第二芯片键合；刻蚀所述器件晶圆的第一背面，在所述器件晶圆内形成贯穿所述器件晶圆且与所述第一通孔相贯通的第二通孔，所述第二通孔和所述第一通孔构成第一导电通；在所述第一导电通孔内形成与所述第二芯片电连接的第一导电柱。
相应的，本发明还提供一种封装结构，包括：器件晶圆，所述器件晶圆包括集成有多个第一芯片的第一正面以及与所述第一正面相背的第一背面；粘合层，位于所述器件晶圆的第一正面，所述粘合层内具有多个露出所述第一正面的通孔；与所述器件晶圆相键合的多个第二芯片，所述第二芯片设置于所述粘合层上，所述第二芯片与所述通孔一一对应且覆盖所述通孔的顶部。
与现有技术相比，本发明的技术方案具有以下优点：
本发明在实现所述器件晶圆和所述第二芯片的键合之前，在所述器件晶圆的第一正面形成粘合层，并对所述粘合层进行图形化，在所述粘合层内形成多个露出所述第一正面的第一通孔，所述第一通孔与所述第二芯片一一对应；与依次刻蚀所述器件晶圆的第一背面和粘合层，先后在所述器件晶圆内形成第二通孔、在所述粘合层内形成与所述第二通孔相贯通的第一通孔的方案相比，本发明通过先在所述粘合层内形成第一通孔，再刻蚀所述第一背面以形成第二通孔的方案，能够避免出现所述粘合层的横向刻蚀严重的问题，从而避免出现所述第一通孔开口尺寸大于所述第二通孔开口尺寸的问题；相应的，后续在第一导电通孔内形成与所述第二芯片电连接的第一导电柱时，有利于降低所述第一导电柱在所述第一通孔内的形成难度、提高所述第一导电柱在所述第一通孔内的形成质量，从而改善所述第一导电柱的电性连接性能，进而优化封装结构的性能和可靠性。
可选方案中，图形化所述粘合层后，剩余粘合层覆盖所述第二芯片对应位置的第一正面，相应的，当后续在所述第一正面形成覆盖所述第二芯片的封装层时，所述封装层与所述第二芯片露出的第一正面实现良好的接触，从而有利于提高所述封装层的绝缘、密封及防潮的作用。
附图说明
图1至图4是一种封装方法各步骤对应的结构示意图；
图5至图14是本发明晶圆级系统封装方法一实施例中各步骤对应的结构示意图；
图15至图17是本发明晶圆级系统封装方法另一实施例中各步骤对应的结构示意图；
图18是本发明封装结构一实施例的结构示意图；
图19是本发明封装结构另一实施例的结构示意图。
具体实施方式
由背景技术可知，晶圆级系统封装容易导致封装结构的性能和可靠性下降。现结合一种晶圆级系统封装方法分析其性能和可靠性下降的原因。
图1至图4是一种封装方法各步骤对应的结构示意图。
参考图1，提供第一器件晶圆10，所述第一器件晶圆10包括集成有多个第一芯片11的第一正面12以及与所述第一正面12相背的第一背面13。
所述第一器件晶圆10用于作为封装工艺中的待集成晶圆，在完成封装制程后，对所述第一器件晶圆10进行封装测试后再进行切割以获得单个成品芯片。
参考图2，提供多个第二芯片31，所述第二芯片31包括具有半导体器件的第二正面(未标示)以及与所述第二正面相背的第二背面(未标示)，所述第二正面和第二背面中的任一面上形成有粘合层20。
所述第二芯片31用于作为封装工艺中的待集成芯片，通过将多个不同功能的第二芯片31整合至一个封装结构中，以实现晶圆级系统封装。
目前，提供所述第二芯片31的步骤包括：提供多个功能不同的第二器件晶圆，每一个第二器件晶圆包括集成有所述第二芯片31的第三正面以及与所述第三正面相背的第三背面；在所述第三正面和第三背面中的任一面上形成粘合膜；对所述多个第二器件晶圆以及位于所述第二器件晶圆上的粘合膜进行切割，获得多个功能不同的第二芯片31以及位于所述第二芯片31任一面上的粘合层20。
继续参考图2，将所述粘合层20固定于所述第一正面12上，通过所述粘合层20实现所述第一器件晶圆10和所述第二芯片31的粘贴结合。
参考图3，在所述第一正面12(如图2所示)形成覆盖所述第二芯片31的封装层40；形成所述封装层40后，通过所述第一背面13(如图2所示)对所述第一器件晶圆10进行减薄处理。
参考图4，采用硅通孔(Through-Silicon Via，TSV)刻蚀工艺，依次刻蚀所述第一背面13和粘合层20，在所述第一器件晶圆10内形成第一通孔15，在所述粘合层20内形成与所述第一通孔15相贯通且露出所述第二芯片31的第二通孔25，所述第二通孔25和所述第一通孔15构成导电通孔；其中，所述导电通孔的延伸方向为第一方向，与所述第一方向以及所述第一正面12(如图2所示)法线方向相垂直的为第二方向(如图4中AA1方向所示)。
晶圆级系统封装主要包括物理连接和电性连接这两个重要工艺，所述粘合层20通常为有机材料，用于实现所述第二芯片31和所述第一器件晶圆10之间的物理连接，并通过硅通孔刻蚀和电镀技术实现所述第一芯片11和第二芯片31与其他电路之间的电性连接、以及所述第一芯片11和第二芯片31之间的电性连接。
硅通孔刻蚀所采用的工艺通常为反应离子干法刻蚀(Reactive Ion Etching)工艺，刻蚀形成所述第一通孔15后，所述第二通孔25的开口尺寸L2(如图4所示)和形貌主要根据所述第一通孔15的形貌和刻蚀制程而定。
其中，在干法刻蚀过程中会生成不和刻蚀气体反应的聚合物(Polymer)副产物，所述副产物容易附着于开口侧壁以阻止横向刻蚀(即沿所述第二方向的刻蚀)，但是由于所述粘合层20为有机材料，所述刻蚀气体主要为O2，且干法刻蚀过程中所生成的副产物大部分为气体，因此在刻蚀所述粘合层20的过程中，所述第二通孔25的侧壁难以得到保护，横向刻蚀相应较为严重；所以，形成所述第二通孔25后，所述第二通孔25容易出现开口尺寸L2变大的问题，即所述第一通孔15的开口尺寸L1(如图4所示)小于所述第二通孔25的开口尺寸L2。其中，所述第一通孔15的开口尺寸L1指的是所述第一通孔15沿所述第二方向的尺寸，所述第二通孔25的开口尺寸L2指的是所述第二通孔25沿所述第二方向的尺寸。
而且，当所述粘合层20的厚度较大时，所述第二通孔25出现开口尺寸L2变大的问题更为明显。
为了实现半导体器件之间的电性连接，后续还需通过电镀技术在所述导电通孔内形成导电柱，由于所述第一通孔15的开口尺寸L1小于所述第二通孔25的开口尺寸L2，因此在靠近所述第二通孔25侧壁的位置处，所述第一器件晶圆10和所述第二芯片31之间容易形成缝隙(如图4中虚线圈所示)，相应的，所述导电柱的材料难以较好地填充于所述缝隙中，甚至所述缝隙中无法形成所述导电柱，从而降低所述导电柱的电性连接性能，进而导致封装结构的性能和可靠性下降。
为了解决所述技术问题，本发明在实现所述器件晶圆和所述第二芯片的键合之前，在所述器件晶圆的第一正面形成粘合层，并对所述粘合层进行图形化，在所述粘合层内形成多个露出所述第一正面的第一通孔，所述第一通孔与所述第二芯片一一对应；与依次刻蚀所述器件晶圆的第一背面和粘合层，先后在所述器件晶圆内形成第二通孔、在所述粘合层内形成与所述第二通孔相贯通的第一通孔的方案相比，本发明通过先形成第一通孔，再刻蚀所述第一背面以形成第二通孔的方案，能够避免出现所述粘合层的横向刻蚀严重的问题，从而避免出现所述第一通孔开口尺寸大于所述第二通孔开口尺寸的问题；相应的，后续在第一导电通孔内形成与所述第二芯片电连接的第一导电柱时，有利于降低所述第一导电柱在所述第一通孔内的形成难度、提高所述第一导电柱在所述第一通孔内的形成质量，从而改善所述第一导电柱的电性连接性能，进而优化封装结构的性能和可靠性。
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
图5至图14是本发明晶圆级系统封装方法一实施例中各步骤对应的结构示意图。
参考图5，提供器件晶圆(CMOS Wafer)100，所述器件晶圆100包括集成有多个第一芯片110的第一正面121以及与所述第一正面121相背的第一背面122。
所述器件晶圆100为完成器件制作的晶圆，所述器件晶圆100用于作为封装工艺中的待集成晶圆。
本实施例中，所述器件晶圆100适于实现晶圆级系统封装。其中，晶圆级系统封装指的是将多个不同功能的有源元件、无源元件、微机电系统、光学元件等其他元件集成至一个器件晶圆上，再进行切割以获得单个封装体的技术。晶圆级系统封装具有高效率、高密度、体积小、成品率高和电热性能优良等优点，因此能够满足不断提高的封装工艺要求。
在其他实施例中，所述器件晶圆还可适于实现晶圆级封装工艺。其中，晶圆级封装指的是直接在器件晶圆上进行大部分或全部的封装测试程序，再进行切割以获得单个成品芯片的技术。
继续参考图5，在所述器件晶圆100的第一正面121形成可光刻的粘合层200。
所述粘合层200为粘性材料，经后续的图形化工艺后，剩余粘合层200适于实现所述器件晶圆100与待集成芯片的粘贴结合。
本实施例中，所述粘合层200为可光刻的粘性材料，因此后续通过曝光显影的方式即可对所述粘合层200进行图形化处理，相应可以避免额外刻蚀工艺的采用，从而简化了后续图形化所述粘合层200的工艺步骤，有利于降低工艺成本、提高封装效率；而且，通过曝光显影的方式图形化所述粘合层200，还能够避免对所述粘合层200的粘性产生影响。
为此，本实施例中，所述粘合层200的材料为干膜(Dry film)。其中，干膜是一种用于半导体芯片封装或印刷电路板制造时所采用的具有粘性的光致抗蚀膜，干膜光刻胶的制造是将无溶剂型光致抗蚀剂涂在涤纶片基上，再覆上聚乙烯薄膜；使用时揭去聚乙烯薄膜，把无溶剂型光致抗蚀剂压于基版上，经曝光显影处理，即可在所述干膜光刻胶内形成图形。
在其他实施例中，所述粘合层的材料还可以为聚酰亚胺(Polyimide)、聚苯并恶唑(PBO)或苯并环丁烯(BCB)。
需要说明的是，所述粘合层200的厚度T1不宜过小，也不宜过大。如果所述粘合层200的厚度T1过小，则容易导致所述粘合层200不足以实现所述器件晶圆100与待集成芯片的粘贴结合；如果所述粘合层200的厚度T1过大，相应会增加后续图形化工艺的难度，且还会造成工艺资源和时间的浪费。为此，本实施例中，根据实际工艺需求，所述粘合层200的厚度T1为5μm至100μm。
参考图6，图形化所述粘合层200，在所述粘合层200内形成多个露出所述第一正面121的第一通孔201。
为了实现所述器件晶圆100与待集成芯片的粘贴结合，后续将所述待集成芯片设置于剩余粘合层200上，所述第一通孔201用于为后续形成与所述待集成芯片电连接的导电柱提供空间位置。相应的，后续将所述待集成芯片设置于剩余粘合层200上后，所述多个第一通孔201与所述待集成芯片一一对应。
本实施例中，所述第一通孔201在所述第一正面121的投影位于所述第一芯片110的一侧，以免与所述待集成芯片电连接的导电柱与所述第一芯片110发生桥接，且为了实现所述封装结构的正常使用功能，根据实际工艺需求，所述第一通孔201与所述第一芯片110一一对应。其中，所述第一通孔201与所述第一芯片110一一对应指的是：所述第一通孔201与所述第一芯片110的数量相同，所述第一通孔201与所述第一芯片110具有预设相对位置关系。
本实施例中，所述第一通孔201的延伸方向为第一方向，与所述第一方向以及所述第一正面121法线方向相垂直的为第二方向(如图6中BB1方向所示)。
具体地，所述粘合层200的材料为干膜，相应的，图形化所述粘合层200的步骤包括：对所述粘合层200进行曝光显影工艺。通过曝光显影工艺图形化所述粘合层200的方式，还有利于提高所述第一通孔201在所述第二方向的开口尺寸的精度；而且，在所述曝光显影工艺后，剩余粘合层200仍具有粘性，从而能够实现所述器件晶圆100与所述待集成芯片的粘贴结合。
本实施例中，为了降低图形化所述粘合层200的工艺难度和工艺成本，图形化所述粘合层200后，剩余粘合层200仅露出所述第一通孔201对应位置的第一正面121。
参考图7，提供多个第二芯片310。
所述第二芯片310用于作为晶圆级系统封装工艺中的待集成芯片，所述多个第二芯片310的功能类型至少为一种。
本实施例中，所述第二芯片310的功能类型为多种，且所述第二芯片310的数量与所述第一芯片110的数量相同。通过将多个不同功能的第二芯片310整合至一个封装结构中，从而实现了晶圆级系统封装方案。
在其他实施例中，例如当所述器件晶圆适于实现晶圆级封装工艺时，所述多个第二芯片的功能类型还可以相同。
所述第二芯片310可以采用集成电路制作技术所制成。具体地，所述第二芯片310可以为存储芯片、通讯芯片、处理器或逻辑芯片。在其他实施例中，所述第二芯片还可以是其他功能芯片。
本实施例中，所述第一通孔201用于为后续形成与所述第二芯片310电连接的导电柱提供空间位置，相应的，所述第二芯片310与所述第一通孔201一一对应。其中，所述第二芯片310与所述第一通孔201一一对应指的是：所述第一通孔201与所述第二芯片310的数量相同，所述第一通孔201露出所述第二芯片310对应位置的部分第一正面121(如图6所示)。
继续参考图7，将所述第二芯片310设置于图形化后的剩余粘合层200上，所述第二芯片310与所述第一通孔201一一对应且覆盖所述第一通孔201的顶部，并使所述器件晶圆100和所述第二芯片310实现键合。
本实施例中，所述粘合层200为粘性材料，因此通过将所述第二芯片310设置于所述剩余粘合层200上，即可实现所述器件晶圆100和所述第二芯片310的粘贴结合，即采用粘贴结合的方式实现所述器件晶圆100和所述第二芯片310的键合。
需要说明的是，所述多个第二芯片310的功能不同，因此所述多个第二芯片310可以通过对不同功能的多个器件晶圆进行切割所获得，所述第二芯片310通常包括形成于半导体衬底上的NMOS器件或PMOS器件等半导体器件，还包括介质层、金属互连结构和焊盘等结构。
本实施例中，所述第二芯片310包括具有器件的第二正面(未标示)以及与所述第二正面相背的第二背面(未标示)。其中，所述第二背面指的是远离所述焊盘一侧的半导体衬底的底部表面。
相应的，将所述第二芯片310设置于所述剩余粘合层200上的步骤中，根据实际工艺需求，可以将所述第二芯片310的第二正面或所述第二背面设置于所述粘合层200上。
还需要说明的是，所述第二芯片310覆盖所述第一通孔201的顶部，也就是说，所述第一通孔201在所述第二芯片310上的投影位于所述第二芯片310内，从而为后续形成与所述第二芯片310电连接的导电柱提供工艺基础，提高所述导电柱的电连接性能。
结合参考图8，本实施例中，使所述器件晶圆100和所述第二芯片310键合后，还包括：在所述第一正面121形成覆盖所述第二芯片310的封装层400。
所述封装层400覆盖所述第二芯片310，从而起到密封和防潮的作用，能够保护所述第二芯片310，从而降低所述第二芯片310发生受损、被污染或被氧化的概率，进而有利于优化封装后所形成封装结构的性能和可靠性。
本实施例中，所述封装层400的材料为环氧树脂(Epoxy)。环氧树脂具有收缩率低、粘结性好、耐腐蚀性好、电性能优异及成本较低等优点，因此广泛用作电子器件和集成电路的封装材料。
在其他实施例中，所述封装层还可以为光刻胶、压合片(Prepreg)或激光活化材料(Laser Activated Material)。
本实施例中，可以通过注塑工艺，使用液体的塑封料或者固体的塑封料，以形成所述封装层400。注塑工艺的填充性能较好，可以使所述塑封料较好地填充于多个第二芯片310之间，从而提高所述封装层400的封装效果。
具体地，所述注塑工艺为热压注塑成型工艺。在其他实施例中，还可以采用其他工艺形成所述封装层。
结合参考图9，形成所述封装层400后，还包括：通过所述第一背面122，对所述器件晶圆100进行减薄处理。
通过对所述器件晶圆100进行减薄处理，以减小所述器件晶圆100的厚度，从而改善所述器件晶圆100的散热效果，且有利于进行后续的封装工艺以及减小封装后所获得封装结构的整体厚度。
本实施例中，所述减薄处理所采用的工艺可以为背部研磨工艺、化学机械抛光(Chemical Mechanical Polishing，CMP)工艺和湿法刻蚀工艺中的一种或多种。
需要说明的是，本实施例中，以先形成所述封装层400后进行所述减薄处理为例进行说明，从而使所述封装层400在所述减薄处理过程中对所述第二芯片310起到固定和支撑作用。
在其他实施例中，还可以在所述减薄处理后形成所述封装层。具体地，将所述第二芯片设置于所述粘合层上后，在所述减薄处理之前，将所述第二芯片背向所述粘合层的表面临时键合于载体晶圆(Carrier Wafer)上，使所述载体晶圆在所述减薄处理过程中对所述多个第二芯片起到临时固定和支撑的作用，降低所述第二芯片发生脱落的概率；而且通过临时键合(Temporary Bonding)的方式，还便于后续将所述第二芯片和所述载体晶圆进行分离。
相应的，在所述减薄处理后，对所述第二芯片和载体晶圆进行解键合(De-bonding)处理，以去除所述载体晶圆；在所述解键合处理后，在所述第一正面形成覆盖所述第二芯片的封装层。
参考图10，形成所述封装层400并完成减薄处理后，刻蚀所述器件晶圆100的第一背面122，在所述器件晶圆100内形成贯穿所述器件晶圆100且与所述第一通孔201相贯通的第二通孔101，所述第二通孔101和所述第一通孔201构成第一导电通孔151。
所述第一导电通孔151用于为后续形成与所述第二芯片310电连接的第一导电柱提供空间位置。
具体地，采用硅穿孔(Through Silicon Via，TSV)刻蚀工艺形成所述第二通孔201，所述刻蚀工艺可以为干法刻蚀和湿法刻蚀中的一种或两种。
本实施例中，刻蚀所述器件晶圆100的步骤包括：采用干法刻蚀工艺，刻蚀部分厚度的所述器件晶圆100；在所述干法刻蚀工艺后，采用湿法刻蚀工艺刻蚀剩余厚度的所述器件晶圆100，以形成贯穿所述器件晶圆100的第二通孔101。
通过先采用干法刻蚀工艺再采用湿法刻蚀工艺的方案，能够在提高刻蚀效率的同时，避免对所述粘合层200和第二芯片310造成刻蚀损耗，且还有利于减小对所述第一通孔201沿所述第二方向(如图6中BB1方向所示)的开口尺寸造成的影响。
需要说明的是，本实施例中，先图形化所述粘合层200以形成所述第一通孔201，再刻蚀所述器件晶圆100以形成所述第二通孔101，即在刻蚀所述器件晶圆100之前，所述粘合层200内已形成有所述第一通孔201，所述第一通孔201沿所述第二方向的开口尺寸通过前述粘合层200的图形化工艺进行设定，从而使所述第一通孔201沿所述第二方向的开口尺寸能够满足工艺需求；因此，与依次刻蚀所述器件晶圆和粘合层，先后在所述器件晶圆内形成第二通孔、在所述粘合层内形成与所述第二通孔相贯通的第一通孔的方案相比，本实施例能够避免出现所述第一通孔201沿所述第二方向的开口尺寸大于所述第二通孔101沿所述第二方向的开口尺寸的问题，从而避免在靠近所述第一通孔201侧壁的位置处(如图10中虚线圈所示)，所述器件晶圆100和第二芯片310之间形成缝隙的问题。
还需要说明的是，由于所述多个第二芯片310的功能不同，因此通过先形成所述第一通孔201再形成所述第二通孔101的方案，可以在优化封装结构的性能和可靠性的同时，实现了晶圆级系统封装方案，使晶圆级系统封装方法与传统系统封装方法相结合，既完成了多种芯片的集成，又实现了在器件晶圆上完成封装制程等制造优势。
本实施例中，所述晶圆级系统封装方法还包括：刻蚀所述器件晶圆100的第一背面122，在所述器件晶圆100内形成露出所述第一芯片110的第二导电通孔152，所述第二导电通孔152用于为后续形成与所述第一芯片110电连接的第二导电柱提供空间位置。
本实施例中，通过不同的刻蚀步骤分别在所述器件晶圆100内形成所述第二通孔101和所述第二导电通孔152。需要说明的是，本实施例以先形成所述第二导电通孔152后形成所述第二通孔101为例进行说明。
具体地，刻蚀所述第一芯片110上方的第一背面122，在所述器件晶圆100内形成露出所述第一芯片110的第二导电通孔152；在所述第二导电通孔152内形成填充层(图未示)，所述填充层还覆盖所述第一背面122；在所述填充层上形成图形层(图未示)，所述图形层内具有露出所述第一通孔201上方填充层的图形开口(图未示)；以所述图形层为掩膜，沿所述图形开口依次刻蚀所述填充层和器件晶圆100，在所述器件晶圆100内形成贯穿所述器件晶圆100且与所述第一通孔201相贯通的第二通孔101；形成所述第二通孔101后，去除所述图形层和填充层。
所述第二导电通孔152的深度较小，通过先形成所述第二导电通孔152后形成所述第二通孔101的方式，能够降低去除所述第二导电通孔152中的填充层的工艺难度。
在其他实施例中，还可以先形成所述第二通孔后形成所述第二导电通孔。
参考图11，在所述第一导电通孔151(如图10所示)内形成与所述第二芯片310电连接的第一导电柱510。
所述第一导电柱510用于实现所述第二芯片310与其他电路之间的电性连接。
需要说明的是，形成所述第一导电柱510的步骤中，还在所述第二导电通孔152(如图10所示)内形成与所述第一芯片110电连接的第二导电柱520。所述第二导电柱520与所述第一芯片110电连接，用于实现所述第一芯片110与其他电路之间的电性连接。而且，通过所述第一导电柱510和第二导电柱520，还能实现所述第二芯片310和第一芯片110之间的电连接。
本实施例中，所述第一导电柱510和第二导电柱520的材料均为铜。在其他实施例中，所述第一导电柱和第二导电柱的材料还可以为铝、钨和钛等导电材料。
具体地，采用电镀工艺在所述第一导电通孔151和第二导电通孔152内填充导电材料层，所述导电材料层还覆盖所述器件晶圆100的第一背面122(如图10所示)；对所述导电材料层进行平坦化工艺，去除所述第一背面122上的导电材料层，保留所述第一导电通孔151内的导电材料作为所述第一导电柱510，保留所述第二导电通孔152内的导电材料作为所述第二导电柱520。
因为在形成所述第一通孔201(如图10所示)之后形成所述第二通孔101(如图10所示)，因此在靠近所述第一通孔201侧壁的位置处(如图10中虚线圈所示)，所述器件晶圆100和第二芯片310之间形成缝隙的概率较低，相应的，所述导电材料在所述第一通孔201内的填充效果和质量较好，从而有利于改善所述第一导电柱510的电性连接性能，进而优化封装结构的性能和可靠性。
结合参考图12，还需要说明的是，形成所述第一导电柱510和第二导电柱520后，还包括：在所述器件晶圆100的第一背面122(如图10所示)形成覆盖所述第一导电柱510的第一焊垫610以及覆盖所述第二导电柱520的第二焊垫620。
所述第二芯片310通过所述第一导电柱510和第一焊垫610与其他电路实现电性连接，所述第一芯片110通过所述第二导电柱520和第二焊垫620与其他电路实现电性连接。
本实施例中，所述第一焊垫610和第二焊垫620的材料均为铝。在其他实施例中，所述第一焊垫和第二焊垫的材料还可以是铜等导电材料。
结合参考图13和图14，形成所述第一焊垫610和第二焊垫620后，在所述第一背面122(如图10所示)形成钝化层700，所述钝化层700还覆盖所述第一焊垫610和第二焊垫620顶部；图形化所述钝化层700，露出部分所述第一焊垫610和部分所述第二焊垫620。
所述钝化层700覆盖所述第一背面122，从而能够防止外界杂质(如钠离子)、离子电荷和水汽等对器件产生影响，进而提高器件的性能和稳定性，提高封装结构的性能和可靠性。
本实施例中，所述钝化层700的材料可以为磷硅玻璃(PSG)、氧化硅、氮化硅、氮氧化硅或聚酰亚胺。
本实施例中，通过刻蚀工艺以图形化所述钝化层700，在所述钝化层700内形成第一开口701(如图14所示)和第二开口702(如图14所示)，所述第一开口701露出部分所述第一焊垫610，所述第二开口702露出部分所述第二焊垫620，从而能够通过所述第一开口701露出的第一焊垫610实现所述第二芯片310与其他电路之间的电性连接，通过所述第二开口702露出的第二焊垫620实现所述第一芯片110与其他电路之间的电性连接，且还可以通过所述露出的第一焊垫610和第二焊垫620实现所述第二芯片310和第一芯片110之间的电连接。
图15至图17是本发明晶圆级系统封装方法另一实施例中各步骤对应的结构示意图。
本实施例与前述实施例的相同之处，在此不再赘述。本实施例与前述实施例的不同之处在于：如图17所示，图形化所述粘合层830后，剩余粘合层830覆盖所述第二芯片910对应位置的第一正面821，所述剩余粘合层830内形成有多个第一通孔801，且所述第一通孔801与所述第二芯片910一一对应。
相应的，当后续形成覆盖所述第二芯片910的封装层900后，所述封装层900覆盖所述第二芯片910露出的所述第一正面821，因此所述封装层900能够与所述第一正面821实现良好的接触，所述封装层900可以更好地实现绝缘、密封及防潮的作用。
本实施例中，为了实现所述器件晶圆800和所述第二芯片910的粘贴结合，图形化所述粘合层830后，剩余粘合层830覆盖所述第二芯片910对应位置的第一正面821，且所述第一通孔801与所述第二芯片910一一对应，所述第一通孔801用于为后续形成与所述第二芯片910电连接的导电柱提供空间位置。
其中，所述第一通孔801与所述第二芯片910一一对应指的是：所述第一通孔801与所述第二芯片910的数量相等，且所述第一通孔801露出所述第二芯片910对应位置的部分第一正面821。
需要说明的是，本实施例中，图形化所述粘合层830后，所述剩余粘合层830至少覆盖部分所述第一芯片810，从而减小相对应的第一芯片810与第二芯片910在平行于所述第一正面821方向的间距，进而有利于提高工艺集成度。在其他实施例中，所述剩余粘合层也可以位于所述第一芯片一侧的第一正面上。
还需要说明的是，所述剩余粘合层830沿平行于所述第一正面821方向的尺寸根据所述第二芯片910沿平行于所述第一正面821方向的尺寸而定，且还可以根据所述第一芯片810沿平行于所述第一正面821方向的尺寸进行调节。
对本实施例所述制造方法的具体描述，可参考前述实施例中的相应描述，本实施例在此不再赘述。
相应的，本发明还提供一种封装结构。
参考图18，示出了本发明封装结构一实施例的结构示意图。
所述封装结构包括：器件晶圆105，所述器件晶圆105包括集成有多个第一芯片205的第一正面111以及与所述第一正面111相背的第一背面112；粘合层305，位于所述器件晶圆105的第一正面111，所述粘合层305内具有多个露出所述第一正面111的第一通孔306；与所述器件晶圆105相键合的多个第二芯片320，所述第二芯片320设置于所述粘合层305上，所述第二芯片320与所述第一通孔306一一对应且覆盖所述第一通孔306的顶部。
所述器件晶圆105为完成器件制作的晶圆，所述器件晶圆105用于作为封装工艺中的待集成晶圆。
本实施例中，所述器件晶圆105适于实现晶圆级系统封装。其中，晶圆级系统封装指的是将多个不同功能的有源元件、无源元件、微机电系统、光学元件等其他元件集成至一个器件晶圆上，再进行切割以获得单个封装体的技术。晶圆级系统封装具有高效率、高密度、体积小、成品率高和电热性能优良等优点，因此能够满足不断提高的封装工艺要求。
在其他实施例中，所述器件晶圆还可适于实现晶圆级封装工艺。其中，晶圆级封装指的是直接在器件晶圆上进行大部分或全部的封装测试程序，再进行切割以获得单个成品芯片的技术。
所述粘合层305的材料为粘性材料，用于实现所述器件晶圆105与所述第二芯片320的粘贴结合，且所述粘合层305内具有多个露出所述第一正面111的第一通孔306，所述第一通孔306用于为形成与所述第二芯片320电连接的导电柱提供空间位置。
本实施例中，所述粘合层305的材料为可光刻的粘性材料，因此所述第一通孔306可以通过对所述粘合层305进行曝光显影的图形化方式形成，相应可以避免额外刻蚀工艺的采用，从而简化了形成所述第一通孔306的工艺步骤，有利于降低工艺成本、提高封装效率；而且，通过曝光显影的方式，还能够避免对所述粘合层305的粘性产生影响。
为此，本实施例中，所述粘合层305的材料为干膜。在其他实施例中，所述粘合层的材料还可以为聚酰亚胺、聚苯并恶唑或苯并环丁烯。
需要说明的是，所述粘合层305的厚度(未标示)不宜过小，也不宜过大。如果所述粘合层305的厚度过小，则容易导致所述粘合层305不足以实现所述器件晶圆105与所述第二芯片320的粘贴结合；如果所述粘合层305的厚度过大，相应会增加形成所述第一通孔306的工艺难度，且还会造成工艺资源和时间的浪费。为此，本实施例中，根据实际工艺需求，所述粘合层305的厚度为5μm至100μm。
本实施例中，所述第一通孔306用于为形成与所述第二芯片320电连接的导电柱提供空间位置，因此所述第一通孔306在所述第一正面111的投影位于所述第一芯片205的一侧，以免与所述第二芯片320电连接的导电柱和所述第一芯片205之间发生桥接，且为了实现所述封装结构的正常使用功能，根据实际工艺需求，所述第一通孔306与所述第一芯片205一一对应。其中，所述第一通孔306与所述第一芯片205一一对应指的是：所述第一通孔306与所述第一芯片205的数量相同，所述第一通孔306与所述第一芯片205具有预设相对位置关系。
本实施例中，为了降低对所述粘合层305进行图形化的工艺难度和工艺成本，所述粘合层305仅露出所述第一通孔306对应位置的第一正面111。
本实施例中，所述第一通孔306的延伸方向为第一方向，与所述第一方向以及所述第一正面111法线方向相垂直的为第二方向(如图18中CC1方向所示)。
所述第二芯片320用于作为晶圆级系统封装工艺中的待集成芯片，所述多个第二芯片320的功能类型至少为一种。
本实施例中，所述多个第二芯片320的功能类型为多种，且所述第二芯片320的数量与所述第一芯片205的数量相同。通过将多个不同功能的第二芯片320整合至一个封装结构中，从而实现了晶圆级系统封装方案。
在其他实施例中，例如当所述器件晶圆适于实现晶圆级封装工艺时，所述多个第二芯片的功能类型还可以相同。
所述第二芯片320可以采用集成电路制作技术所制成。具体地，所述第二芯片320可以为存储芯片、通讯芯片、处理器或逻辑芯片。在其他实施例中，所述第二芯片还可以是其他功能芯片。
本实施例中，所述第一通孔306用于为形成与所述第二芯片320电连接的导电柱提供空间位置，相应的，所述第二芯片320与所述第一通孔306一一对应。其中，所述第二芯片320与所述第一通孔306一一对应指的是：所述第二芯片320与所述第一通孔306的数量相等，且所述第二芯片320覆盖所述第一通孔306的顶部。
需要说明的是，所述多个第二芯片320的功能不同，因此所述多个第二芯片320可以通过对不同功能的多个器件晶圆进行切割所获得，所述第二芯片320通常也包括位于半导体衬底上的NMOS器件或PMOS器件等器件，还包括介质层、金属互连结构和焊盘等结构。
本实施例中，所述第二芯片320包括具有半导体器件的第二正面(未标示)以及与所述第二正面相背的第二背面(未标示)。其中，所述第二背面指的是远离所述焊盘一侧的半导体衬底的底部表面。
相应的，根据实际工艺需求，所述第二芯片320的第二正面或第二背面设置于所述粘合层305上。
还需要说明的是，为了能够实现所述第二芯片320与其他电路之间的电性连接，所述封装结构通常包括位于所述器件晶圆105和第一通孔306内且与所述第二芯片320电连接的导电柱，相应的，所述封装结构的封装制程通常包括刻蚀所述器件晶圆105的第一背面112，在所述器件晶圆105内形成与所述第一通孔306相贯通的第二通孔。
其中，根据本实施例所述封装结构，在所述封装结构的封装制程中，先形成所述第一通孔306，再刻蚀所述器件晶圆105以形成所述第二通孔，因此所述第一通孔306沿所述第二方向的开口尺寸通过所述粘合层305的图形化工艺进行设定，从而使所述第一通孔306沿所述第二方向的开口尺寸满足工艺需求；与依次刻蚀器件晶圆和粘合层，先后在所述器件晶圆内形成第二通孔、再在所述粘合层内形成第一通孔的方案相比，本实施例能够避免出现所述第一通孔306的横向刻蚀严重的问题，以免出现所述第一通孔306沿所述第二方向开口尺寸大于第二通孔沿所述第二方向开口尺寸的问题，从而提高所述导电柱在所述第一通孔306内的形成质量，进而有利于改善所述导电柱对所述第二芯片320的电性连接性能，相应优化了封装结构的性能和可靠性。
所述封装结构可以采用第一实施例所述的封装方法所形成，也可以采用其他封装方法所形成。本实施例中，对所述封装结构的具体描述，可参考第一实施例中的相应描述，本实施例在此不再赘述。
参考图19，示出了本发明封装结构另一实施例的结构示意图。
本实施例与前述实施例的相同之处，在此不再赘述。本实施例与前述实施例的不同之处在于：所述粘合层705覆盖所述第二芯片720对应位置的第一正面411，所述粘合层705内的第一通孔706露出所述第二芯片720对应位置的部分第一正面411。
相应的，当所述封装结构还包括覆盖所述第二芯片720的封装层时，所述封装层还覆盖所述第二芯片720露出的第一正面411，因此所述封装层能够与所述第一正面411实现良好的接触，所述封装层可以更好地实现绝缘、密封及防潮的作用。
本实施例中，为了实现所述器件晶圆405和所述第二芯片720的粘贴结合，所述粘合层705覆盖所述第二芯片720对应位置的第一正面411，且所述第一通孔706与所述第二芯片720一一对应，所述第一通孔706用于为形成与所述第二芯片720电连接的导电柱提供空间位置。
其中，所述第一通孔706与所述第二芯片720一一对应指的是：所述第一通孔706与所述第二芯片720的数量相等，所述第二芯片720覆盖所述第一通孔706的顶部。
需要说明的是，本实施例中，所述粘合层705至少覆盖部分所述第一芯片605，从而减小相对应的第一芯片605与第二芯片720在平行于所述第一正面411方向的间距，进而有利于提高工艺集成度。在其他实施例中，所述粘合层也可以位于所述第一芯片一侧的第一正面上。
还需要说明的是，所述粘合层705沿平行于所述第一正面411方向的尺寸根据所述第二芯片720沿平行于所述第一正面411方向的尺寸而定，且还可以根据所述第一芯片605沿平行于所述第一正面411方向的尺寸进行调节。
所述封装结构可以采用第二实施例所述的封装方法所形成，也可以采用其他封装方法所形成。本实施例中，对所述封装结构的具体描述，可结合参考第一实施例和第二实施例中的相应描述，本实施例在此不再赘述。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (15)

1.一种晶圆级系统封装方法，其特征在于，包括：
提供器件晶圆，所述器件晶圆包括集成有多个第一芯片的第一正面以及与所述第一正面相背的第一背面；
提供多个第二芯片；
在所述器件晶圆的第一正面形成可光刻的粘合层；
图形化所述粘合层，在所述粘合层内形成多个露出所述第一正面的第一通孔；
图形化所述粘合层后，将所述第二芯片设置于剩余粘合层上，所述第二芯片与所述第一通孔一一对应且覆盖所述第一通孔的顶部，并使所述器件晶圆和所述第二芯片键合；
刻蚀所述器件晶圆的第一背面，在所述器件晶圆内形成贯穿所述器件晶圆且与所述第一通孔相贯通的第二通孔，所述第二通孔和所述第一通孔构成第一导电通孔；
在所述第一导电通孔内形成与所述第二芯片电连接的第一导电柱。
2.如权利要求1所述的晶圆级系统封装方法，其特征在于，使所述器件晶圆和所述第二芯片键合后，刻蚀所述器件晶圆的第一背面之前，还包括：在所述第一正面形成覆盖所述第二芯片的封装层；
通过所述第一背面对所述器件晶圆进行减薄处理。
3.如权利要求1所述的晶圆级系统封装方法，其特征在于，使所述器件晶圆和所述第二芯片键合后，在所述第一导电通孔内形成与所述第二芯片电连接的第一导电柱之前，还包括：刻蚀所述器件晶圆的第一背面，在所述器件晶圆内形成露出所述第一芯片的第二导电通孔；
形成所述第一导电柱的步骤中，还在所述第二导电通孔内形成与所述第一芯片电连接的第二导电柱。
4.如权利要求3所述的晶圆级系统封装方法，其特征在于，形成所述第一导电柱和第二导电柱后，还包括：在所述器件晶圆的第一背面形成覆盖所述第一导电柱的第一焊垫以及覆盖所述第二导电柱的第二焊垫；
在所述第一背面形成钝化层，所述钝化层还覆盖所述第一焊垫和第二焊垫顶部；
图形化所述钝化层，露出部分所述第一焊垫和部分所述第二焊垫。
5.如权利要求1所述的晶圆级系统封装方法，其特征在于，所述第二芯片包括形成有半导体器件的第二正面以及与所述第二正面相背的第二背面；
将所述第二正面或第二背面设置于剩余粘合层上。
6.如权利要求1所述的晶圆级系统封装方法，其特征在于，图形化所述粘合层后，剩余粘合层仅露出所述第一通孔对应位置的第一正面；
或者，
剩余粘合层覆盖所述第二芯片对应位置的第一正面。
7.如权利要求1所述的晶圆级系统封装方法，其特征在于，所述粘合层的材料为干膜、聚酰亚胺、聚苯并恶唑或苯并环丁烯。
8.如权利要求1所述的晶圆级系统封装方法，其特征在于，图形化所述粘合层的步骤包括：对所述粘合层进行曝光显影工艺。
9.如权利要求1所述的晶圆级系统封装方法，其特征在于，刻蚀所述器件晶圆的工艺为干法刻蚀和湿法刻蚀中的一种或两种。
10.如权利要求1所述的晶圆级系统封装方法，其特征在于，所述多个第二芯片的功能类型至少为一种。
11.一种封装结构，其特征在于，包括：
器件晶圆，所述器件晶圆包括集成有多个第一芯片的第一正面以及与所述第一正面相背的第一背面；
粘合层，位于所述器件晶圆的第一正面，所述粘合层内具有多个露出所述第一正面的通孔；
与所述器件晶圆相键合的多个第二芯片，所述第二芯片设置于所述粘合层上，所述第二芯片与所述通孔一一对应且覆盖所述通孔的顶部。
12.如权利要求11所述的封装结构，其特征在于，所述第二芯片包括具有半导体器件的第二正面以及与所述第二正面相背的第二背面；
所述第二芯片的第二正面或第二背面设置于所述粘合层上。
13.如权利要求11所述的封装结构，其特征在于，所述粘合层的材料为干膜、聚酰亚胺、聚苯并恶唑或苯并环丁烯。
14.如权利要求11所述的封装结构，其特征在于，所述粘合层仅露出所述通孔对应位置的第一正面；
或者，
所述粘合层覆盖所述第二芯片对应位置的第一正面。
15.如权利要求11所述的封装结构，其特征在于，所述多个第二芯片的功能类型至少为一种。
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