CN102024782B - 三维垂直互联结构及其制作方法 - Google Patents

三维垂直互联结构及其制作方法 Download PDF

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Publication number
CN102024782B
CN102024782B CN201010513047XA CN201010513047A CN102024782B CN 102024782 B CN102024782 B CN 102024782B CN 201010513047X A CN201010513047X A CN 201010513047XA CN 201010513047 A CN201010513047 A CN 201010513047A CN 102024782 B CN102024782 B CN 102024782B
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layer
chip
wafer
hole
interconnect architecture
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CN102024782A (zh
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马盛林
朱韫晖
孙新
金玉丰
缪旻
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Peking University
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Peking University
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Priority to CN201010513047XA priority Critical patent/CN102024782B/zh
Publication of CN102024782A publication Critical patent/CN102024782A/zh
Priority to US13/806,136 priority patent/US8836140B2/en
Priority to PCT/CN2011/001288 priority patent/WO2012048516A1/zh
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Publication of CN102024782B publication Critical patent/CN102024782B/zh
Priority to US14/449,155 priority patent/US9040412B2/en
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    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER

Abstract

本发明公开了一种三维垂直互联结构及其制作方法。结构包括顺次堆叠或面对面堆叠在一起的至少两层芯片，各层所述芯片之间采用粘结材料粘结，各层所述芯片由下至上依次为衬底层和表面介质层，所述芯片的上表面具有横截面为环形的第一凹坑，所述第一凹坑内填充有金属形成第一导电环，所述第一导电环通过重新布局布线层与所述芯片内部的微电子器件连接，与所述第一导电环内径相同且圆心一致的第一通孔贯穿所述堆叠的芯片，所述第一通孔内具有第一微型导电柱。本发明的三维垂直互联结构提高了微电子器件制作中三维互联叠层间电互联和粘合强度，提高了成品率。

Description

三维垂直互联结构及其制作方法
技术领域
本发明涉及半导体及微传感器制造领域，特别是涉及一种三维垂直互联结构及其制作方法。
背景技术
基于硅通孔TSV互联的三维集成技术可以提供高封装密度，使单位体积内容纳更多的微电子器件；较短的信号路径，降低寄生电容，提高了芯片的速度；因此受到了研究者和工业界的重视。然而，基于硅通孔TSV互联的三维叠层芯片在TSV制作、TSV绝缘、TSV电镀填充、超薄晶圆临时键合等方面仍面临挑战，尤其在微焊球、或焊盘制作及其低温键合、叠层芯片热管理、叠层内垂直相邻芯片间信号管理方面尤为突出。叠层垂直相邻芯片间电互联、物理连接需要通过基于微焊球、或焊盘的键合实现。一方面，硅通孔TSV互联的三维集成技术需要尺寸更小的微焊球、或焊盘以实现其技术优势，业界期望典型尺寸为20μm-100μm。另一方面，硅通孔TSV互联的三维集成技术需要通过微焊球、或焊盘实现可靠的电连接、物理连接，小尺寸的微焊球、或焊盘不利于实现这一需求。而且，叠层层数的增多，需要至少1次或1次以上的键合、回流工艺以实现叠层垂直相邻芯片的键合。这种情况下，已经完成键合的微焊球、或焊盘需要再次经历键合、回流工艺，实现多层堆叠；这会对已经键合的微焊球、或焊盘造成伤害，影响其可靠性。
另外，随着叠层层数增多，叠层芯片单位体积内功耗上升。叠层内部芯片释放的热量增多，而且散热渠道有限，容易在叠层内部造成热点，造成叠层芯片性能下降这对叠层的可靠性造成严重威胁。
基于硅通孔TSV互联的三维集成技术要求叠层内芯片有更小的厚度，缩短叠层内垂直相邻芯片间信号路径，提高叠层芯片性能、封装密度。然而位于叠层芯片厚度下降，叠层垂直相邻的芯片表面的信号传输会受到彼此干扰，不利于芯片叠层性能的正常发挥。
发明内容
(一)要解决的技术问题
本发明要解决的技术问题是如何提高微电子器件制作中三维互联叠层间电互联和粘合强度，提高成品率。
(二)技术方案
为解决上述技术问题，提供一种三维垂直互联结构，包括顺次堆叠或面对面堆叠在一起的至少两层芯片，各层所述芯片之间采用粘结材料粘结，各层所述芯片由下至上依次为衬底层和表面介质层，所述芯片的上表面具有横截面为环形的第一凹坑，所述第一凹坑内填充有金属形成第一导电环，所述第一导电环通过重新布局布线层与所述芯片内部的微电子器件连接，与所述第一导电环形状相同且中心一致的第一通孔贯穿所述堆叠的芯片，所述第一通孔内具有第一微型导电柱。
优选地，各层所述芯片的上表面和/或下表面具有导热环，所述芯片的所述上表面和/或下表面具有导热层，所述导热层与所述导热环连接，与所述导热环形状相同且中心一致的第二通孔贯穿所述叠堆的芯片，所述第二通孔内具有微型导热柱。
优选地，所述芯片的上表面和/或下表面具有横截面为环形的第二凹坑，所述第二凹坑内填充有金属形成第二导电环，所述上表面和/或下表面涂覆有接地导电层，所述第二导电环与所述接地导电层连接，与所述第二导电环形状相同且中心一致的第三通孔贯穿所述叠堆的芯片，所述第三通孔内具有第二微型导电柱。
优选地，各层所述芯片之间的粘结材料内具有微流道，所述微流道含有垂直贯穿所述叠堆的芯片的第四通孔。
优选地，所述粘结材料为有机物或金属焊料，所述有机物粘结材料包括聚酰亚胺、环氧树脂、紫外线胶带、双苯并环丁烯、非导电粘合剂、硅橡胶或聚对二甲苯，所述金属焊料包括铜、钨、金、银、锡、铟、镍、钯、铜锡合金、锡银铜合金、锡银合金、金锡合金、铟金合金、铅锡合金、镍钯合金、镍金合金或镍钯金合金。
优选地，所述第一凹坑的深度为1-30微米。
优选地，所述导热层为金属导热材料，所述金属导热材料包括金、铜或铝。
优选地，所述接地导电层为金属材料或导电浆料，所述金属材料为金、铜或铝。
优选地，所述第一通孔、第二通孔和/或第三通孔为圆柱形、棱柱形、圆锥形或棱锥形。
本发明还提供了一种三维垂直互联结构的制作方法，包括步骤：
S1，在经过减薄或未经减薄的单层硅晶圆或芯片的有源区面进行光刻，制作环状图形，然后依次刻蚀单层晶圆或芯片的表面介质层和衬底层，制作出扳指状的第一凹坑；
S2，沉积阻挡层、电镀种子层覆盖第一凹坑内侧壁，并电镀铜以填充第一凹坑，形成第一导电环；
S3，制作连接第一导电环与晶圆或芯片内部微电子器件的重新布局布线层，所述重新布局布线层包括介质层与金属互联层；
S4，依次刻蚀重新布局布线层的介质层以及晶圆或芯片的表面介质层，在第一导电环内部制作第一通孔，所述第一通孔的横截面形状、中心与第一导电环内环相同；
S5，将完成了步骤S1-S4的单层晶圆或芯片依次堆叠并对准，相邻的晶圆或芯片间使用有机物或者金属焊料粘结；
S6，在多层堆叠的晶圆或芯片层的一面，沉积电镀种子层并电镀，密闭第一通孔，把电镀金属层作为种子层自底向上填充贯穿多层堆叠的通孔，制作第一微型导电柱并去除电镀种子层，完成三维垂直互联结构的制作。
优选地，在步骤S2中沉积阻挡层、电镀种子层之前，沉积绝缘层覆盖第一凹坑的内侧壁，所述绝缘层选择二氧化硅或聚酰亚胺，利用溅射或等离子增强化学气相沉积法沉积绝缘层。
优选地，在步骤S2之后，重复步骤S1-S2在单层晶圆或芯片有源区面和/或其相对的一面制作相同结构的第二导电环和/或导热环。
优选地，在步骤S3中，在单层晶圆或芯片有源区面和/或其相对的一面制作接地导电层和/或导热层，接地导电层与第二导电环连接，导热层与导热环连接。
优选地，在步骤S5中，图形化粘接材料，以形成用于散热的微流道。
本发明还提供了一种三维垂直互联结构的制作方法，包括步骤：
S1，在单层硅晶圆或芯片的有源区面进行光刻，制作圆环图形，然后依次刻蚀单层晶圆或芯片的表面介质层和衬底层，制作出扳指状的第一凹坑；
S2，沉积阻挡层、电镀种子层覆盖第一凹坑内侧壁，并电镀铜以填充第一凹坑，形成第一导电环；
S3，制作连接第一导电环与晶圆或芯片内部微电子器件的重新布局布线层，所述重新布局布线层包括介质层与金属互联层；
S4，依次刻蚀重新布局布线层的介质层以及晶圆或芯片的表面介质层，在第一导电环内部制作盲孔，所述盲孔的横截面形状、中心与第一导电环内环相同；
S5，将完成了步骤S1-S4的两层晶圆或芯片面对面堆叠并对准，晶圆或芯片间使用有机物或者金属焊料粘结；
S6，在堆叠的晶圆或芯片层的两面减薄直至暴露出盲孔实现通孔；
S7，将完成了步骤S1-S4的单层晶圆或芯片与完成了步骤S1-S6的晶圆或芯片叠层、粘结，并重复步骤S6以实现三层及三层以上的晶圆或芯片的堆叠；
S8，在多层堆叠的晶圆或芯片的一面沉积电镀种子层并电镀，密闭通孔，把电镀金属层作为种子层自底向上填充贯穿多层堆叠的通孔，制作微型导电柱并去除电镀种子层，完成三维垂直互联结构的制作。
优选地，在步骤S3中，在单层晶圆或芯片有源区面和/或其相对的一面制作第二导电环和/或导热环。
优选地，在步骤S3中，在单层晶圆或芯片有源区面和/或其相对的一面制作接地导电层和/或导热层，接地导电层与第二导电环连接，导热层与导热环连接。
优选地，在步骤S5中，图形化粘接材料，以形成用于散热的微流道。
优选地，在步骤S4之后，沉积绝缘层覆盖盲孔侧壁和底部，并在盲孔的开口进行刻蚀，去除导电环内部的绝缘层，暴露第一导电环的内侧壁
(三)有益效果
与传统基于TSV三维集成技术相比，本发明采用不同结构实现了堆叠晶圆或芯片的粘接固定以及晶圆或芯片间的电互联。采用有机材料或焊料实现单层晶圆或芯片间的粘接固定，不提供单层晶圆或芯片间的电互联，因而可以采用灵活的晶圆键合技术、焊接技术、粘接技术。环绕在贯穿于晶圆或芯片叠层内微型导电柱外的导电环，实现了晶圆间、以及晶圆或芯片内微电子器件之间的电互联，工艺简单，可靠性高。叠层内垂直相邻的晶圆或芯片间的微流道设计、导热层设计，可以有效缓解叠层内芯片热积累。叠层内垂直相邻的晶圆或芯片间的接地金属层设计，可以有效缓解叠层内芯片间信号串扰。在完成多层晶圆、芯片间粘接后，一次制作贯穿于叠层的TSV通孔内的微型导电柱，实现了三维垂直互联结构单层晶圆或芯片间的电互联。降低了填充工艺难度，减少了工艺时间，提高了电镀成品率。
附图说明
图1(a)和图1(b)分别是依照本发明实施例的三维垂直互联方法在单层晶圆或芯片有源区面制作扳指状凹坑的俯视图和横截面示意图。
图2是依照本发明实施例的三维垂直互联方法在单层晶圆或芯片有源区面制作导电环的横截面示意图。
图3是依照本发明实施例的三维垂直互联方法在单层晶圆或芯片有源区面制作重新布局布线层的横截面示意图。
图4是依照本发明实施例的三维垂直互联方法在单层晶圆或芯片有源区面导电环内部制作TSV通孔，侧壁绝缘后的横截面示意图。
图5是依照本发明实施例的三维垂直互联方法在两层完成互联结构制作的晶圆对准、粘接后的横截面示意图。
图6是依照本发明实施例的三维垂直互联方法在两层完成互联结构制作的晶圆对准、粘接、电镀填充后实现垂直互联的横截面示意图。
图7是依照本发明实施例的三维垂直互联方法在两层完成互联结构制作的晶圆正面对正面(正面是晶圆有源区所在面)对准、粘接后的横截面示意图。
图8是依照本发明实施例的三维垂直互联方法在两层完成互联结构制作的晶圆正面对正面(正面是晶圆有源区所在面)对准、粘接、两面减薄后，实现两层叠层TSV穿通的横截面示意图。
图9是依照本发明实施例的三维垂直互联方法在另一层晶圆堆叠在两层完成互联结构制作的晶圆面对面粘合对之上且背面减薄后的示意图。
图10是依照本发明实施例的三维垂直互联方法两层完成互联结构制作的晶圆对准、粘接、电镀填充，实现垂直互联的横截面示意图。
具体实施方式
下面结合附图和实施例，对本发明的具体实施方式作进一步详细描述。以下实施例用于说明本发明，但不用来限制本发明的范围。
实施例一
本发明的一个实施例提供了一种三维垂直互联结构，参见图1-图7，包括至少两层晶圆或芯片，顺次堆叠或面对面堆叠在一起，各层晶圆或芯片之间采用粘结材料040粘结，各层晶圆或芯片由下至上依次为衬底层010和表面介质层011，晶圆或芯片的上表面具有横截面为圆环形的扳指状凹坑020，凹坑020内填充有金属形成导电圆环022，导电圆环022通过重新布局布线层012与晶圆或芯片内部的微电子器件连接，与导电圆环022内径相同且圆心一致的TSV通孔030贯穿堆叠的晶圆或芯片，通孔030内具有微型导电柱。
优选地，各层晶圆或芯片之间的粘结材料040内具有微流道，微流道含有垂直贯穿所述叠堆的晶圆或芯片的通孔。
实施例二
本发明的另一实施例提供了一种三维垂直互联结构，包括至少两层晶圆或芯片，顺次堆叠或面对面堆叠在一起，各层晶圆或芯片之间采用粘结材料040粘结，各层晶圆或芯片由下至上依次为衬底层010和表面介质层011，晶圆或芯片的上表面具有横截面为圆环形的扳指状凹坑020，凹坑020内填充有金属形成导电圆环022，导电圆环022通过重新布局布线层012与晶圆或芯片内部的微电子器件连接，与导电圆环022内径相同且圆心一致的TSV通孔030贯穿堆叠的晶圆或芯片，通孔030内具有微型导电柱。
各层晶圆或芯片上表面和/或下表面具有导热圆环，晶圆或芯片的上表面和/或下表面具有导热层，导热层与导热圆环连接，与导热圆环内径相同且圆心一致的通孔贯穿叠堆的晶圆或芯片，通孔内具有微型导热柱。
优选地，各层晶圆或芯片之间的粘结材料040内具有微流道，微流道含有垂直贯穿所述叠堆的晶圆或芯片的通孔。
实施例三
本发明的另一实施例提供了一种三维垂直互联结构，包括至少两层晶圆或芯片，顺次堆叠或面对面堆叠在一起，各层晶圆或芯片之间采用粘结材料040粘结，各层晶圆或芯片由下至上依次为衬底层010和表面介质层011，晶圆或芯片的上表面具有横截面为圆环形的扳指状凹坑020，凹坑020内填充有金属形成导电圆环022，导电圆环022通过重新布局布线层012与晶圆或芯片内部的微电子器件连接，与导电圆环022内径相同且圆心一致的TSV通孔030贯穿堆叠的晶圆或芯片，通孔030内具有微型导电柱。
晶圆或芯片的上表面和/或下表面具有横截面为圆环形的凹坑020，凹坑020内填充有金属形成导电圆环022，下表面涂覆有接地导电层，导电圆环与接地导电层连接，与导电圆环内径相同且圆心一致的通孔030贯穿所述叠堆的晶圆或芯片，通孔030内具有微型导电柱033。
优选地，各层晶圆或芯片之间的粘结材料040内具有微流道，微流道含有垂直贯穿所述叠堆的晶圆或芯片的通孔。
实施例四
本发明的另一实施例提供了一种三维垂直互联结构，包括至少两层晶圆或芯片，顺次堆叠或面对面堆叠在一起，各层晶圆或芯片之间采用粘结材料040粘结，各层晶圆或芯片由下至上依次为衬底层010和表面介质层011，晶圆或芯片的上表面具有横截面为圆环形的扳指状凹坑020，凹坑020内填充有金属形成导电圆环022，导电圆环022通过重新布局布线层012与晶圆或芯片内部的微电子器件连接，与导电圆环022内径相同且圆心一致的TSV通孔030贯穿堆叠的晶圆或芯片，通孔030内具有微型导电柱。
各层晶圆或芯片上表面和/或下表面具有导热圆环，晶圆或芯片的上表面和/或下表面具有导热层，导热层与导热圆环连接，与导热圆环内径相同且圆心一致的通孔贯穿叠堆的晶圆或芯片，通孔内具有微型导热柱。
晶圆或芯片的上表面和/或下表面具有横截面为圆环形的凹坑020，凹坑020内填充有金属形成导电圆环022，下表面涂覆有接地导电层，导电圆环与接地导电层连接，与导电圆环内径相同且圆心一致的通孔030贯穿所述叠堆的晶圆或芯片，通孔030内具有微型导电柱033。
各层晶圆或芯片之间的粘结材料040内具有微流道，微流道含有垂直贯穿所述叠堆的晶圆或芯片的通孔。
上述各实施例中的粘结材料均可以选择有机物或金属焊料，有机物包括聚酰亚胺、环氧树脂、紫外线胶带、双苯并环丁烯、非导电粘合剂、硅橡胶或聚对二甲苯，金属焊料包括铜、钨、金、银、锡、铟、镍、钯、铜锡合金、锡银铜合金、锡银合金、金锡合金、铟金合金、铅锡合金、镍钯合金、镍金合金或镍钯金合金。
上述三维垂直互联结构的制作方法可以通过两个实施例来实现：
实施例五
三维垂直互联结构的制作方法包括下列步骤：
步骤A.在完成了微电子器件制作的单层硅晶圆或芯片的有源区面进行光刻，制作圆环图形。然后依次刻蚀单层晶圆或芯片表面介质层011和衬底层010，制作出扳指状凹坑020，图1(a)和图1(b)分别是扳指状凹坑020的俯视图和沿径向截面图。单层晶圆表面介质层011可以采用活性离子蚀刻(reactive ion etching，RIE)，也可以采用其他湿法或干法刻蚀技术。晶圆或芯片衬底层010的刻蚀可以采用深度反应离子刻蚀(Deep reactive etching，DRIE)，也可以采用其他湿法或干法刻蚀技术。凹坑020的深度最好为1μm-30μm。单层晶圆或芯片可以是背面完成减薄之后的超薄单层晶圆或芯片。
步骤B.沉积阻挡层TiW、电镀种子层金(Au)或铜(Cu)覆盖扳指状凹坑020内侧壁；光刻，晶圆有源区面除了凹坑区域及电极接触区全部由光刻胶覆盖；电镀金属铜，填充扳指状凹坑020。填充于扳指状凹坑020内部的金属形成扳指状的导电圆环022，如图2所示。去除光刻胶，和扳指状凹坑020以外的阻挡层和电镀种子层，可以根据需要对电镀表面进行平坦化。在沉积阻挡层、电镀种子层前，可以沉积绝缘层021(如二氧化硅、聚酰亚胺等)覆盖凹坑020的内侧壁。阻挡层、种子层沉积可以采用半导体行业常规工艺如溅射、蒸发、化学气相沉积(CVD)等方法。绝缘层材料的沉积可以采用半导体行业常规工艺如溅射、等离子增强化学气相沉积(PECVD)等。
同样，可以重复步骤A、步骤B在单层晶圆或芯片背面(有源区相对一面)制作相同的结构扳指状凹坑020、绝缘层021和导电圆环022。
步骤C.制作连接导电环与晶圆或芯片内部微电子器件的重新布局布线层012。重新布局布线层012的互连线013可以采用铜、铝等金属，也可以采用其他金属。重新布局布线层012的介质层可以为聚酰亚胺、BCB、环氧树脂等材料，也可以为其他介质材料。此步骤至少包括一层重新布局布线层012，但不限于一层。
此步骤还可以含有，在单层晶圆或芯片正面(有源区面)或背面制作接地导电层，或导热层。接地导电层与导电圆环连接，导热层与导热圆环连接。
接地导电层可以使用金、铜、铝等金属，也可使用其他导电浆料。
导热层可以是金、铜、铝等导热材料，也可以使用其他散热材料。
步骤D.光刻，依次刻蚀重新布局布线层012的介质层、表面介质层011，在导电圆环022内部制作TSV通孔030，TSV通孔030横截面半径、圆心与导电环内环相同。TSV通孔030的实现可以由深度反应离子刻蚀DRIE刻蚀技术实现，也可以采用其他如激光打孔等技术实现。TSV通孔030如果使用DRIE实现，可以采用单面刻蚀，也可以采用双面刻蚀实现。表面介质层011、重新布局布线层012的介质层的刻蚀可以采用RIE也可采用其他湿法或干法刻蚀技术。如单层晶圆或芯片厚度超过300μm，优选采用双面刻蚀，可以提高效率。可以沉积绝缘层031，如二氧化硅等半导体行业常规绝缘层材料，覆盖TSV通孔030侧壁和底部。在晶圆或芯片TSV通孔030开口进行刻蚀，去除导电圆环022内部的绝缘层031，暴露导电圆环022的侧壁。
步骤E.把多层完成步骤A、B、C、D的单层晶圆或芯片对准、堆叠，如图5所示。垂直相邻的晶圆或芯片间使用有机膜040，如聚酰亚胺、BCB、环氧树脂等有机物粘接，也可使用常规焊料如Al-Ge，Au-Sn，Cu-Sn等焊料焊接。
此步骤中可以含有图形化粘接材料040的工序，晶圆键合，形成用于散热的微流道。
此步骤中粘接材料040可以选择有机物或金属焊料，有机物包括聚酰亚胺、环氧树脂、紫外线胶带、双苯并环丁烯、非导电粘合剂、硅橡胶或聚对二甲苯，也可以选择金属焊料包括铜、钨、金、银、锡、铟、镍、钯、铜锡合金、锡银铜合金、锡银合金、金锡合金、铟金合金、铅锡合金、镍钯合金、镍金合金或镍钯金合金。但不限于此，也可使用其他半导体加工行业常用焊料。
步骤F.在多层堆叠的晶圆或芯片层的一面，沉积电镀种子层，电镀，密闭TSV通孔030。把电镀金属层作为种子层，自底向上填充贯穿多层堆叠的TSV通孔030，制作微型导电柱033，电镀焊球或焊盘050。去除电镀种子层，完成三维垂直互联结构的制作，如图6。
此步骤中叠层TSV通孔030也可以采用辅助晶圆片，完成填充。具体来讲，在辅助晶圆片一面制作种子层，临时夹持辅助晶圆和叠层。利用辅助晶圆片种子层，自底向上，填充叠层TSV通孔，形成贯穿叠层晶圆或芯片的微型导电柱。
实施例六
三维垂直互联结构的制作方法包括下列步骤：
步骤A.在完成微电子器件制作的单层硅晶圆、或芯片的有源区面进行光刻，制作圆环图形。然后依次刻蚀单层晶圆或芯片表面介质层011和衬底层010制作出扳指状凹坑020，图1(a)和图1(b)分别是扳指状凹坑020的俯视图和横截面图。介质层011可以采用RIE也可以采用其他湿法或干法刻蚀技术。衬底层010的刻蚀可以采用DRIE，也可以采用其他湿法或干法刻蚀技术。凹坑深度建议为1μm-30μm。单层晶圆或芯片可以是背面完成减薄之后的超薄单层晶圆或芯片。
步骤B.沉积阻挡层TiW、电镀种子层金Au或铜Cu覆盖扳指状凹坑020侧壁和底部。光刻，晶圆有源区面除了凹坑区域及电极接触区全部由光刻胶覆盖。电镀金属，如铜，填充扳指状凹坑020。填充于扳指状凹坑020内部的金属，形成扳指状的导电圆环022，如图2所示。去除光刻胶、凹坑以外的阻挡层、电镀种子层，可以根据需要对电镀表面进行平坦化。在沉积阻挡层、电镀种子层前，可以沉积绝缘层021，如二氧化硅、聚酰亚胺等覆盖凹坑020内侧壁。阻挡层、种子层沉积可以采用半导体行业常规工艺如溅射、蒸发、化学气相沉积(CVD)等方法。绝缘层材料的沉积可以采用半导体行业常规工艺如溅射、等离子增强化学气相沉积(PECVD)等。
步骤C.制作连接导电圆环022与晶圆或芯片内部微电子器件的重新布局布线层012。重新布局布线层012的互连线013可以采用由铜、铝等金属，也可以采用其他导电材料。重新布局布线层012的介质层可以由聚酰亚胺、BCB、环氧树脂等材料，也可以由其他介质材料。此步骤至少包括一层重新布局布线层012，不限于1层。如图3所示。
步骤D.光刻，依次刻蚀重新布局布线层的介质层012、晶圆或芯片表面介质层011，在导电圆环022内部制作TSV盲孔030，TSV盲孔030横截面半径、圆心与导电圆环内环相同。TSV盲孔030可以由刻蚀、激光打孔等打孔技术实现。如果采用刻蚀技术实现，表面介质层011、重新布局布线层012的介质层可以采用RIE亦可采用其他湿法或干法刻蚀技术。晶圆或芯片衬底010可以采用DRIE刻蚀技术。可以沉积绝缘层材料如二氧化硅，覆盖TSV盲孔030的侧壁和底部绝缘TSV盲孔030侧壁和底部。对TSV盲孔030开口进行刻蚀，去除导电圆环内部的绝缘层，暴露金属圆环022的内侧壁。
步骤E.如图7，把两层完成步骤A-D的单层晶圆或芯片的有源区面对面对准，晶圆或芯片之间由粘接材料粘接。此步骤中粘接材料040可以选择有机物或金属焊料，有机物包括聚酰亚胺、环氧树脂、紫外线胶带、双苯并环丁烯、非导电粘合剂、硅橡胶或聚对二甲苯；也可以选择金属焊料包括铜、钨、金、银、锡、铟、镍、钯、铜锡合金、锡银铜合金、锡银合金、金锡合金、铟金合金、铅锡合金、镍钯合金、镍金合金或镍钯金合金。但不限于此，也可使用其他半导体加工行业常用焊料。
此步骤中可以含有图形化的粘接材料040的工序，制作用于散热的微流道。
步骤F.把完成堆叠的2层晶圆或芯片的两面减薄，直至暴露出TSV盲孔030，实现叠层TSV通孔，如图8。减薄可以采用化学机械抛光(CMP)或者其他湿法干法减薄技术。
步骤G.把完成步骤A-D的单层晶圆与完成步骤A-F的叠层，重复步骤E和F，可以实现三层及三层以上晶圆或芯片的堆叠。如图9所示。
步骤H.在多层堆叠的晶圆或芯片层的一面，沉积电镀种子层，电镀，密闭TSV通孔。把电镀金属层作为种子层，自底向上填充贯穿多层堆叠的TSV通孔，制作微金属柱033，电镀焊球或焊盘050。去除电镀种子层，完成三维垂直互联结构的制作，如图10。
此步骤中叠层TSV通孔亦可以采用辅助晶圆片，完成填充。具体来讲，在辅助晶圆片一面制作种子层，临时夹持辅助晶圆和叠层。利用辅助晶圆片种子层，自底向上，填充叠层TSV通孔，形成贯穿叠层晶圆或芯片的微导电圆柱。
由以上实施例可以看出，与传统基于TSV三维集成技术相比，本发明采用不同结构实现了堆叠晶圆或芯片的粘接固定以及晶圆或芯片间的电互联。采用有机材料或焊料实现单层晶圆或芯片间的粘接固定，不提供单层晶圆或芯片间的电互联，因而可以采用灵活的晶圆键合技术、焊接技术、粘接技术。环绕在贯穿于晶圆或芯片叠层内微型导电柱外的导电环，实现了晶圆间、以及晶圆或芯片内微电子器件之间的电互联，工艺简单，可靠性高。叠层内垂直相邻的晶圆或芯片间的微流道设计、导热层设计，可以有效缓解叠层内芯片热积累。叠层内垂直相邻的晶圆或芯片间的接地金属层设计，可以有效缓解叠层内芯片间信号串扰。在完成多层晶圆、芯片间粘接后，一次制作贯穿于叠层的TSV通孔内的微型导电柱，实现了三维垂直互联结构单层晶圆或芯片间的电互联。降低了填充工艺难度，减少了工艺时间，提高了电镀成品率。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明技术原理的前提下，还可以做出若干改进和变型，这些改进和变型也应视为本发明的保护范围。

Claims (19)

1.一种三维垂直互联结构，其特征在于，包括顺次堆叠或面对面堆叠在一起的至少两层芯片，各层所述芯片之间采用粘结材料粘结，各层所述芯片由下至上依次为衬底层和表面介质层，所述芯片的上表面具有横截面为环形的第一凹坑，所述第一凹坑内填充有金属形成第一导电环，所述第一导电环通过重新布局布线层与所述芯片内部的微电子器件连接，与所述第一导电环形状相同且中心一致的第一通孔贯穿所述堆叠的芯片，所述第一通孔内具有第一微型导电柱。
2.如权利要求1所述的三维垂直互联结构，其特征在于，各层所述芯片的上表面和/或下表面具有导热环，所述芯片的所述上表面和/或下表面具有导热层，所述导热层与所述导热环连接，与所述导热环形状相同且中心一致的第二通孔贯穿所述叠堆的芯片，所述第二通孔内具有微型导热柱。
3.如权利要求2所述的三维垂直互联结构，其特征在于，所述芯片的上表面和/或下表面具有横截面为环形的第二凹坑，所述第二凹坑内填充有金属形成第二导电环，所述上表面和/或下表面涂覆有接地导电层，所述第二导电环与所述接地导电层连接，与所述第二导电环形状相同且中心一致的第三通孔贯穿所述叠堆的芯片，所述第三通孔内具有第二微型导电柱。
4.如权利要求1-3任一项所述的三维垂直互联结构，其特征在于，各层所述芯片之间的粘结材料内具有微流道，所述微流道含有垂直贯穿所述叠堆的芯片的第四通孔。
5.如权利要求1所述的三维垂直互联结构，其特征在于，所述粘结材料为有机物或金属焊料，所述有机物粘结材料包括聚酰亚胺、环氧树脂、紫外线胶带、双苯并环丁烯、非导电粘合剂、硅橡胶或聚对二甲苯，所述金属焊料包括铜、钨、金、银、锡、铟、镍、钯、铜锡合金、锡银铜合金、锡银合金、金锡合金、铟金合金、铅锡合金、镍钯合金、镍金合金或镍钯金合金。
6.如权利要求1所述的三维垂直互联结构，其特征在于，所述第一凹坑的深度为1-30微米。
7.如权利要求2所述的三维垂直互联结构，其特征在于，所述导热层为金属导热材料，所述金属导热材料包括金、铜或铝。
8.如权利要求3所述的三维垂直互联结构，其特征在于，所述接地导电层为金属材料或导电浆料，所述金属材料为金、铜或铝。
9.如权利要求3所述的三维垂直互联结构，其特征在于，所述第一通孔、第二通孔和/或第三通孔为圆柱形、棱柱形、圆锥形或棱锥形。
10.一种三维垂直互联结构的制作方法，其特征在于，包括步骤：
S1，在经过减薄或未经减薄的单层硅晶圆或芯片的有源区面进行光刻，制作环状图形，然后依次刻蚀单层晶圆或芯片的表面介质层和衬底层，制作出扳指状的第一凹坑；
S2，沉积阻挡层、电镀种子层覆盖第一凹坑内侧壁，并电镀铜以填充第一凹坑，形成第一导电环；
S3，制作连接第一导电环与晶圆或芯片内部微电子器件的重新布局布线层，所述重新布局布线层包括介质层与金属互联层；
S4，依次刻蚀重新布局布线层的介质层以及晶圆或芯片的表面介质层，在第一导电环内部制作第一通孔，所述第一通孔的横截面形状、中心与第一导电环内环相同；
S5，将完成了步骤S1-S4的单层晶圆或芯片依次堆叠并对准，相邻的晶圆或芯片间使用有机物或者金属焊料粘结；
S6，在多层堆叠的晶圆或芯片层的一面，沉积电镀种子层并电镀，密闭第一通孔，把电镀金属层作为种子层自底向上填充贯穿多层堆叠的通孔，制作第一微型导电柱并去除电镀种子层，完成三维垂直互联结构的制作。
11.如权利要求10所述的三维垂直互联结构的制作方法，其特征在于，
在步骤S2中沉积阻挡层、电镀种子层之前，沉积绝缘层覆盖第一凹坑的内侧壁，所述绝缘层选择二氧化硅或聚酰亚胺，利用溅射或等离子增强化学气相沉积法沉积绝缘层。
12.如权利要求11所述的三维垂直互联结构的制作方法，其特征在于，
在步骤S2之后，重复步骤S1-S2在单层晶圆或芯片有源区面和/或其相对的一面制作相同结构的第二导电环和/或导热环。
13.如权利要求12所述的三维垂直互联结构的制作方法，其特征在于，
在步骤S3中，在单层晶圆或芯片有源区面和/或其相对的一面制作接地导电层和/或导热层，接地导电层与第二导电环连接，导热层与导热环连接。
14.如权利要求10所述的三维垂直互联结构的制作方法，其特征在于，
在步骤S5中，图形化粘接材料，以形成用于散热的微流道。
15.一种三维垂直互联结构的制作方法，其特征在于，包括步骤：
S1，在单层硅晶圆或芯片的有源区面进行光刻，制作圆环图形，然后依次刻蚀单层晶圆或芯片的表面介质层和衬底层，制作出扳指状的第一凹坑；
S2，沉积阻挡层、电镀种子层覆盖第一凹坑内侧壁，并电镀铜以填充第一凹坑，形成第一导电环；
S3，制作连接第一导电环与晶圆或芯片内部微电子器件的重新布局布线层，所述重新布局布线层包括介质层与金属互联层；
S4，依次刻蚀重新布局布线层的介质层以及晶圆或芯片的表面介质层，在第一导电环内部制作盲孔，所述盲孔的横截面形状、中心与第一导电环内环相同；
S5，将完成了步骤S1-S4的两层晶圆或芯片面对面堆叠并对准，晶圆或芯片间使用有机物或者金属焊料粘结；
S6，在堆叠的晶圆或芯片层的两面减薄直至暴露出盲孔实现通孔；
S7，将完成了步骤S1-S4的单层晶圆或芯片与完成了步骤S1-S6的晶圆或芯片叠层、粘结，并重复步骤S6以实现三层及三层以上的晶圆或芯片的堆叠；
S8，在多层堆叠的晶圆或芯片的一面沉积电镀种子层并电镀，密闭通孔，把电镀金属层作为种子层自底向上填充贯穿多层堆叠的通孔，制作微型导电柱并去除电镀种子层，完成三维垂直互联结构的制作。
16.如权利要求15所述的三维垂直互联结构的制作方法，其特征在于，在步骤S3中，在单层晶圆或芯片有源区面和/或其相对的一面制作第二导电环和/或导热环。
17.如权利要求16所述的三维垂直互联结构的制作方法，其特征在于，在步骤S3中，在单层晶圆或芯片有源区面和/或其相对的一面制作接地导电层和/或导热层，接地导电层与第二导电环连接，导热层与导热环连接。
18.如权利要求15所述的三维垂直互联结构的制作方法，其特征在于，在步骤S5中，图形化粘接材料，以形成用于散热的微流道。
19.如权利要求15-18任一项所述的三维垂直互联结构的制作方法，其特征在于，在步骤S4之后，沉积绝缘层覆盖盲孔侧壁和底部，并在盲孔的开口进行刻蚀，去除导电环内部的绝缘层，暴露第一导电环的内侧壁。
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