CN112514059A - 堆叠微电子部件的层间连接 - Google Patents

堆叠微电子部件的层间连接 Download PDF

Info

Publication number
CN112514059A
CN112514059A CN201980049050.XA CN201980049050A CN112514059A CN 112514059 A CN112514059 A CN 112514059A CN 201980049050 A CN201980049050 A CN 201980049050A CN 112514059 A CN112514059 A CN 112514059A
Authority
CN
China
Prior art keywords
microelectronic
forming
substrates
stack
conductive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201980049050.XA
Other languages
English (en)
Other versions
CN112514059B (zh
Inventor
G·高
B·哈巴
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Evanss Adhesive Technologies
Original Assignee
Evanss Adhesive Technologies
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Evanss Adhesive Technologies filed Critical Evanss Adhesive Technologies
Publication of CN112514059A publication Critical patent/CN112514059A/zh
Application granted granted Critical
Publication of CN112514059B publication Critical patent/CN112514059B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/89—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using at least one connector not provided for in any of the groups H01L24/81 - H01L24/86
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/5442—Marks applied to semiconductor devices or parts comprising non digital, non alphanumeric information, e.g. symbols
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361—Physical or chemical etching
    • H01L2224/03616—Chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/08146—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bonding area connecting to a via connection in the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/2405—Shape
    • H01L2224/24051—Conformal with the semiconductor or solid-state device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8012—Aligning
    • H01L2224/80121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/821—Forming a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/9202—Forming additional connectors after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H01L2225/06544—Design considerations for via connections, e.g. geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06593—Mounting aids permanently on device; arrangements for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

可以采用包括过程步骤的代表性技术和设备来形成多管芯堆叠或多晶片堆叠的公共互连。堆叠的每个器件包括设置在器件的表面上的预先确定的相对位置处的导电焊盘。器件被堆叠以使导电焊盘垂直对准。形成穿硅过孔，该穿硅过孔电耦合堆叠的每个器件的导电焊盘。

Description

堆叠微电子部件的层间连接
优先权要求和相关申请的交叉引用
本申请要求根据35U.S.C.§119(e)(1)要求于2019年6月12日提交的美国非临时申请号16/438,714和于2018年6月12日提交的美国临时申请号62/683,857的权益，其全部内容通过引用并入本文。
技术领域
以下描述涉及集成电路(“IC”)。更具体地，以下描述涉及制造IC管芯和晶片。
背景技术
微电子元件通常包括由半导体材料(诸如硅或砷化镓之类)形成的薄平板(通常被称为半导体晶片)。晶片可以被形成为包括位于晶片的表面上和/或部分嵌入晶片内的多个集成芯片或管芯。与晶片分开的管芯通常作为单独、预先封装单元提供。在一些封装设计中，管芯被安装到衬底或芯片载体，而衬底或芯片载体又被安装在诸如印刷电路板(PCB)之类的电路面板上。例如，许多管芯提供在适于表面安装的封装中。
封装半导体管芯还能够以“堆叠”布置提供，其中一个封装被设置在例如电路板或其他载体上，而另一封装被安装在第一封装的顶部上。这些布置可以允许若干个不同的管芯或器件被安装在电路板上的单个覆盖区中，并且可以通过在封装之间提供短互连来进一步促进高速操作。通常，该互连距离只能稍微大于管芯本身的厚度。为了在管芯封装的堆叠内实现互连，可以在每个管芯封装(除了最顶部封装之外)的两侧(例如，多个面)上提供用于机械连接和电连接的互连结构。
附加地，管芯或晶片可以以三维布置堆叠，以作为各种微电子封装方案的一部分。这可以包括将一个或多个管芯、器件和/或晶片的层堆叠在较大的基部管芯、器件、晶片、衬底等上；以垂直布置或水平布置堆叠多个管芯或晶片；以及两者的各种组合。
管芯或晶片可以使用各种键合技术在堆叠布置中被键合，这些键合技术包括直接电介质键合、非粘合技术(诸如
Figure BDA0002911167460000021
)或混合键合技术(诸如
Figure BDA0002911167460000022
)，两者均可从Invensas Bonding Technologies,Inc.(以前Ziptronix，Inc.)、Xperi公司获得。键合包括自发过程，当两个已经制备的表面放在一起时，在周围条件下发生自发过程(参见，例如，美国专利号6,864,585和7,485,968，其全部内容通过引用并入本文)。
键合的管芯或晶片的相应配合表面通常包括嵌入式导电互连结构(其可以是金属)等。在一些示例中，键合表面被布置和对准，使得来自相应表面的导电互连结构在键合期间被接合。接合的互连结构在堆叠管芯或晶片之间形成连续导电互连(用于信号、功率等)。
实现堆叠管芯和晶片布置可能存在多种挑战。当使用直接键合技术或混合键合技术来键合堆叠的管芯时，通常期望要键合的管芯的表面极其平坦、光滑且干净。比如，通常，这些表面在表面拓扑上应当具有非常低的变化(即，纳米级变化)，以使这些表面可以紧密配合以形成持久键合。
可以形成和制备双面管芯以用于堆叠和键合，其中管芯的两侧将被键合到其他衬底或管芯，诸如在多个管芯到管芯的应用或管芯到晶片的应用的情况下。制备管芯的两侧包括修整两个表面以满足电介质粗糙度规格和金属层(例如，铜等)凹部规格。可以制备键合表面，以使用化学机械抛光(CMP)工艺等与另一管芯、晶片或其他衬底键合。
关于多个管芯到管芯堆叠或管芯到晶片堆叠，一些导电互连结构可以包括金属穿硅过孔(TSV)等，其部分或全部延伸通过每个管芯或晶片，从而电耦合经堆叠的芯片或晶片(有时与导电层或迹线结合)。比如，依据衬底的厚度，示例TSV可以延伸约50微米。在一些情况下，经堆叠的管芯或晶片可以包括至少两个TSV，其包括电连接到上方管芯的一个TSV和电连接到下方管芯的一个TSV。然而，由于附加TSV用于连接，所以如果堆叠2个或3个以上的管芯，则该方案可能变得不切实际。
附图说明
参照附图对具体实施方式进行阐述。在附图中，附图标记的一个或多个最左边数字标识该附图标记首次出现的附图。在不同附图中使用相同附图标记指示相似项或相同项。
为了进行讨论，图中所图示的设备和系统被示为具有多个部件。如本文中所描述的，设备和/或系统的各种实现方式可以包括较少部件，并且仍然在本公开的范围内。可替代地，设备和/或系统的其他实现方式可以包括附加部件或所描述的部件的各种组合，并且仍在本公开的范围内。
图1A示出了具有带有内部区域的导电焊盘的示例衬底的横截面。
图1B示出了图1A的示例衬底的俯视图。
图2示出了根据一个实施例的几个示例经键合衬底的横截面，其具有带有内部区域的导电焊盘、并且具有在导电焊盘的内部区域处穿过衬底而形成的TSV。
图3示出了几个示例未对准的经键合衬底的横截面，其具有带有内部区域的导电焊盘、并且具有在导电焊盘的内部区域处穿过衬底中的一些衬底而形成的TSV。
图4A示出了根据各个实施例的几个示例经键合衬底的横截面，其具有带有内部区域的导电焊盘、并且具有在该导电焊盘的内部区域处穿过该衬底而形成的TSV。
图4B示出了根据一个实施例的带有内部区域的示例导电焊盘的俯视图，其中该导电焊盘的直径增加。
图4C示出了根据一个实施例的带有内部区域的示例导电焊盘的俯视图，其中该导电焊盘的内部区域的直径增加。
图5示出了根据各个实施例的示例管芯或晶片的俯视图，其中各种导电焊盘具有不同形状的内部区域。
图6示出了根据一个实施例的几个示例经键合衬底的横截面，其具有带有内部区域的导电焊盘、并且具有在该导电焊盘的内部区域处穿过该衬底而形成的TSV。
图7是示出了根据一个实施例的形成多管芯堆叠或多晶片堆叠的公共互连的示例过程的文本流程图。
发明内容
可以采用包括过程步骤的代表性技术和设备来形成多管芯堆叠或多晶片堆叠的公共互连。堆叠的每个器件包括导电焊盘，该导电焊盘设置在器件的表面上的预先确定的相对位置处。器件被堆叠以垂直地对准导电焊盘。空腔被蚀刻通过器件，并且在空腔中形成穿硅过孔(TSV)，该穿硅过孔电耦合堆叠的每个器件的导电焊盘。
在各个实现方式中，可以形成或蚀刻导电焊盘以在焊盘的周边内包括没有导电材料的内部区域。内部区域可以在堆叠器件之前形成，这可以减少堆叠之后的过程步骤。内部区域可以具有各种形状和/或尺寸，以促进TSV的形成并且确保TSV接触堆叠的所有期望器件。
在各个示例中，从堆叠的底部器件到顶部器件，内部区域的尺寸逐渐变大。可替代地或附加地，内部区域可以具有各种形状，其包括几何形状、不规则形状等。内部区域的各种形状和尺寸可以减轻由管芯放置不准确性而导致的遮盖效果。用于减轻遮盖效果的备选技术可以包括堆叠时器件的有意偏移。
在一个实施例中，一种示例微电子组件包括多个微电子衬底，该多个微电子衬底被堆叠以形成垂直堆叠。导电焊盘设置在微电子衬底中的每个微电子衬底的表面上的第一相对位置处。微电子衬底中的每个微电子衬底的导电焊盘垂直地对准，同时多个微电子衬底形成垂直堆叠。空腔延伸通过微电子衬底中的至少除了一个微电子衬底之外的所有微电子衬底(at least all but one of the microelectronic substrates)，其中该空腔与微电子衬底中的每个微电子衬底的导电焊盘的一部分相邻。导电材料设置在空腔内，从而形成垂直堆叠的微电子衬底中的每个微电子衬底所共有的穿硅过孔(TSV)。TSV包括层间连接，其电耦合到微电子衬底中的每个微电子衬底的导电焊盘。
参考电气部件和电子部件以及各种载体对各种实现方式和布置进行了讨论。虽然提及了特定部件(即，管芯、晶片、集成电路(IC)芯片管芯、衬底等)，但这并不旨在是限制性的，并且为了便于讨论和说明方便。参考晶片、管芯、衬底等所讨论的技术和设备可应用于任何类型或数目的电子部件、电路(例如，集成电路(IC)、混合电路、ASICS、存储器设备、处理器等)、部件组、封装部件、结构(例如，晶片、面板、板、PCB等)等，其可以与接口彼此耦合、并且与外部电路、系统、载体等耦合。这些不同部件、电路、组、封装、结构等中的每个部件、电路、组、封装、结构等都可以统称为“微电子部件”。为了简单起见，除非另有说明，否则键合到另一部件的部件本文中被称为“管芯”。
该发明内容并不旨在给出完整描述。下文使用多个示例对实现方式进行更详细的解释。尽管本文中和下文对各种实现方式和示例进行了讨论，但是通过组合各个实现方式和示例的特征和元件，其他实现方式和示例是可能的。
具体实施方式
概述
在各个实施例中，可以采用技术和设备来简化管芯到管芯堆叠、管芯到晶片堆叠或晶片到晶片堆叠中的所有期望管芯和/或晶片的通用电连接，特别是当堆叠2个或3个以上的管芯和/或晶片时。本文中与管芯有关的讨论还涉及这种堆叠中的晶片或其他衬底。
参看图1A(其示出了横截面轮廓视图)和图1B(其示出了俯视图)，图案化的金属和氧化物层通常作为混合键合、或
Figure BDA0002911167460000061
表面层而被设置在管芯、晶片或其他微电子衬底(以下称为“管芯102”)上。可以使用各种技术来形成代表性器件管芯102，以包括基部衬底104和一个或多个绝缘或电介质层106。基部衬底104可以由硅、锗、玻璃、石英、电介质表面、直接间隙半导体材料或层、或间接间隙半导体材料或层或其他合适材料组成。绝缘层106被沉积或形成在衬底104上方，并且可以由诸如氧化物、氮化物、氧氮化物、碳氧化物、碳化物、碳氮化物、金刚石、类金刚石材料、玻璃、陶瓷、玻璃-陶瓷等之类的无机电介质材料层组成。
形成键合表面108包括：修整绝缘层106的表面108以满足电介质粗糙度规格和任何金属层(例如，铜迹线、结构、焊盘等)以满足凹部规格，以制备表面108以供直接键合。换句话说，键合表面108被形成为尽可能平坦光滑，其中表面拓扑变化非常小。诸如化学机械抛光(CMP)、干法蚀刻或湿法蚀刻等之类的各种传统工艺可以用于实现低表面粗糙度。该工艺提供了产生可靠键合的平坦、光滑表面108。
在双侧管芯102(未示出)的情况下，可以在管芯102的两侧上提供具有经制备的键合表面108的图案化的金属和绝缘层106。绝缘层106通常高度平坦(通常达到nm级粗糙度)，其中金属层(例如，嵌入式导电特征)位于键合表面108处或正好凹陷到键合表面108下方。通常，绝缘层106的表面108下方的凹陷量由尺寸公差、规格、或物理限制确定。通常使用化学机械抛光(CMP)步骤和/或其他准备步骤来制备键合表面108，以用于与另一管芯、晶片或其他衬底直接键合。
如图1A和图1B所示，器件晶片102的键合表面108可以包括嵌入绝缘层106(例如，部分地延伸到经制备的表面108下方的电介质衬底106中)中的导电焊盘110或其他导电特征，诸如迹线、互连结构等。如果需要，则可以布置焊盘110，以使来自其他设备的导电特征可以在键合期间被配合并且接合到焊盘110。接合的导电特征可以在堆叠器件之间形成连续导电互连(用于信号、功率等)。
镶嵌工艺(damascene process)(或其他工艺)可以用于在绝缘层106中形成焊盘110或其他导电特征。比如，一些图案化的金属焊盘110或其他导电特征的厚度可以约为0.5微米至2微米，并且在键合表面108下方延伸。焊盘110或导电特征可以由金属(例如，铜等)或其他导电材料或材料的组合等组成。
在一些示例中，在沉积焊盘110的材料之前，可以在用于焊盘110的空腔中沉积阻挡层(未示出)，使得阻挡层设置在焊盘110与绝缘层106之间。阻挡层可以由例如钽或其他导电材料组成，以防止或减少焊盘110的材料扩散到绝缘层106中。在形成焊盘110之后，可以(例如，经由CMP)对器件晶片102的包括绝缘层106和焊盘110或其他导电特征在内的暴露表面进行平坦化，以形成平坦键合表面108。
如图1A和图1B所示，导电焊盘110可以被形成为：在焊盘110的周边内，具有没有导电材料的内部区域112，以适应各种应用，如下文所进一步讨论的。比如，焊盘110可以被形成为具有各种形状，诸如“O”、“U”、“C”、“G”、“D”以及其他形状，该其他形状包括没有导电材料的内侧区域(与内部区域112相似)、以及包围内侧的内部区域的外导电区域(其可以部分或完全地合围内侧非导电区域)。在一些实施例中，内部区域112包括或暴露绝缘材料，诸如绝缘层106，并且在其他实施例中，内部区域112可以包括凹部、空腔、孔口、或部分或完全通过管芯102的其他孔洞。
可替代地，在没有内部区域112的情况下，可以形成焊盘110。在一些实施例中，如下文所进一步讨论的，在没有内部区域112的情况下形成的焊盘110可以在制造和/或器件组装期间被蚀刻或以其他方式被处理以具有内部区域112。
示例实施例
参考图2，管芯102可以被堆叠和键合，其包括比如在没有粘合剂的情况下直接粘合到具有导电焊盘110的其他管芯102，。在一个实施例中，堆叠200(例如，微电子组件)的管芯102中的每个管芯包括导电焊盘110，该导电焊盘110设置在管芯102的表面上的相同相对位置处。当管芯102以垂直配置堆叠时，在每个管芯102上的相同位置处具有导电焊盘110允许每个管芯102上的导电焊盘110垂直排列。
当一个管芯102的导电焊盘110位于另一管芯102的导电焊盘110上方时，可以在导电焊盘110之间形成TSV 202，其中TSV 202穿过一个或两个管芯102，从而将导电焊盘110电耦合在一起。换句话说，TSV 202可以电耦合到TSV 202接触的管芯102中的每个管芯102上的导电焊盘110，从而在接触的管芯102之间形成电连接。
在各个实现方式中，如图2所示，单个TSV 202可以用于连接堆叠200中的所有管芯102，其中TSV 202延伸到堆叠200中的所有管芯102。在实现方式中，TSV 202可以一直延伸通过堆叠200的顶部管芯102和/或底部管芯102、或不延伸通过堆叠200的顶部管芯102和/或底部管芯102，但是可以延伸通过顶部管芯102与底部管芯102之间的管芯102中的每个管芯102，并且连接到顶部管芯102和底部管芯102。例如，如果需要在顶部管芯102或底部管芯102的外部表面处电连接到另一微电子部件，则TSV 202可以延伸通过顶部管芯102或底部管芯102。
在一个示例中，导电焊盘110由金属(比如，诸如铜或铜合金)形成在每个管芯102的至少一个表面上。当管芯102在导电焊盘110对准的情况下堆叠时，过程可以用于在导电焊盘110处形成穿过所有期望管芯102的空腔204。在一个实现方式中，空腔202形成在每个管芯102的每个导电焊盘110的内部区域112处。在导电焊盘110没有内部区域112的另一实现方式中，当空腔202延伸通过堆叠200的管芯102时，在每个导电焊盘110的周长之内的位置处，形成空腔202。
比如，该过程可以包括交替进行金属蚀刻(例如，以蚀刻金属导电焊盘110中的内部区域112)、氧化物蚀刻(例如，以蚀刻通过每个管芯102的绝缘层106)、以及用于堆叠200中的管芯102中的每个管芯102的硅蚀刻(例如，以蚀刻通过每个管芯102的基部层104)，以形成空腔204。在蚀刻通过堆叠200的每个管芯102时，这些步骤可以交替进行。在备选实施例中，如果存在管芯102中的一个或多个管芯102上，则附加蚀刻步骤可以用于蚀刻通过其他层。进一步地，当内部区域112预先形成在堆叠200的管芯102的导电焊盘110上时，可以无需金属蚀刻。
空腔204可以使用沉积工艺(或其他工艺)填充有导电材料(例如，诸如铜之类的金属)，以将堆叠200中的所有管芯102与公共TSV 202电耦合(例如，以使用TSV 202形成堆叠200中的所有管芯102的层间电连接)。应当指出，最底部管芯102的导电焊盘110无需被蚀刻，以具有内部区域112以形成层间连接。进一步地，如果在TSV 202下方不期望电连接，则空腔204和TSV 202无需延伸通过最底部管芯102。然而，如果在TSV 202下方期望电连接，则空腔204和TSV 202可以(通过在最底部管芯102处进行蚀刻和填充)延伸到最底部管芯102和堆叠200的外表面。
TSV 202可以包括诸如金属(例如，铜)之类的导电材料，并且在与每个管芯的键合表面108正交的情况下，部分地或全部地延伸通过一个或多个管芯102(其依据期望堆叠200的哪些管芯102在TSV 202的层间连接节点处被电耦合)。比如，依据管芯102的厚度，TSV202可以延伸通过管芯102约50微米。
在各个实施例中，例如，如图1B所示，在堆叠之前，可以在管芯102中的一个或多个管芯102上对导电焊盘110进行预先图案化，以减少形成层间连接(例如，TSV 202)时的过程步骤。比如，导电焊盘110中的每个导电焊盘110可以被预先图案化(形成或蚀刻)，其具有没有导电材料的内部区域112，该内部区域112具有预先确定的尺寸、形状等，以消除堆叠管芯102之后的过程的金属蚀刻部分。当导电焊盘110在焊盘110的内部部分处预先形成有非导电部分112时，可以在内部区域112内，对管芯102的氧化物层106和硅层104(在导电焊盘110的内部部分处并且与导电焊盘110的导电部分直接相邻)进行蚀刻，以在管芯102被堆叠之后，形成空腔204。
当空腔204填充有导电材料(例如，金属)时，导电材料在堆叠管芯102中的每个堆叠管芯102处接触导电焊盘110中的每个导电焊盘110，以形成层间连接(例如，TSV 202)。在各个实现方式中，可以以“O”、“C”、“U”、“G”、“D”或具有内部敞口区域(例如，开口112)的任何几何形状或预选形状形成(沉积或蚀刻)导电焊盘110。在一个示例中，内部非导电区域112的宽度或直径大约为5微米至10微米。在一些实施例中，由于可能无需将焊盘110连接到管芯102的另一侧，所以最底部管芯102的导电焊盘110可以形成有内部区域112、或可以不形成有内部区域112。
在另一实施例中，堆叠200的各个管芯102上的导电焊盘110的尺寸、和/或每个导电焊盘110的内部区域112的尺寸可以不均匀。这种不均匀的尺寸布置可以允许将空腔204蚀刻通过到达最底部管芯102的导电焊盘110，同时考虑到堆叠管芯102之间的随机未对准。比如，虽然图2表示具有理想管芯102放置的管芯堆叠200，但是在大容量制造设置中，完美对准的管芯102可能不切实际或不太可能。图3示出了可能更可能的管芯堆叠200，其中管芯102之间的平均未对准为“m”。
如图3所示，管芯102的随机未对准(基于堆叠期间的管芯102放置的误差)可以导致预先图案化的导电焊盘110的金属部分交叠、或遮盖堆叠200中的下部管芯102上的内部区域112(其包括绝缘层106和硅基部层104)。当导电焊盘110和内部区域112在管芯102中的每个管芯102之中均匀或接近均匀时，这可能是个问题。遮盖可能导致在氧化物和硅蚀刻步骤期间遗漏下部管芯102。在那种情况下，空腔204和所得TSV 202不会延伸到“遗漏的”管芯102，这可以阻止它们被包括在层间连接中。由于堆叠200的底部处的遗漏的管芯102的可能性可能随着附加的未对准管芯102而增加，所以这种“遗漏的管芯”效应可能随着堆叠200中具有更多数目的管芯102而更糟。
在各个实施例中，以不均匀布置形成导电焊盘110和/或内部区域112可以通过减少遮盖来减轻堆叠200中的“遗漏的芯片”效应。比如，在如图4A所示的实施例中，形成导电焊盘110并且堆叠管芯102，使得导电焊盘110的内部区域112随着每个管芯102而逐渐增大，从而从堆叠200的底部管芯102(或从底部管芯102数第二管芯(the second from thebottom die 102))向顶部管芯102前进。
在该实施例中，导电焊盘110的内部区域112的预先确定的尺寸递增可以被布置为大于潜在未对准误差“m”。结果，下部导电焊盘110与上部导电焊盘110的任何交叠或遮盖都不是下部导电焊盘110的内部区域112的全部遮盖，并且不足以防止下部管芯102的内部区域112被蚀刻，以在下部管芯102(如果需要，则包括倒数第二管芯102和/或最底部管芯102)中形成空腔204。因此，如果需要，则由于空腔204和所得TSV 202延伸到倒数第二管芯102和/或最底部管芯102，所以堆叠200中不存在“遗漏的管芯102”。
作为一个示例，根据一个实现方式，图4B和图4C各自以焊盘110可以布置在管芯堆叠200中的次序示出了导电焊盘110的集合。应当指出，如图4A所示，在管芯堆叠200中，导电焊盘110可能布置在彼此上方。如图4B和图4C所示，内侧的内部区域112的直径变得越来越大，从最底部焊盘110处的直径“d1”到顶部焊盘110处的直径“d2”(其中d1<d2)。
如图4B所示，导电焊盘110的总直径还可以从最底部焊盘110处的直径“d3”增加到顶部焊盘110处的直径“d4”(其中d3＜d4)。如果需要，则增加导电焊盘110的总直径可以允许焊盘110的导电外“环”具有相同或相似的厚度(例如，d3-d1＝d4-d2)。在其他方式中，如图4C所示，导电焊盘110的外径可以均匀(其中d3＝d4)。在一些情况下，使导电焊盘110的外径均匀可以简化制造。
参考图5，在另一实施例中，导电焊盘110的内部区域112可以形成为具有预先确定的图案或形状。基于选择的图案或形状，即使当图案在堆叠200的管芯102中的每个管芯上(针对给定空腔204和TSV 202)均匀时，堆叠的图案化的导电焊盘110也可以避免堆叠200中的下部管芯102处的内部区域112上的总遮盖效应(由于随机未对准)。
图5的示例导电焊盘110示出了用于内部区域112的一些非限制性示例图案和形状。在各个实现方式中，导电焊盘110的内部区域112的图案或形状可以包括多边形、几何形状、偏心或不规则形状、多刻面形状等。在一些实现方式中，导电焊盘110的整体形状还可以包括多边形、几何形状、偏心或不规则形状、多刻面形状等。在各个实现方式中，根据管芯102的放置准确性，可以选择区域112的尺寸、图案和形状以获得最高成功概率(例如，在无需蚀刻导电焊盘的情况下，完全层间电连接)。
参考图6，在另一实施例中，在管芯200放置在堆叠200上时，可以通过预先确定的有意偏移来减轻遮盖效应。在该实施例中，内部区域112的尺寸和形状以及导电焊盘110的整体直径和形状可以是如参考上文关于图1B、图4B、图4C和图5中的任一附图而被讨论。如图6所示，对于堆叠200中的每个管芯102，导电焊盘110和内部区域112在尺寸和形状上可以均匀。在该实施例中，管芯102以预先确定的偏移“o”堆叠。
如图6所示，具有有意偏移的堆叠布置可以允许将空腔204蚀刻通过到达堆叠200的底部管芯102的导电焊盘110，同时考虑到堆叠管芯102之间的随机未对准。在一个实施例中，添加到堆叠中的管芯102在预先确定的方向上被偏移、并且被偏移预先确定的程度“o”。例如，每个管芯102可以在180度方向上有意偏移0.5微米(比如)。
在该实施例中，有意偏移“o”被选择为稍大于管芯放置工具的平均放置误差“m”。有意偏移“o”的累积效应导致下部管芯102上的区域112的遮盖减少，因此当蚀刻堆叠的管芯102的绝缘层106和硅基部层104(例如，无需蚀刻导电焊盘110中的任一导电焊盘110)时，空腔204很可能延伸到最底部管芯102的导电焊盘110。
在备选实施例中，导电焊盘110的内部区域112的尺寸和形状以及管芯102的布置可以具有备选配置，以考虑随机未对准。进一步地，可以一起采用所公开的技术的任何组合以考虑随机未对准。
示例过程
图7图示了根据各种实施例的形成多管芯堆叠或多晶片堆叠(例如，诸如堆叠200)的公共互连的代表性过程700。例如，穿硅过孔(TSV)可以在管芯中的每个管芯处相似处境的接触焊盘处被形成在空腔中，空腔被设置通过堆叠的管芯中的每个管芯。TSV包括层间连接，该层间连接在每个管芯处电耦合相似处境的接触焊盘。该过程参考图1至图6。
描述过程的次序不旨在被解释为限制性的，并且过程中的任何数目的所描述的过程框可以以任何次序组合以实现过程或备选过程。附加地，在没有背离本文中所描述的主题的精神和范围的情况下，可以从过程中删除各个框。更进一步地，在没有背离本文中所描述的主题的范围的情况下，可以以任何合适硬件、软件、固件或其组合来实现该过程。在备选实现方式中，其他技术可以以各种组合包括在该过程中，并且仍在本公开的范围内。
在一个实现方式中，在框702处，过程700包括：在多个微电子衬底(例如，诸如管芯102)的每个微电子衬底的表面上的第一相对位置处，形成导电焊盘(例如，诸如导电焊盘110)。
在一个实现方式中，该过程包括：在微电子衬底中的、至少除了一个微电子衬底之外的所有微电子衬底的表面上形成导电焊盘，以包括内部区域，该内部区域没有导电焊盘的导电材料的。
在一个实现方式中，该过程包括：将堆叠的每个微电子衬底的导电焊盘的内部区域形成为具有不同的最大尺寸。在一个实施例中，该方法包括：将堆叠的每个后续微电子衬底的导电焊盘的内部区域形成为其最大尺寸大于先前放置的微电子衬底的导电焊盘的内部区域的最大尺寸。
在一个实现方式中，该过程包括：对导电焊盘进行图案化以具有“O”、“C”、“D”、“G”或“U”形状。
在一个示例中，该过程包括：对导电焊盘的外部周边进行图案化，以具有第一预先确定的尺寸和形状，并且对导电焊盘的内部部分进行图案化，以具有第二预先确定的尺寸和形状。在一个实现方式中，该过程包括：形成第二预先确定的尺寸和形状以包括多边形、几何形状、偏心形状、不规则形状、或多刻面形状。
在框704处，该过程包括：堆叠多个微电子衬底以形成微电子衬底的垂直堆叠，同时在每个微电子衬底处垂直对准导电焊盘。在一些实施例中，在键合之后，微电子衬底(其在键合之前可以更厚)可以根据需要减薄。例如，在将微电子衬底键合到另一微电子衬底或堆叠之后，可以减薄每个微电子衬底。
在框706处，该过程包括：蚀刻微电子衬底中的、至少除了一个微电子衬底之外的所有微电子衬底的一个或多个层，以形成空腔，该空腔延伸通过微电子衬底中的、至少除了一个微电子衬底之外的所有微电子衬底。在该实现方式中，空腔与微电子衬底中的每个微电子衬底上的导电焊盘的一部分相邻。在一个示例中，该过程包括：在导电焊盘的内部区域或敞开区域内形成空腔。在另一实现方式中，该过程包括：由于在多个微电子衬底的每个微电子衬底的表面上形成导电焊盘以包括敞开区域而减少用于形成空腔的至少一个迭代蚀刻步骤。
在框708处，该过程包括：使用导电材料填充空腔以形成垂直堆叠的微电子衬底中的每个微电子衬底所共有的穿硅过孔(TSV)。在实现方式中，TSV包括层间连接，该层间连接在每个微电子衬底处电耦合导电焊盘。
在一个实现方式中，该方法包括：在形成空腔之前，使用无需粘合剂的环境温度直接键合技术将堆叠中的多个微电子衬底彼此键合。
在一个实现方式中，导电焊盘的内部区域的尺寸在整个微电子衬底中不均匀。在一个示例中，从堆叠的底部的微电子衬底到堆叠的顶部的微电子衬底，导电焊盘的内部区域的尺寸随着堆叠的微电子衬底中的每个微电子衬底逐渐增加。
在一个实现方式中，该过程包括：通过相对于先前放置的微电子衬底在第一偏移方向上使每个后续微电子衬底有意偏移预先确定的距离来形成垂直堆叠。在一个示例中，预先确定的距离大于用于堆叠多个微电子衬底以形成垂直堆叠的管芯放置工具的平均管芯放置误差。
在一个实现方式中，微电子衬底各自可以从与导电焊盘相对的一侧减薄，以减小TSV必须延伸的程度。在每个微电子衬底堆叠在先前管芯或支撑衬底上时，可以进行这种减薄。而且，虽然示出了以面到背定向堆叠的微电子衬底，但是微电子衬底可以以面到面定向或背到背定向放置。
在各个实施例中，与本文中所描述的过程步骤相比较，一些过程步骤可以被修改或消除。
本文中所描述的技术、部件和设备不限于图1至图7的图示，并且在没有脱离本公开的范围的情况下，可以应用于包括其他电气部件的其他设计、类型、布置和构造。在一些情况下，附加或备选部件、技术、序列或过程可以用于实现本文中所描述的技术。进一步地，可以以各种组合来布置和/或组合部件和/或技术，同时导致相似或大约相同的结果。
结论
尽管已经以特定于结构特征和/或方法动作的语言对本公开的实现方式进行了描述，但是应当理解，实现方式不必限于所描述的特定特征或动作。相反，特定特征和动作被公开为实现示例设备和技术的代表性形式。

Claims (24)

1.一种形成微电子部件的方法，包括：
在多个微电子衬底的每个微电子衬底的表面上的第一相对位置处，形成导电焊盘；
堆叠所述多个微电子衬底以形成微电子衬底的垂直堆叠，同时在每个微电子衬底处垂直地对准所述导电焊盘；
蚀刻所述微电子衬底中的、至少除了一个微电子衬底之外的所有微电子衬底的一个或多个层，以形成空腔，所述空腔延伸通过所述微电子衬底中的、至少除了一个微电子衬底之外的所有所述微电子衬底，所述空腔与所述微电子衬底中的每个微电子衬底上的所述导电焊盘的一部分相邻；以及
使用导电材料填充所述空腔以形成所述垂直堆叠的所述微电子衬底中的每个微电子衬底所共有的穿硅过孔(TSV)，所述TSV包括层间连接，所述层间连接在每个微电子衬底处电耦合所述导电焊盘。
2.根据权利要求1所述的形成微电子部件的方法，还包括：在所述微电子衬底中、至少除了一个微电子衬底之外的所有所述微电子衬底的所述表面上形成包括没有导电材料的内部区域的所述导电焊盘。
3.根据权利要求2所述的形成微电子部件的方法，还包括：对所述导电焊盘的外部周边进行图案化以具有第一预先确定的尺寸和形状，并且对所述导电焊盘的所述内部部分进行图案化以具有第二预先确定的尺寸和形状。
4.根据权利要求3所述的形成微电子部件的方法，还包括：对所述导电焊盘进行图案化以具有“O”、“C”、“D”、“G”或“U”形状。
5.根据权利要求3所述的形成微电子部件的方法，其中所述第二预先确定的尺寸和形状包括多边形、几何形状、偏心形状、不规则形状、或多刻面形状。
6.根据权利要求2所述的形成微电子部件的方法，还包括：形成穿过所述导电焊盘的所述内部区域的所述空腔。
7.根据权利要求2所述的形成微电子部件的方法，还包括：通过在所述多个微电子衬底的每个微电子衬底的所述表面上形成包括所述内部区域的所述导电焊盘，来减少用于形成所述空腔的迭代蚀刻步骤。
8.根据权利要求2所述的形成微电子部件的方法，其中所述导电焊盘的所述内部区域的尺寸在所述微电子衬底上整体上不均匀。
9.根据权利要求8所述的形成微电子部件的方法，其中所述导电焊盘的所述内部区域的尺寸随着所述堆叠的所述微电子衬底中的每个微电子衬底从所述堆叠的底部的微电子衬底到所述堆叠的顶部处的微电子衬底而逐渐增大。
10.根据权利要求2所述的形成微电子部件的方法，还包括：通过有意使每个后续微电子衬底相对于先前放置的微电子衬底在第一偏移方向上偏移预先确定的距离来形成所述垂直堆叠。
11.根据权利要求10所述的形成微电子部件的方法，其中所述预先确定的距离大于用于堆叠所述多个微电子衬底以形成所述垂直堆叠的管芯放置工具的平均管芯放置误差。
12.根据权利要求1所述的形成微电子部件的方法，还包括：在形成所述空腔之前，使用无需粘合剂的环境温度直接键合技术键合所述多个微电子衬底。
13.一种形成微电子部件的方法，包括：
在多个微电子衬底的每个微电子衬底的表面上的第一相对位置处形成导电焊盘，所述导电焊盘包括没有导电材料的内部区域；
堆叠所述多个微电子衬底以形成微电子衬底的垂直堆叠，同时在每个微电子衬底处垂直地对准所述导电焊盘；
蚀刻所述微电子衬底中的、至少除了一个微电子衬底之外的所有微电子衬底的一个或多个层，以形成空腔，所述空腔延伸通过所述微电子衬底中的、至少除了一个微电子衬底之外的所有所述微电子衬底，所述空腔与所述导电焊盘的一部分相邻并且延伸通过所述微电子衬底中的、至少除了一个微电子衬底之外的所有所述微电子衬底的所述导电焊盘的所述内部区域；以及
使用导电材料填充所述空腔以形成所述垂直堆叠的所述微电子衬底中的每个微电子衬底所共有的穿硅过孔(TSV)，所述TSV包括层间连接，所述层间连接在每个微电子衬底处电耦合所述导电焊盘。
14.根据权利要求13所述的形成微电子部件的方法，还包括：将所述堆叠的每个微电子衬底的所述导电焊盘的所述内部区域形成为具有不同的最大尺寸。
15.根据权利要求13所述的形成微电子部件的方法，还包括：形成所述堆叠的每个后续微电子衬底的所述导电焊盘的所述内部区域，以使其最大尺寸大于先前放置的微电子衬底的所述导电焊盘的所述内部区域的最大尺寸。
16.根据权利要求13所述的形成微电子部件的方法，还包括：将所述堆叠的每个微电子衬底的所述导电焊盘的所述内部区域形成为具有预先确定的尺寸和形状，所述预先确定的形状包括多边形、几何形状、偏心形状、不规则形状、或多刻面形状。
17.一种微电子部件，包括：
多个微电子衬底，被堆叠为以形成垂直堆叠；
导电焊盘，设置在所述多个微电子衬底的每个微电子衬底的表面上的第一相对位置处，所述微电子衬底中的每个微电子衬底的导电焊盘垂直地对准，同时所述多个微电子衬底形成所述垂直堆叠；
空腔，延伸通过所述微电子衬底中的、至少除了一个微电子衬底之外的所有微电子衬底，所述空腔与所述微电子衬底中的每个微电子衬底的所述导电焊盘的一部分相邻；以及
导电材料，位于所述空腔内以用于形成所述垂直堆叠的所述微电子衬底中的每个微电子衬底所共有的穿硅过孔(TSV)，所述TSV包括层间连接，所述层间连接电耦合到所述微电子衬底中的每个微电子衬底的所述导电焊盘。
18.根据权利要求17所述的微电子部件，其中在所述微电子衬底中的、至少除了一个微电子衬底之外的所有所述微电子衬底的所述导电焊盘包括没有导电材料的内部区域。
19.根据权利要求18所述的微电子部件，其中所述内部区域具有预先确定的尺寸和形状，所述形状包括多边形、几何形状、偏心形状、不规则形状、或多刻面形状。
20.根据权利要求18所述的微电子部件，其中所述空腔延伸通过所述微电子衬底中的、至少除了一个微电子衬底之外的所有所述微电子衬底的所述导电焊盘的所述内部区域。
21.根据权利要求18所述的微电子部件，其中所述导电焊盘的所述内部区域的尺寸在所述微电子衬底中的、至少除了一个微电子衬底之外的所有所述微电子衬底上整体上不均匀。
22.根据权利要求21所述的微电子部件，其中所述内部区域的所述尺寸从所述堆叠的底部的微电子衬底到所述堆叠的顶部处的微电子衬底而逐渐增大。
23.根据权利要求17所述的微电子部件，其中所述堆叠的每个微电子衬底相对于所述堆叠中的上方或下方的微电子衬底具有有意的预先确定的偏移，所述预先确定的偏移大于用于堆叠所述多个微电子衬底以形成所述垂直堆叠的管芯放置工具的平均管芯放置误差。
24.根据权利要求17所述的微电子部件，其中在形成所述空腔之前，所述多个微电子衬底使用无需粘合剂的环境温度直接键合技术而被键合在一起。
CN201980049050.XA 2018-06-12 2019-06-12 堆叠微电子部件的层间连接 Active CN112514059B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201862683857P 2018-06-12 2018-06-12
US62/683,857 2018-06-12
PCT/US2019/036741 WO2019241367A1 (en) 2018-06-12 2019-06-12 Interlayer connection of stacked microelectronic components

Publications (2)

Publication Number Publication Date
CN112514059A true CN112514059A (zh) 2021-03-16
CN112514059B CN112514059B (zh) 2024-05-24

Family

ID=68765270

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201980049050.XA Active CN112514059B (zh) 2018-06-12 2019-06-12 堆叠微电子部件的层间连接

Country Status (3)

Country Link
US (2) US11171117B2 (zh)
CN (1) CN112514059B (zh)
WO (1) WO2019241367A1 (zh)

Families Citing this family (58)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7109092B2 (en) 2003-05-19 2006-09-19 Ziptronix, Inc. Method of room temperature covalent bonding
US7485968B2 (en) 2005-08-11 2009-02-03 Ziptronix, Inc. 3D IC method and device
US8735219B2 (en) 2012-08-30 2014-05-27 Ziptronix, Inc. Heterogeneous annealing method and device
US10886250B2 (en) 2015-07-10 2021-01-05 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
US10204893B2 (en) 2016-05-19 2019-02-12 Invensas Bonding Technologies, Inc. Stacked dies and methods for forming bonded structures
US10580735B2 (en) 2016-10-07 2020-03-03 Xcelsis Corporation Stacked IC structure with system level wiring on multiple sides of the IC die
US10719762B2 (en) 2017-08-03 2020-07-21 Xcelsis Corporation Three dimensional chip structure implementing machine trained network
TWI822659B (zh) 2016-10-27 2023-11-21 美商艾德亞半導體科技有限責任公司 用於低溫接合的結構和方法
US10002844B1 (en) 2016-12-21 2018-06-19 Invensas Bonding Technologies, Inc. Bonded structures
TWI782939B (zh) 2016-12-29 2022-11-11 美商英帆薩斯邦德科技有限公司 具有整合式被動構件的接合結構
US10629577B2 (en) 2017-03-16 2020-04-21 Invensas Corporation Direct-bonded LED arrays and applications
US10515913B2 (en) 2017-03-17 2019-12-24 Invensas Bonding Technologies, Inc. Multi-metal contact structure
US10269756B2 (en) 2017-04-21 2019-04-23 Invensas Bonding Technologies, Inc. Die processing
US10879212B2 (en) 2017-05-11 2020-12-29 Invensas Bonding Technologies, Inc. Processed stacked dies
US10446441B2 (en) 2017-06-05 2019-10-15 Invensas Corporation Flat metal features for microelectronics applications
US10840205B2 (en) 2017-09-24 2020-11-17 Invensas Bonding Technologies, Inc. Chemical mechanical polishing for hybrid bonding
US11031285B2 (en) 2017-10-06 2021-06-08 Invensas Bonding Technologies, Inc. Diffusion barrier collar for interconnects
US11380597B2 (en) 2017-12-22 2022-07-05 Invensas Bonding Technologies, Inc. Bonded structures
US10923408B2 (en) 2017-12-22 2021-02-16 Invensas Bonding Technologies, Inc. Cavity packages
US10727219B2 (en) 2018-02-15 2020-07-28 Invensas Bonding Technologies, Inc. Techniques for processing devices
US11169326B2 (en) 2018-02-26 2021-11-09 Invensas Bonding Technologies, Inc. Integrated optical waveguides, direct-bonded waveguide interface joints, optical routing and interconnects
US11056348B2 (en) 2018-04-05 2021-07-06 Invensas Bonding Technologies, Inc. Bonding surfaces for microelectronics
US10790262B2 (en) 2018-04-11 2020-09-29 Invensas Bonding Technologies, Inc. Low temperature bonded structures
US10964664B2 (en) 2018-04-20 2021-03-30 Invensas Bonding Technologies, Inc. DBI to Si bonding for simplified handle wafer
US11004757B2 (en) 2018-05-14 2021-05-11 Invensas Bonding Technologies, Inc. Bonded structures
US11276676B2 (en) 2018-05-15 2022-03-15 Invensas Bonding Technologies, Inc. Stacked devices and methods of fabrication
US11749645B2 (en) 2018-06-13 2023-09-05 Adeia Semiconductor Bonding Technologies Inc. TSV as pad
US11393779B2 (en) 2018-06-13 2022-07-19 Invensas Bonding Technologies, Inc. Large metal pads over TSV
US10910344B2 (en) 2018-06-22 2021-02-02 Xcelsis Corporation Systems and methods for releveled bump planes for chiplets
WO2020010056A1 (en) 2018-07-03 2020-01-09 Invensas Bonding Technologies, Inc. Techniques for joining dissimilar materials in microelectronics
US11462419B2 (en) 2018-07-06 2022-10-04 Invensas Bonding Technologies, Inc. Microelectronic assemblies
US11158606B2 (en) 2018-07-06 2021-10-26 Invensas Bonding Technologies, Inc. Molded direct bonded and interconnected stack
US11515291B2 (en) 2018-08-28 2022-11-29 Adeia Semiconductor Inc. Integrated voltage regulator and passive components
US20200075533A1 (en) 2018-08-29 2020-03-05 Invensas Bonding Technologies, Inc. Bond enhancement in microelectronics by trapping contaminants and arresting cracks during direct-bonding processes
WO2020043171A1 (en) * 2018-08-31 2020-03-05 Changxin Memory Technologies, Inc. Memory device, semiconductor device and method for manufacturing the same
US11158573B2 (en) 2018-10-22 2021-10-26 Invensas Bonding Technologies, Inc. Interconnect structures
KR20210104742A (ko) 2019-01-14 2021-08-25 인벤사스 본딩 테크놀로지스 인코포레이티드 접합 구조체
US11901281B2 (en) 2019-03-11 2024-02-13 Adeia Semiconductor Bonding Technologies Inc. Bonded structures with integrated passive component
US10854578B2 (en) 2019-03-29 2020-12-01 Invensas Corporation Diffused bitline replacement in stacked wafer memory
US11610846B2 (en) 2019-04-12 2023-03-21 Adeia Semiconductor Bonding Technologies Inc. Protective elements for bonded structures including an obstructive element
US11373963B2 (en) 2019-04-12 2022-06-28 Invensas Bonding Technologies, Inc. Protective elements for bonded structures
US11205625B2 (en) 2019-04-12 2021-12-21 Invensas Bonding Technologies, Inc. Wafer-level bonding of obstructive elements
US11355404B2 (en) 2019-04-22 2022-06-07 Invensas Bonding Technologies, Inc. Mitigating surface damage of probe pads in preparation for direct bonding of a substrate
US11296053B2 (en) 2019-06-26 2022-04-05 Invensas Bonding Technologies, Inc. Direct bonded stack structures for increased reliability and improved yield in microelectronics
US11862602B2 (en) 2019-11-07 2024-01-02 Adeia Semiconductor Technologies Llc Scalable architecture for reduced cycles across SOC
US11762200B2 (en) 2019-12-17 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Bonded optical devices
US11876076B2 (en) 2019-12-20 2024-01-16 Adeia Semiconductor Technologies Llc Apparatus for non-volatile random access memory stacks
US11721653B2 (en) 2019-12-23 2023-08-08 Adeia Semiconductor Bonding Technologies Inc. Circuitry for electrical redundancy in bonded structures
US11842894B2 (en) 2019-12-23 2023-12-12 Adeia Semiconductor Bonding Technologies Inc. Electrical redundancy for bonded structures
US11417629B2 (en) * 2020-02-11 2022-08-16 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional stacking structure and manufacturing method thereof
KR20230003471A (ko) 2020-03-19 2023-01-06 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드 직접 결합된 구조체들을 위한 치수 보상 제어
US11742314B2 (en) 2020-03-31 2023-08-29 Adeia Semiconductor Bonding Technologies Inc. Reliable hybrid bonded apparatus
US11735523B2 (en) 2020-05-19 2023-08-22 Adeia Semiconductor Bonding Technologies Inc. Laterally unconfined structure
US11631647B2 (en) 2020-06-30 2023-04-18 Adeia Semiconductor Bonding Technologies Inc. Integrated device packages with integrated device die and dummy element
US11728273B2 (en) 2020-09-04 2023-08-15 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US11764177B2 (en) 2020-09-04 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US11264357B1 (en) 2020-10-20 2022-03-01 Invensas Corporation Mixed exposure for large die
KR20220060915A (ko) * 2020-11-05 2022-05-12 삼성전자주식회사 오버레이 측정용 tsv 키, 및 그 tsv 키를 포함한 반도체 소자 및 반도체 패키지

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101558483A (zh) * 2005-08-11 2009-10-14 齐普特洛尼克斯公司 三维ic方法和器件
CN101740484A (zh) * 2008-11-25 2010-06-16 台湾积体电路制造股份有限公司 形成穿透硅通孔的方法
CN101802990A (zh) * 2007-07-31 2010-08-11 泰塞拉公司 使用穿透硅通道的半导体封装方法
CN102024782A (zh) * 2010-10-12 2011-04-20 北京大学 三维垂直互联结构及其制作方法
US20110108972A1 (en) * 2009-11-12 2011-05-12 International Business Machines Corporation Integrated Circuit Die Stacks With Translationally Compatible Vias
CN102150257A (zh) * 2008-09-11 2011-08-10 美光科技公司 堆叠式装置识别指派
CN102187458A (zh) * 2008-09-11 2011-09-14 美光科技公司 包含用于穿硅通孔的穿透结构的堆叠式裸片互连结构
CN103426863A (zh) * 2012-05-21 2013-12-04 国际商业机器公司 用于三维电路集成的过孔结构及其形成方法
US20170005000A1 (en) * 2015-07-01 2017-01-05 Imec Vzw Method for bonding and interconnecting integrated circuit devices
CN107305861A (zh) * 2016-04-25 2017-10-31 晟碟信息科技（上海）有限公司 半导体装置及其制造方法

Family Cites Families (74)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69429848T2 (de) 1993-11-01 2002-09-26 Matsushita Electric Ind Co Ltd Elektronische Anordnung und Verfahren zur Herstellung
KR960009074A (ko) 1994-08-29 1996-03-22 모리시다 요이치 반도체 장치 및 그 제조방법
US6097096A (en) 1997-07-11 2000-08-01 Advanced Micro Devices Metal attachment method and structure for attaching substrates at low temperatures
JP3532788B2 (ja) 1999-04-13 2004-05-31 唯知 須賀 半導体装置及びその製造方法
US6423640B1 (en) 2000-08-09 2002-07-23 Taiwan Semiconductor Manufacturing Co., Ltd. Headless CMP process for oxide planarization
US6887769B2 (en) 2002-02-06 2005-05-03 Intel Corporation Dielectric recess for wafer-to-wafer and die-to-die metal bonding and method of fabricating the same
US6762076B2 (en) 2002-02-20 2004-07-13 Intel Corporation Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices
US7105980B2 (en) 2002-07-03 2006-09-12 Sawtek, Inc. Saw filter device and method employing normal temperature bonding for producing desirable filter production and performance characteristics
JP4083502B2 (ja) 2002-08-19 2008-04-30 株式会社フジミインコーポレーテッド 研磨方法及びそれに用いられる研磨用組成物
US7023093B2 (en) 2002-10-24 2006-04-04 International Business Machines Corporation Very low effective dielectric constant interconnect Structures and methods for fabricating the same
US6962835B2 (en) 2003-02-07 2005-11-08 Ziptronix, Inc. Method for room temperature metal direct bonding
US6908027B2 (en) 2003-03-31 2005-06-21 Intel Corporation Complete device layer transfer without edge exclusion via direct wafer bonding and constrained bond-strengthening process
US7109092B2 (en) 2003-05-19 2006-09-19 Ziptronix, Inc. Method of room temperature covalent bonding
US6867073B1 (en) 2003-10-21 2005-03-15 Ziptronix, Inc. Single mask via method and device
US20060057945A1 (en) 2004-09-16 2006-03-16 Chia-Lin Hsu Chemical mechanical polishing process
US7193423B1 (en) 2005-12-12 2007-03-20 International Business Machines Corporation Wafer-to-wafer alignments
US7750488B2 (en) 2006-07-10 2010-07-06 Tezzaron Semiconductor, Inc. Method for bonding wafers to produce stacked integrated circuits
US7803693B2 (en) 2007-02-15 2010-09-28 John Trezza Bowed wafer hybridization compensation
US8349635B1 (en) 2008-05-20 2013-01-08 Silicon Laboratories Inc. Encapsulated MEMS device and method to form the same
US9893004B2 (en) 2011-07-27 2018-02-13 Broadpak Corporation Semiconductor interposer integration
US8476165B2 (en) 2009-04-01 2013-07-02 Tokyo Electron Limited Method for thinning a bonding wafer
US8482132B2 (en) 2009-10-08 2013-07-09 International Business Machines Corporation Pad bonding employing a self-aligned plated liner for adhesion enhancement
JP5517800B2 (ja) 2010-07-09 2014-06-11 キヤノン株式会社 固体撮像装置用の部材および固体撮像装置の製造方法
FR2966283B1 (fr) 2010-10-14 2012-11-30 Soi Tec Silicon On Insulator Tech Sa Procede pour realiser une structure de collage
US8377798B2 (en) 2010-11-10 2013-02-19 Taiwan Semiconductor Manufacturing Co., Ltd Method and structure for wafer to wafer bonding in semiconductor packaging
US8620164B2 (en) 2011-01-20 2013-12-31 Intel Corporation Hybrid III-V silicon laser formed by direct bonding
US8716105B2 (en) 2011-03-31 2014-05-06 Soitec Methods for bonding semiconductor structures involving annealing processes, and bonded semiconductor structures and intermediate structures formed using such methods
US8501537B2 (en) 2011-03-31 2013-08-06 Soitec Methods for bonding semiconductor structures involving annealing processes, and bonded semiconductor structures formed using such methods
WO2012161044A1 (ja) 2011-05-24 2012-11-29 ソニー株式会社 半導体装置
JP5982748B2 (ja) 2011-08-01 2016-08-31 ソニー株式会社 半導体装置、半導体装置の製造方法、および電子機器
US8697493B2 (en) 2011-07-18 2014-04-15 Soitec Bonding surfaces for direct bonding of semiconductor structures
US8441131B2 (en) 2011-09-12 2013-05-14 Globalfoundries Inc. Strain-compensating fill patterns for controlling semiconductor chip package interactions
CN103377911B (zh) 2012-04-16 2016-09-21 中国科学院微电子研究所 提高化学机械平坦化工艺均匀性的方法
US9142517B2 (en) 2012-06-05 2015-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid bonding mechanisms for semiconductor wafers
US8809123B2 (en) 2012-06-05 2014-08-19 Taiwan Semiconductor Manufacturing Company, Ltd. Three dimensional integrated circuit structures and hybrid bonding methods for semiconductor wafers
US20140175655A1 (en) 2012-12-22 2014-06-26 Industrial Technology Research Institute Chip bonding structure and manufacturing method thereof
US8946784B2 (en) 2013-02-18 2015-02-03 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for image sensor packaging
US8802538B1 (en) 2013-03-15 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for hybrid wafer bonding
US9443796B2 (en) 2013-03-15 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. Air trench in packages incorporating hybrid bonding
US9064937B2 (en) 2013-05-30 2015-06-23 International Business Machines Corporation Substrate bonding with diffusion barrier structures
US9929050B2 (en) 2013-07-16 2018-03-27 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming three-dimensional integrated circuit (3DIC) stacking structure
US9723716B2 (en) 2013-09-27 2017-08-01 Infineon Technologies Ag Contact pad structure, an electronic component, and a method for manufacturing a contact pad structure
US9257399B2 (en) 2013-10-17 2016-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. 3D integrated circuit and methods of forming the same
JP2015115446A (ja) 2013-12-11 2015-06-22 株式会社東芝 半導体装置の製造方法
US9437572B2 (en) 2013-12-18 2016-09-06 Taiwan Semiconductor Manufacturing Company, Ltd. Conductive pad structure for hybrid bonding and methods of forming same
US9299736B2 (en) 2014-03-28 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid bonding with uniform pattern density
US9230941B2 (en) 2014-03-28 2016-01-05 Taiwan Semiconductor Manufacturing Company, Ltd. Bonding structure for stacked semiconductor devices
US9472458B2 (en) 2014-06-04 2016-10-18 Semiconductor Components Industries, Llc Method of reducing residual contamination in singulated semiconductor die
KR102301573B1 (ko) * 2014-06-05 2021-09-10 삼성전자주식회사 반도체 장치
KR102275705B1 (ko) 2014-07-11 2021-07-09 삼성전자주식회사 웨이퍼 대 웨이퍼 접합 구조
US9536848B2 (en) 2014-10-16 2017-01-03 Globalfoundries Inc. Bond pad structure for low temperature flip chip bonding
US9394161B2 (en) 2014-11-14 2016-07-19 Taiwan Semiconductor Manufacturing Co., Ltd. MEMS and CMOS integration with low-temperature bonding
US9656852B2 (en) 2015-07-06 2017-05-23 Taiwan Semiconductor Manufacturing Company Ltd. CMOS-MEMS device structure, bonding mesa structure and associated method
US10075657B2 (en) 2015-07-21 2018-09-11 Fermi Research Alliance, Llc Edgeless large area camera system
US9728521B2 (en) 2015-07-23 2017-08-08 Taiwan Semiconductor Manufacturing Co., Ltd. Hybrid bond using a copper alloy for yield improvement
KR102379165B1 (ko) * 2015-08-17 2022-03-25 삼성전자주식회사 Tsv 구조를 구비한 집적회로 소자 및 그 제조 방법
US9559081B1 (en) 2015-08-21 2017-01-31 Apple Inc. Independent 3D stacking
US9953941B2 (en) 2015-08-25 2018-04-24 Invensas Bonding Technologies, Inc. Conductive barrier direct hybrid bonding
US9496239B1 (en) 2015-12-11 2016-11-15 International Business Machines Corporation Nitride-enriched oxide-to-oxide 3D wafer bonding
US9923011B2 (en) 2016-01-12 2018-03-20 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure with stacked semiconductor dies
US10026716B2 (en) 2016-04-15 2018-07-17 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC formation with dies bonded to formed RDLs
KR102505856B1 (ko) 2016-06-09 2023-03-03 삼성전자 주식회사 웨이퍼 대 웨이퍼 접합 구조체
US9941241B2 (en) 2016-06-30 2018-04-10 International Business Machines Corporation Method for wafer-wafer bonding
US10163750B2 (en) 2016-12-05 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure for heat dissipation
US10453832B2 (en) 2016-12-15 2019-10-22 Taiwan Semiconductor Manufacturing Co., Ltd. Seal ring structures and methods of forming same
EP3563411B1 (en) 2016-12-28 2021-04-14 Invensas Bonding Technologies, Inc. Method of processing a substrate on a temporary substrate
US20180182665A1 (en) 2016-12-28 2018-06-28 Invensas Bonding Technologies, Inc. Processed Substrate
US10431614B2 (en) 2017-02-01 2019-10-01 Semiconductor Components Industries, Llc Edge seals for semiconductor packages
JP6640780B2 (ja) 2017-03-22 2020-02-05 キオクシア株式会社 半導体装置の製造方法および半導体装置
US10269756B2 (en) 2017-04-21 2019-04-23 Invensas Bonding Technologies, Inc. Die processing
US10580823B2 (en) 2017-05-03 2020-03-03 United Microelectronics Corp. Wafer level packaging method
US10879212B2 (en) 2017-05-11 2020-12-29 Invensas Bonding Technologies, Inc. Processed stacked dies
US11251157B2 (en) 2017-11-01 2022-02-15 Taiwan Semiconductor Manufacturing Company, Ltd. Die stack structure with hybrid bonding structure and method of fabricating the same and package
US10811392B2 (en) * 2019-02-27 2020-10-20 Western Digital Technologies, Inc. TSV semiconductor device including two-dimensional shift

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101558483A (zh) * 2005-08-11 2009-10-14 齐普特洛尼克斯公司 三维ic方法和器件
CN101802990A (zh) * 2007-07-31 2010-08-11 泰塞拉公司 使用穿透硅通道的半导体封装方法
CN102150257A (zh) * 2008-09-11 2011-08-10 美光科技公司 堆叠式装置识别指派
CN102187458A (zh) * 2008-09-11 2011-09-14 美光科技公司 包含用于穿硅通孔的穿透结构的堆叠式裸片互连结构
CN101740484A (zh) * 2008-11-25 2010-06-16 台湾积体电路制造股份有限公司 形成穿透硅通孔的方法
US20110108972A1 (en) * 2009-11-12 2011-05-12 International Business Machines Corporation Integrated Circuit Die Stacks With Translationally Compatible Vias
CN102024782A (zh) * 2010-10-12 2011-04-20 北京大学 三维垂直互联结构及其制作方法
CN103426863A (zh) * 2012-05-21 2013-12-04 国际商业机器公司 用于三维电路集成的过孔结构及其形成方法
US20170005000A1 (en) * 2015-07-01 2017-01-05 Imec Vzw Method for bonding and interconnecting integrated circuit devices
CN107305861A (zh) * 2016-04-25 2017-10-31 晟碟信息科技（上海）有限公司 半导体装置及其制造方法

Also Published As

Publication number Publication date
CN112514059B (zh) 2024-05-24
US11171117B2 (en) 2021-11-09
US20220028835A1 (en) 2022-01-27
WO2019241367A1 (en) 2019-12-19
US20190378820A1 (en) 2019-12-12

Similar Documents

Publication Publication Date Title
CN112514059B (zh) 堆叠微电子部件的层间连接
CN112470270B (zh) Tsv上的偏移焊盘
US11837582B2 (en) Molded direct bonded and interconnected stack
US11735523B2 (en) Laterally unconfined structure
US20200035641A1 (en) Post cmp processing for hybrid bonding
EP3657538A1 (en) Semiconductor device, semiconductor package and method of manufacturing the same
CN112534574A (zh) Tsv之上的大金属焊盘
KR101729378B1 (ko) 반도체 디바이스 및 반도체 디바이스 제조 방법
CN108428679B (zh) 具有热导柱的集成电路封装
US20050224921A1 (en) Method for bonding wafers to produce stacked integrated circuits
US9190345B1 (en) Semiconductor devices and methods of manufacture thereof
TW201023299A (en) Method of forming stacked dies
US9159673B2 (en) Forming interconnect structures using pre-ink-printed sheets
US7700410B2 (en) Chip-in-slot interconnect for 3D chip stacks
US9905523B2 (en) Microelectronic assemblies formed using metal silicide, and methods of fabrication
WO2024021356A1 (zh) 高深宽比tsv电联通结构及其制造方法
TW202046417A (zh) 堆疊微電子構件的中間層連接
CN112385036A (zh) 模制的直接键合和互连的堆叠

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
CB02 Change of applicant information

Address after: California, USA

Applicant after: Insulation Semiconductor Bonding Technology Co.

Address before: California, USA

Applicant before: Evanss Adhesive Technologies

CB02 Change of applicant information
GR01 Patent grant
GR01 Patent grant