CN1959983A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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CN1959983A
CN1959983A CNA2006101431363A CN200610143136A CN1959983A CN 1959983 A CN1959983 A CN 1959983A CN A2006101431363 A CNA2006101431363 A CN A2006101431363A CN 200610143136 A CN200610143136 A CN 200610143136A CN 1959983 A CN1959983 A CN 1959983A
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C·W·科布格尔三世
M·C·哈基
D·V·霍拉克
古川俊治
S·J·霍尔梅斯
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International Business Machines Corp
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Abstract

本发明公开了一种制造三维集成电路芯片或晶片组件的方法，更具体地说，一种在将芯片定向成叠层之前在晶片上设置的芯片的处理。还公开了三维集成电路的制造，其中芯片密度可以很高并且在晶片仍是完整的并且通常为平面结构时进行处理。

Description

半导体器件及其制造方法
技术领域
本发明涉及三维集成电路芯片或晶片组件的制造工艺，更具体地说，涉及在将芯片定向成叠层之前设置在晶片上的芯片的工艺。此外，本发明还适合三维集成电路的制造，其中芯片的密度可以很高并且在晶片仍完整并且通常为平面结构时被处理。
背景技术
大体上，在半导体及相关技术中已公知形成三维或叠层集成电路的基本概念，其中广泛应用多芯片叠层的使用和制造以促使多种多样的技术，以及材料可以容易地在单系统中结合，目的是提供不能通过单一技术和材料结合的方式获得的功能。另外，可以利用连接不同芯片的最短引线或布线容易地获得在以多芯片叠层组装的芯片上提供的不同集成电路结构或阵列和模块的有利的和通用的组合，从而导致布线长度的缩短，同时减小在形成多芯片叠层时的整个封装区域。在互相结合并且接合的多个小尺寸芯片的组装中同样可以制造很大尺寸的芯片，从而增加使用该芯片叠层的电子器件的产量。在一些实例中，通过多芯片叠层的形成和在三维叠层形成排列中多个小芯片的互相接合获得的三维集成电路结构可以结合不同的技术。此技术的结合可以促使得到如粒子迁移绘图或三维传感器的优点。因此，在所谓的立方体形成中经常利用芯片叠层，例如那些由Irvine Sensors(Reg.TM)制造的，其中引线从接合芯片之间向外延伸到叠层边缘，以在芯片安装时提供到其的可到达性，例如在垂直芯片阵列中，在下面的衬底上。这在实现立方体与很少接触引线层叠后，通常在立方体边缘上需要特殊单芯片工艺，以及需要实现不寻常封装。
可以在面向上的方向上将小芯片布线接合到大芯片上。然后，此混合结合又布线接合到外面的载体或接合到特殊衬底上的C4(控制塌陷芯片连接)，其装备有凹进以接受通常在附装中存在的所谓的突出。因此，此基本明显的结合被限制在接合到相当大芯片的一个小的或几个很小尺寸的芯片，以便保留基础晶片表面区域的相当数量的部分或一定百分比，用于将后者连接到电子或半导体器件封装。这有效地限制了在多芯片叠层中形成或组装的芯片的相对尺寸和数量。
现有技术的讨论
虽然，在与此技术有关的当前技术状态中发展了各种三维芯片和晶片系统以及组装工艺，但是与通过本发明获得的广泛方面相比，这些技术仍受到各种限制和约束。
Suga的美国专利No.6,465,892 B1和美国专利No.6,465,892 B1的分案，美国专利No.6,472,293 B2，每一个都涉及用于叠层半导体器件的互连结构并且都公开了制造互连结构的方法，其中每个专利的基本概念都归于缩短布线长度的努力，通过叠加半导体衬底和通过固态接合技术将它们接合在一起。虽然这提供了芯片层叠，但是在制造工艺中没有利用平面晶片结构形成多芯片叠层，从而在形成和接合芯片为叠层前，要预先进行所有芯片的处理。
至于Fung等人的美国专利No.6,355,501 B1，其涉及三维芯片层叠组装，并且其转让给本申请的受让人，这属于三维叠层SOI(绝缘体上硅)结构的形成。然而，虽然此专利致力于具有互连的层叠超薄芯片的方法，用于使集成电路封装的操作速度的最大化，但是还没有公开在芯片层叠前，在晶片分离或切割成分立部件前，制造和处理所有设置在标准晶片上的芯片的工艺。
发明内容
因此，为了清楚并独特地改善现有技术，如当前技术所表现出的，本发明致力于提供这样的方法，其中在分离和形成或接合芯片叠加成多芯片叠层之前，在芯片排列在平坦平面晶片上的同时处理芯片时进行制造。
实际上，通过上面的芯片面向位于其下的芯片提供用于集成电路或半导体器件的布线的通路，以便粘合接合在一起并且由此进行通常的平面晶片的设计，接合，切割和处理，其中上部芯片始于SOI或类似的技术以便必要时容易进行减薄。此特殊的减薄处理有效地提供在芯片中的任何过孔具有合理的维度并且在晶片仍完整并且表面结构平整时建造或形成。这可以帮助在晶片的表面上提供超高的芯片密度，以便因此将处理芯片的产量最大化，并且结果增加了通过叠加形成多芯片叠层并将芯片接合在一起的产量。
因此本发明的一个目的是提供用于制造多芯片叠层的工艺，此工艺允许在芯片对准成多芯片叠层之前在芯片设置在晶片衬底上时处理芯片。
本发明的另一个目的是处理安放在晶片上的多个芯片，以便使从芯片形成的多芯片叠层的上部芯片延伸到下部芯片的布线的通路成为可能，以有助于平面晶片设计，接合，晶片切割和分离芯片的处理的利用。
附图说明
现在结合附图对根据本发明形成的多芯片叠层的优选实施例进行详细描述，其中：
图1示出了在根据本发明的多芯片叠层的制造中利用的第一基础半导体芯片(A)；
图2示出了适合与图1中示出的基础半导体芯片(A)接合的第二半导体芯片(B)；
图3示出了图1和2的半导体芯片A和B，根据本发明在多芯片叠层制造工艺期间进行的相互对准和接合的关系；
图4示出了图3的半导体芯片，其中进行了另外的工艺步骤；
图5示出了以在如图4所示的叠层关系制造接合芯片的顺序进行的另外的工艺步骤；
图6示出了另外的实施例，包括利用改进的半导体芯片C代替适合与基础半导体芯片(A)接合的芯片B；以及
图7示出了以根据本发明的相互对准和接合关系的图1和图6的半导体芯片A和C。
具体实施方式
详细参考附图，如图1所示，其提供了设置在衬底如平面晶片12上的第一基础半导体芯片10(标记为A)，并且提供了多个金属级14，虽然对于多级技术可以容易地提供附加的级和层，但是在此具体实施例中仅示出了两个。同样在基础半导体芯片10中提供如包括场效应晶体管(FET)栅极电极100和有源SOI区域102的有源器件。
此具体的芯片结构为晶片形式，并且包括可能被具体的技术所要求的用导电材料18填充的互连通路和过孔16。芯片安装在柄(handle)20上，在掩埋氧化物(“BOX”)和浅沟槽隔离(“STI”)层22下面构成处理层并且在其上永久保留。因此，芯片可以是块体，Si，SOI，SiGe，GaAs或技术上公知的任何合适的结造。
如在附图2中所示，提供第二芯片26(标记为B)，其可以由SOI或柄晶片28可以容易的从其上除去的这种类型的任何合适的材料构成。在柄晶片或层28的相对侧，向第二晶片26提供覆层(或多层)30。
如在图1的前述晶片A中，在芯片B中可以利用任何数目的金属级32，这依赖于技术的类型和集成电路要求的连接，虽然在此情况下，仅通过实例的方式示出了两个金属级32。同样，如在前述晶片A中，在基础半导体芯片26中提供的是如包括场效应晶体管(FET)栅极电极104和有源SOI区域106的有源器件。为了确认是好的小片(die)，使芯片26经受与最终结果相关的测试，并且随后通过覆层或膜30用介质覆盖晶片，并且印刷并蚀刻过孔34，其穿过覆层或膜30，并且穿过级间介质(ILD)19和BOX(掩埋氧化物层)22，在柄晶片或层28上或内停止。这些过孔34没有被填充，并且在后面用来接触芯片A。
在可能的频繁次数内，如果需要，可以进行从在图2中的其底部到芯片B的任何电接触(未示出)。使用由完全透过BOX和STI层22到达柄晶片28的接触特征构成的形状36，如在附图2中所示，以完成此特殊的制造步骤。其后，切割芯片或多个芯片B并且收集为被接受的确认的小片。
如在芯片10和26即在附图3的芯片A和B的组装中所示，翻转芯片B并且向晶片或芯片A和/或芯片B的面对表面42，44上提供粘合剂40。接受芯片26(即芯片B)翻转和对准并且通过粘合剂40接合到先前测试过并接受的晶片或芯片10(即芯片A)上。接合粘合剂可以由如顺丁烯二酐聚合物构成，其通过使用枝状胺粘结料激活，并且建议，通过粘合剂形成的芯片间的粘合剂越薄越好以便不会导致任何除气现象或芯片10，26(即芯片A和B)添加粘合剂后叠层的体积的任何明显的改变。如果接合的表面足够平坦和干净，能够得到5到10nm的最终厚度，从而减小了最小厚度要求的粘合剂的数量。
如在附图4中所示，从芯片26(即芯片B)除去包括柄层28的晶片衬底，并且如果柄层28由硅构成，可以通过KOH溶液进行此除去工艺。类似地，如果芯片B中的形状36接触特征同样由硅构成，那么使用的KOH将蚀刻掉此材料，但是这并不是需要或必须的，除非用与填充过孔34的材料相同的材料回填它们。柄晶片或层28的除去暴露了已经在芯片26中形成的未被填充的过孔34。其后，进行蚀刻，利用仍旧开口的过孔34作为掩膜以便除去在过孔34下并且在合适金属衬垫14上存在的覆层或膜30以及粘合剂40；从而，蚀刻在金属衬垫14上停止。
参考附图5，随后填充过孔34，作为任何穿过掩埋氧化物层(BOX)与芯片26(形状36)接触，如果它们被打开。另外，可以通过沉积并深蚀刻厚衬里材料并且随后在其上电镀执行此工艺。对提供电导率，用铜填充是有利的；然而，铜填充要求衬里相对较厚，因为铜会透过芯片26的BOX层，并且因此致使其易受金属污染。可以使用ALD工艺用于沉积用作塞栓或籽晶的不同材料的目的。然后从叠层(双层芯片10和26)的上表面或顶部除去任何金属。如果上表面足够平坦，可以使用CMP以完成此上表面的清理。为了保留普通的多个或平坦的上表面，可以将虚芯片B附装到坏芯片A位置，这可以确定。此清理步骤优选使用干蚀刻。
附图5示出了完成了接合芯片A(芯片10)和芯片B(芯片26)，通过填充过孔34与芯片A连接并且通过填充接触形状36与芯片B连接。
在附图6和7中示出的是一种设计，其中芯片C(指芯片50)顶部与基础半导体芯片A直接接触而不需要过孔34的上部连接到接触形状36。在此实施例中，如图6所示，构造过孔34以便其与芯片50的布线形状52交迭，其要求与基础芯片10连接。因为过孔34的蚀刻被布线形状52阻挡，过孔的剖面上部比底部宽。
然后翻转芯片50，并且接合到基础芯片10上，并且从芯片50除去柄衬底并且蚀刻过孔34的底部，如上所述。然后加衬并填充过孔34，并且除去过多的金属，类似于在附图5示出的结构中执行的。在附图7中示出了此工艺的结果。作为在接合前翻转芯片50的结果，过孔34的较宽上部分移到了底部，过孔34的保形填充可以导致填充空隙62。
芯片层叠工艺可以重复向由来自图5的芯片10和26(A和B)形成的叠层或由来自图7的芯片50和26形成的叠层的顶部附装附加的芯片。在这些附加芯片中需要过孔以贯穿每个前级芯片的过孔34或接触形状36。
可以通过连接到在叠层顶部芯片的上表面上暴露的填充过孔进行叠层芯片的外部接合并且目前可以仅包括小的横截面过孔末端。然后另外的步骤将向表面电镀衬垫，其将是C4或布线接合连接的合适材料。然而，除了电镀或使用光刻和蚀刻以形成衬垫，也可能制造仅包括大衬垫和过孔的芯片，并且随后通过使用用于两个有源电路芯片描述的方法类似的方法，将此仅有衬垫的芯片附装到上表面上。
在本发明的可选方面中，可以在芯片26上的过孔34的印刷和/或蚀刻前施加提供芯片10，26和/或50的接合的粘合剂，并且随后用过孔掩蔽构图。制造中的此顺序可以帮助避免用粘合剂填充过孔，但是在使用抗蚀剂和/或显影剂时有限制。
另外顶部芯片(如示出的芯片26)可以由无源部件构成，其有时会在封装兼容性，超导体，大电容器等等中需求。另外，在穿过BOX接触形状36到芯片26中使用多晶硅塞栓的情况下，可以通过在沉积多晶硅前沉积薄氧化物膜或覆盖蚀刻形状36孔来保护多晶硅填充不受柄晶片除去蚀刻。其后，仅需要蚀刻掉薄氧化物以暴露多晶硅接着除去柄层28。
为了提供满意的制造，芯片10，26和50(A，B和C)必须是充分平整的结构并且粘合剂接合材料足够厚以防止在接合期间在粘合剂中形成任何空隙。使用改进的光刻曝光或设备，可以很好地对准芯片10和26(以及50)，小于25nm。通过观察其前侧确定芯片10的位置，并可以通过利用相同的或不同的光学仪器来检测或映射芯片26的前侧。可以使用如用于步进台的合适的精密机械将芯片26移到合适的位置并且然后下压到芯片10上。(这还适用于芯片50)。覆盖膜30的材料可以选自，如氮化硅的候选材料，以便在接合后清理过孔34的底部的其蚀刻不减薄芯片26的BOX和STI层22。另外，除非对最后的衬垫有其它要求，在所有的芯片仍为晶片形式时进行所有的光刻工艺，而不是在分立的芯片或芯片叠层上进行，因此除了芯片26与芯片10(或芯片50)的对准和粘合剂接合材料的施加之外，很少要求特殊的工艺。
最后，为了扩大过孔34的上端或顶部，可能要过多电镀过孔金属，为了制造突出部分用于在没有要求任何叠层上的光刻情况下提高与金属层的接触。
根据前面的叙述，下面的内容变得容易和清楚，即本发明以高效和独特模式改善了提供多芯片叠层或晶片的制造工艺，提供了简化的制造顺序并且允许在晶片上设置更高密度的不同技术的芯片，并且兼顾形成三维集成电路结构的叠层关系。
虽然很明显这里公开的本发明可以很好地用来实现上述目标，但是应该认识到，本领域的技术人员可以进行许多修改和实施例，并且旨在所附权利要求覆盖落入本发明的精神和范围内的所有这样的修改和实施例。

Claims (24)

1.一种电子器件，包括以形成多芯片叠层的重叠粘合关系的至少两个集成电路芯片或元件；包括：
第一所述集成电路芯片或元件，具有包括多个介质和金属层的多层结构，由覆层构成第一表面并由柄层构成相反侧表面；以及
第二所述集成电路芯片或元件，具有包括多个介质和金属层的多层结构，由覆层构成第一表面，所述第二集成电路芯片或元件处于颠倒位置并且以与所述第一集成电路芯片或元件的所述覆层表面接合的方式粘合固定，所述第二集成电路芯片或元件具有导体填充过孔，所述过孔将所述第一集成电路芯片或元件中的导体层连接到所述多芯片叠层的上表面，并且将所述第二集成电路芯片或元件中的导体层连接到所述多芯片叠层的上表面。
2.根据权利要求1的多芯片叠层，其中在衬底上形成所述第二集成电路芯片或元件，所述衬底在所述两个芯片或元件粘合固定之后被除去。
3.根据权利要求1的多芯片叠层，其中所述第一芯片或元件由多个粘合固定的多芯片集成电路叠层构成。
4.根据权利要求1的半导体器件，其中所述第二半导体芯片或元件包括至少一个过孔，从所述第一芯片或元件延伸到上表面，与所述第二集成电路芯片或元件中的导体层相交，以便提供用于在所述至少两个芯片或元件的所述金属层之间的电连接的通路。
5.根据权利要求1的半导体器件，其中通过插入粘合剂层粘附所述第一和第二半导体芯片或元件。
6.根据权利要求5的半导体器件，其中所述粘合剂层包括通过枝状胺粘结料激活的由顺丁烯二酐聚合物构成的薄粘合剂。
7.根据权利要求1的半导体器件，其中所述柄层由硅构成。
8.根据权利要求4的半导体器件，其中用导电材料填充在所述第二半导体芯片或元件中形成的所述至少一个过孔，以便提供从外电路到所述第一和第二半导体芯片或元件的电子部件的电连接，并且在所述第一和第二半导体芯片或元件的电子部件之间提供电连接。
9.根据权利要求1的半导体器件，其中用于所述第一半导体芯片或元件的所述衬底选自Si，SOI，SiGe，GaAs等的材料。
10.根据权利要求1的半导体器件，其中至少将第三所述半导体芯片或元件选择性地粘合接合到所述第二半导体芯片或元件，以便形成具有另外的电接触并与其连接的多芯片叠层。
11.根据权利要求1的半导体器件，其中所述第二半导体芯片或元件包括SOI层。
12.一种提供电子器件的方法，所述电子器件包括以形成多芯片叠层的重叠粘合关系的至少两个集成电路芯片或元件；所述方法包括：
提供第一所述集成电路芯片或元件，具有包括多个介质和金属层的多层结构，包括形成由覆层构成的第一表面和由柄层构成的相反侧表面；以及
提供第二所述集成电路芯片或元件，具有包括多个介质和金属层的多层结构，包括形成由覆层构成的第一表面和由柄层构成的相反侧表面，所述第二集成电路芯片或元件以颠倒位置设置并且以与所述第一集成电路芯片或元件的所述覆层表面接合的方式粘合固定，所述第二集成电路芯片或元件形成有用导体材料填充的过孔，所述过孔将所述第一集成电路芯片或元件中的导体层连接到所述多芯片叠层的上表面，并且将所述第二集成电路芯片或元件中的导体层连接到所述多芯片叠层的上表面。
13.根据权利要求12的方法，其中在衬底上形成所述第二集成电路芯片或元件，所述衬底在所述两个芯片或元件粘合固定之后被除去。
14.根据权利要求12的方法，其中所述第一芯片或元件由多个粘合固定的多芯片集成电路叠层构成。
15.根据权利要求12的方法，其中所述第二半导体芯片或元件具有在其中形成的至少一个过孔，从所述第一芯片或元件延伸到上表面，以便提供从外电路到所述第一和第二半导体芯片或元件的电子部件的电连接，并且在所述至少两个芯片或元件的所述金属层之间提供电连接，所述过孔使用常规半导体技术在所述第二半导体芯片或元件仍为晶片形式时限定。
16.根据权利要求12的方法，其中通过插入粘合剂层粘附所述第一和第二半导体芯片或元件。
17.根据权利要求16的方法，其中所述粘合剂层包括通过枝状胺粘结料激活的由顺丁烯二酐聚合物构成的薄粘合剂。
18.根据权利要求15的方法，其中使用未填充的所述至少一个过孔作为蚀刻掩膜从所述至少一个过孔的底部蚀刻所述粘合剂层。
19.根据权利要求12的方法，其中所述柄层由硅构成。
20.根据权利要求15的方法，其中用导电材料填充在所述第二半导体芯片或元件中形成的所述至少一个过孔，以便提供所述第一和第二半导体芯片或元件的电子部件之间的电连接。
21.根据权利要求12的方法，其中用于所述第一半导体芯片或元件的所述衬底选自Si，SOI，SiGe，GaAs等的材料。
22.根据权利要求12的方法，其中将具有重复所述第一半导体芯片的层的至少第三所述半导体芯片或元件选择性地粘合接合到所述第二半导体芯片或元件，以便形成具有另外的电接触并与其连接的多芯片叠层。
23.根据权利要求12的方法，其中所述第二半导体芯片或元件包括SOI层。
24.根据权利要求12的方法，其中在从大尺寸半导体晶片切割之前处理并粘合层叠所述半导体芯片或元件。
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