CN104716087B - 用于堆叠的cmos器件的连接技术 - Google Patents

用于堆叠的cmos器件的连接技术 Download PDF

Info

Publication number
CN104716087B
CN104716087B CN201410765376.1A CN201410765376A CN104716087B CN 104716087 B CN104716087 B CN 104716087B CN 201410765376 A CN201410765376 A CN 201410765376A CN 104716087 B CN104716087 B CN 104716087B
Authority
CN
China
Prior art keywords
substrate
layer
conductive layer
integrated circuit
level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201410765376.1A
Other languages
English (en)
Other versions
CN104716087A (zh
Inventor
曾祥仁
陈威宇
江庭玮
田丽钧
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN104716087A publication Critical patent/CN104716087A/zh
Application granted granted Critical
Publication of CN104716087B publication Critical patent/CN104716087B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H01L21/743—Making of internal connections, substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8221—Three dimensional integrated circuits stacked in different levels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/074—Stacked arrangements of non-apertured devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11803—Masterslice integrated circuits using field effect technology
    • H01L27/11807—CMOS gate arrays
    • H01L2027/11883—Levels of metallisation
    • H01L2027/11887—Three levels of metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06548—Conductive via connections through the substrate, container, or encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
    • H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53242—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a noble metal, e.g. gold
    • H01L23/53252—Additional layers associated with noble-metal layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
    • H01L23/53266—Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/207—Diameter ranges

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

一种堆叠的集成电路包括垂直连接在一起的多层。多层水平连接结构被制造于层的衬底内。从衬底之上观察时水平连接结构的层具有不同的图案。本发明还涉及用于堆叠的CMOS器件的连接技术。

Description

用于堆叠的CMOS器件的连接技术
技术领域
本发明涉及用于堆叠的CMOS器件的连接技术。
背景技术
堆叠CMOS芯片是一种具有多个垂直堆叠且共享一个封装件的器件层的集成电路。堆叠CMOS芯片将芯片结构延伸至三维并且增加可以“挤压”到给定的足迹(footprint)内的CMOS器件的数目。
发明内容
为了解决现有技术中的问题，本发明提供了一种半导体集成电路(IC)，包括：第一器件层，具有位于第一衬底内的第一层间水平互连结构，以及第二器件层，通过所述第一层间水平互连结构电连接至所述第一器件层，其中，所述第一层间水平互连结构包括具有不同图案的第一导电层和第二导电层。
在上述IC中，其中，所述第一层间水平互连结构包括：设置在所述第一衬底中并且电连接至所述第二器件层的器件的第一垂直连接元件，以及设置在所述第一衬底中、所述第一垂直连接元件之上的第一水平层，其中，所述第一水平层通过所述第一垂直连接元件电连接至所述第二器件层的器件。
在上述IC中，其中，所述第一层间水平互连结构包括：设置在所述第一衬底中并且电连接至所述第二器件层的器件的第一垂直连接元件，以及设置在所述第一衬底中、所述第一垂直连接元件之上的第一水平层，其中，所述第一水平层通过所述第一垂直连接元件电连接至所述第二器件层的器件；其中，所述第二器件层还包括布置在所述第二器件层的器件上方的电互连结构，所述电互连结构具有与所述第一垂直连接元件连接的上表面。
在上述IC中，其中，所述第一层间水平互连结构包括：设置在所述第一衬底中并且电连接至所述第二器件层的器件的第一垂直连接元件，设置在所述第一衬底中、所述第一垂直连接元件之上的第一水平层，以及设置在第一衬底中、所述第一水平层之上并且通过所述第一垂直连接元件和所述第一水平层电连接至所述第一器件的第二水平层。
在上述IC中，其中，所述第一层间水平互连结构包括：设置在所述第一衬底中并且电连接至所述第二器件层的器件的第一垂直连接元件，设置在所述第一衬底中、所述第一垂直连接元件之上的第一水平层，以及设置在第一衬底中、所述第一水平层之上并且通过所述第一垂直连接元件和所述第一水平层电连接至所述第一器件的第二水平层；还包括：设置在所述第一衬底中并且将所述第一水平层电连接至所述第二水平层的第二垂直连接元件。
在上述IC中，其中，其中，所述第一层间水平互连结构还包括：位于所述第一衬底中并且与所述第二导电层平行或者垂直布置的第三导电层。
在上述IC中，其中，还包括通过第二层间水平互连结构与所述第一器件层电连接的第三器件层。
在上述IC中，其中，所述第一器件层在两侧上都具有器件。
根据本发明的另一个方面，提供了一种集成电路，包括：第一衬底，包括多个第一器件，以及第一水平互连结构，设置在所述第一衬底中，其中，所述第一水平互连结构包括从所述第一衬底之上观察时具有不同图案的第一导电层和第二导电层。
在上述集成电路中，还包括第二衬底，所述第二衬底包括多个第二器件，所述第一衬底和所述第二衬底彼此电连接，因此所述第二衬底位于所述第一衬底下方，其中，所述第一水平互连结构将一个或者多个所述多个第一器件电连接至一个或者多个所述多个第二器件。
在上述集成电路中，还包括第二衬底，所述第二衬底包括多个第二器件，所述第一衬底和所述第二衬底彼此电连接，因此所述第二衬底位于所述第一衬底下方，其中，所述第一水平互连结构将一个或者多个所述多个第一器件电连接至一个或者多个所述多个第二器件；其中，将所述第一衬底沉积、喷涂、淋涂、旋涂或者接合至所述第二衬底。
在上述集成电路中，还包括第二衬底，所述第二衬底包括多个第二器件，所述第一衬底和所述第二衬底彼此电连接，因此所述第二衬底位于所述第一衬底下方，其中，所述第一水平互连结构将一个或者多个所述多个第一器件电连接至一个或者多个所述多个第二器件；其中，将所述第一衬底沉积、喷涂、淋涂、旋涂或者接合至所述第二衬底；还包括：第三衬底，包括堆叠至所述第一衬底上的多个第三器件，以及第二水平连接结构，位于所述第三衬底内。
在上述集成电路中，还包括第二衬底，所述第二衬底包括位于所述第一衬底下方的多个第二器件，其中，上面具有器件的所述第一衬底的第一面面向上面具有器件的所述第二衬底的第二面。
在上述集成电路中，其中，所述第一水平互连结构是铜、银、钨或者铝。
在上述集成电路中，其中，所述第一水平互连结构包括：Ta、Ti、TaN、TiW、TiWN或者TiN阻挡层；以及围绕所述阻挡层的介电层。
在上述集成电路中，其中，所述第一水平互连结构包括：Ta、Ti、TaN、TiW、TiWN或者TiN阻挡层；以及围绕所述阻挡层的介电层；其中，所述第一水平连接结构和所述第二水平连接结构具有相同或者不同数量的导电层或者具有相同或者不同图案的导电层。
根据本发明的又一个方面，提供了一种制造堆叠CMOS器件的方法，包括：形成具有第一衬底的包括多个第一器件的第一器件层，在所述第一器件层上施加第二衬底，在所述第二衬底中形成第一导电层，在所述第二衬底中、在所述第一导电层上方形成第二导电层，以及在所述第二衬底上形成多个第二器件，所述多个第二器件通过所述第二衬底中的所述第一导电层和所述第二导电层电连接至所述多个第一器件。
在上述方法中，还包括：在所述第二衬底中形成垂直导电连接件以将所述第一导电层电连接至所述第二导电层。
在上述方法中，还包括：在所述第二衬底中形成垂直导电连接件以将所述第一导电层电连接至所述第二导电层；其中，所述垂直导电连接件从之上观察时具有落入所述第一导电层的外边缘内的正方形状周界或者圆形周界。
在上述方法中，其中，所述第一导电层是水平连接结构，并且其中，所述第二导电层是与所述第一导电层垂直的水平连接结构。
附图说明
图1根据一些实施例示出了堆叠CMOS器件的透视截面图。
图2根据一些可选实施例示出了堆叠CMOS器件的透视截面图。
图3和图4示出了水平连接结构的三步结构和水平连接结构的四步结构的透视截面图。
图5示出了用于连接堆叠CMOS器件的方法的一些实施例的流程图。
图6a至图6e中示出了用于连接堆叠CMOS器件的方法的一些实施例的透视截面图。
具体实施方式
此处的描述是参考附图，其中类似的附图标记通常用于指代相同的元件，并且其中各种结构不一定按比例绘制。在以下描述中，出于解释的目的，阐述了许多特定细节以便于理解。应该理解的是，附图的细节并不意在限制本公开，而是非限制性的实施例。然而，例如，其对于本领域的普通技术人员可能是显而易见，在此描述的一个或多个方面可以以这些具体细节的较轻程度实施。在其他实例中，公知的结构和器件以框图的形式示出以便于理解。
相对于其中多个芯片布置在分离的水平间隔的封装件中的封装方案，堆叠CMOS器件(其包括在单个封装件中彼此垂直地“堆叠”的多个芯片)在产品内布置时缩小电路的横向足迹。然而，在一些应用中堆叠CMOS器件的垂直尺寸可能变成问题。例如，对于诸如手机或便携式娱乐单元的超薄装置，堆叠CMOS芯片可能过厚。此外，形成不同的垂直器件层之间的电连接需要相应的器件层上的相应接触点的对准，这限制了结构设计中的灵活性。因此，在根据一些实施例的堆叠半导体集成电路中，代替仅由垂直的晶圆间通孔连接多个层，在单独的器件层的衬底内制造多层的水平连接结构。从衬底之上观察，多层水平连接结构的各个层具有不同的图案。相对于传统的方法，具有多层水平连接结构的堆叠CMOS器件提供若干优点。例如，不同层的电接触点的位置是灵活的，用于电路径层的金属使用降低，以及电路径层的数目和/或厚度减小，其趋向于“减薄”芯片厚度。功耗也降低了。
图1根据一些实施例示出了堆叠CMOS器件100的透视截面图。堆叠CMOS器件100包括多个器件层，诸如第一器件层102和第二器件层116。第一器件层102包括第一衬底104和多个第一器件106。第二器件层116包括第二衬底118和多个第二器件120。第一层间水平互连结构108至少部分地形成在第一衬底104内。第一层间水平结构108将第一衬底104上的一个或多个器件(诸如器件106)电连接至第二衬底118上的一个或多个器件(诸如器件120)。第一层间水平互连结构108可以包括当从第一衬底之上观察时具有不同图案的多个导电层，诸如金属层。
第一层间水平结构108包括第一导电层110，其在本实例中采用垂直连接元件的形式。第一导电层110连接至第二导电层112，在本实例中其采用第一水平层的形式。在本实例中采用第一水平层的形式的第二导电层112设置在第一垂直连接元件110之上，并连接至多个第一器件106的器件或第一器件层102上的其他接触路径，例如，电源、接地或信号引脚。第二导电层112通过第一垂直连接元件110电连接至第二器件层116的器件。第一导电层110将第二导电层112(并且因此器件106)连接至第二器件层116上的电互连结构115。电互连结构115具有多个金属层，诸如113和114。这些金属层113和114布置在第一衬底104的背侧下方并连接至第二器件层116的器件120。电互连结构115也可连接到堆叠在第一器件层102下方的第二器件层116的其他接触点。电互连结构115既可以形成在第一层102和第二层116之间的介电层中或可连接至第二层116内。
第一衬底104上的多个第一器件106和第二衬底118上的多个第二器件120可以是二维结构(例如，平面MOSFET)或三维结构(例如，绝缘体上硅(SOI)器件或FinFET器件)。第一衬底104中的第一层间水平互连结构108可以是具有Ta、Ti、TaN、TiW、TiWN或者TiN阻挡物以防止金属扩散的铜、银、钨或铝。围绕阻挡层形成介电层以便电隔离。第一衬底104可以是体硅或介电材料上的外延硅。为了进一步减少金属材料，减少层，或降低电互连结构115的复杂性，第一器件层102可以在两侧具有器件。第一器件层102也可以相对于图1中所示“翻转”以便具有多个第一器件106的第一衬底104的顶侧靠近具有多个第二器件120的第二衬底118的顶侧。通过这种方式，多个第一器件106和多个第二器件120之间的电连接变得更加灵活。第一器件层102可通过沉积、喷涂、淋涂、或旋涂形成在第二器件层116上。第一器件层102也可以接合至第二器件层116。
因此，图1根据一些实施例示出了具有由多层层间水平互连结构108连接的两个器件层(例如，102、116)的堆叠CMOS器件100的实例。这种结构的一些优点包括改进布局和布线的灵活性以及减少金属使用，并进一步减少电路的面积和功耗。
图2根据一些可选实施例示出了堆叠CMOS器件200的透视截面图。堆叠CMOS器件200示出了具有第三衬底228和多个第三器件(例如，232)的第三器件层226可以堆叠在与图1中的102和116类似的第一器件层202和第二器件层216上的公开的示例性实施例。更多层可堆叠至第三器件层226上。第三衬底228内的第二水平连接结构230包括三层220、222和224并且电连接第一器件层202和第三器件层226，其详细的示例透视截面图显示在图3中。值得注意的是，具有第一水平连接结构的第一衬底204和具有第二水平连接结构的第三衬底228可具有相似的或不同的结构。水平连接结构可以具有相同或不同数量的导电层。导电层的图案也可以是不同的。因此，图2根据一些可选实施例示出了具有由多层层间水平互连结构连接的两个以上的器件层的另一示例性半导体集成电路。
图3示出水平连接结构的示例性三层结构的透视截面图。水平连接结构可用作图2中的第一水平连接结构208或第二水平连接结构230。在实例中，第一导电层320是电连接至下面的器件层的器件的第一垂直连接元件。第二导电层322是设置在第一垂直连接元件320之上的第一水平层并且第三导电层324是设置在第一水平层322之上并通过第一导电层320和第二导电层322电连接至其上的器件层326的衬底304上的器件的第二水平层。第一导电层320的至少一个部分的位置水平移动至第二导电层322或第三导电层324的位置。第一导电层320通过第二导电层322和第三导电层324连接衬底304的另一侧上的不与第一导电层320的位置垂直对准的接触点，诸如326和328。在示出的例子中是垂直连接元件的第一导电层320从上方观察可以具有正方形或圆形的周界并且可以落入第二导电层的边缘内。在一些实施例中，320沿Z方向形成，322沿Y方向形成，324沿X方向形成。在一些实施例中，320、322、324在各自的X，Y，Z方向上彼此垂直。在一些实施例中，304包括任意数量的导电层。在一些实施例中，304中的导电层中的任何两个导电层彼此平行或彼此垂直。
图4示出了包括额外的第四导电层的四层水平连接结构400的透视截面图。四层水平连接结构400可以用作图2中的第一水平连接结构208或第二水平连接结构230。在图4的实例中，第一导电层420是在z方向上延伸的第一垂直连接元件并且其电连接至下面的器件层的器件(未示出)。第二导电层422是设置在第一垂直连接元件420之上且在y方向上延伸的第一水平层。第三导电层423是将第二导电层422连接到第四导电层424的第二垂直连接元件。第四导电层424是在x方向上延伸并且设置在第二垂直连接元件423之上的第二水平层。第一导电层420通过第二导电层422、第三导电层423、以及第四导电层424电连接到器件层426的衬底404上的器件。图3和图4的结构可以应用至公开的堆叠CMOS器件的任何上层级的层(例如，100的层102和200的层202或226)。
图5根据一些实施例示出了用于连接堆叠CMOS层的方法的一些实施例的流程图。虽然公开的方法(例如，图5的方法500)在下面示出并描述为一系列动作或事件，应该理解，这些动作或事件的所示顺序不应以限制性的意义解释。例如，一些动作可以按不同的顺序和/或与除了本文示出和/或描述的那些之外的其他动作或事件同时发生。此外，并非所有示出的动作都需要用于实施本文描述的一个或多个方面或实施例。此外，本文描述的一个或多个动作可以在一个或者多个单独的动作和/或阶段中实施。
在502，形成包括多个第一器件的具有第一衬底的第一器件层。
在504，在第一器件层上施加第二衬底。
在506，在第二衬底中形成电连接至第一衬底上的器件的第一导电层。
在508，在第二衬底中形成第二导电层。
在510，在第二衬底上形成多个第二器件和电连接件。
现参照如图6a至图6e所示的一系列截面图来描述图5的方法的一个实例。虽然结合方法500描述图6a至图6e，但是应当理解，在图6a至图6e中公开的结构不限于这种方法，而是可以独立作为结构。
在图6a中，形成具有第一衬底618和多个第一器件的第一器件层602。将具有多个金属层的电路径615形成到介电层630内的第一衬底上。多个金属层可以是例如铜、银、钨或铝。
在图6b中，在第一器件层602上施加第二衬底604。第二衬底可以通过沉积形成，举例来说诸如外延沉积，或者可接合至第二器件层116。例如，在一些实施例中，第一器件层可对应于第一体硅晶圆，以及第二器件层可对应于第二体硅晶圆，其中，第一晶圆具有结合到第二体硅晶圆的顶侧的背侧(或顶侧)。
在图6c中，在已经将第二衬底施加至第一衬底之后，在第二衬底中形成第一导电层610。第一导电层610电连接至第一衬底618上的器件。例如，第一导电层610可以是具有用于防止金属扩散的Ta、Ti、TaN、TiW、TiWN或者TiN阻挡物的铜、银、钨或铝。介电层(未示出)围绕阻挡层形成以便电隔离。
在图6d中，在第二衬底604中形成第二导电层612。例如，第二导电层612可以是具有用于防止金属扩散的Ta、Ti、TaN、TiW、TiWN或者TiN阻挡物的铜、银、钨或铝，并且还形成围绕阻挡层的介电层以便电隔离。
在图6e中，在第二衬底上形成多个第二器件和电连接件。第二衬底上的多个第二器件的一个或者多个电连接至第一衬底上的多个第一器件的一个或多个。
因此，一些实施例涉及半导体集成电路(IC)。该半导体集成电路包括具有位于第一衬底内的第一层间水平互连结构的第一器件层和通过第一层间水平互连结构电连接至第一器件层的第二器件层。第一层间水平互连结构包括具有不同图案的第一导电层和第二导电层。
其他实施例涉及集成电路。该集成电路包括第一衬底，第一衬底包括在第一衬底中设置的多个第一器件和第一水平互连结构。该集成电路还包括第二衬底，第二衬底包括多个第二器件，第一和第二衬底电连接至彼此，因此，第二衬底位于第一衬底下方并且第一水平互连结构将多个第一器件中的一个或者多个电连接至多个第二器件中的一个或者多个。第一水平互连结构包括从第一衬底之上观察时具有不同图案的第一导电层和第二导电层。
又一实施例涉及一种制造堆叠的CMOS器件的方法。在该方法中，形成具有第一衬底的包括多个第一器件的第一器件层。在第一器件层上施加第二衬底。在第二衬底中形成电连接至第一衬底上的器件的第一导电层。然后在第二衬底填充第二导电层。最后，在第二衬底上形成多个第二器件和电连接件。
应当理解，虽然讨论本文描述的方法的各个方面时在整个本文本中引用示例性结构(例如，在讨论图5中列举的方法时，图6a至图6e中显示的结构)，那些结构不受到显示的相应结构的限制。而是，考虑方法(以及结构)独立于彼此并且能够单独存在并且在不涉及附图中示出的任何特定方面的情况下实践。另外本文描述的层可以以任何合适的方式形成，诸如用旋涂、溅射、生长和/或沉积技术等。
基于阅读和/或理解说明书和所附附图本领域技术人员可以想到等效的改变和/或修改。本文的公开内容包括所有这样的修改和变更，并且一般不旨在由此限制。例如，尽管本文提供的附图示出和描述为具有特定的掺杂类型，如本领域普通技术人员所理解的，应该理解可以利用可选的掺杂类型。
另外，虽然已经关于若干实施方式的仅仅其中之一公开特定的特征或者方面，这种特征或者方面可以与可能需要的其他实施方式的一个或者多个其他特征和/或方面组合。此外，就本文使用的术语“包括”，“具有”，“有”，“带有”，和/或其变体而言，这些术语旨在是包含性的意义-类似“包括”。另外，“示例性”仅意味着表示一实例，而不是最好的。也可以理解，为了简单和便于理解，本文描述的部件、层和/或元件示出为相对于其他的部件、层和/或元件具有特定的尺寸和/或方向，并且实际尺寸和/或方向可以与本文示出的基本上不同。

Claims (20)

1.一种半导体集成电路(IC)，包括：
第一器件层，具有位于第一衬底内的第一层间水平互连结构，其中所述第一器件层的器件位于所述第一衬底上，以及
第二器件层，通过所述第一层间水平互连结构电连接至所述第一器件层的器件，
其中，所述第一层间水平互连结构包括具有不同图案的第一导电层和第二导电层。
2.根据权利要求1所述的半导体集成电路，其中，所述第一层间水平互连结构包括：
设置在所述第一衬底中并且电连接至所述第二器件层的器件的第一垂直连接元件，以及
设置在所述第一衬底中、所述第一垂直连接元件之上的第一水平层，
其中，所述第一水平层通过所述第一垂直连接元件电连接至所述第二器件层的器件。
3.根据权利要求2所述的半导体集成电路，其中，所述第二器件层还包括布置在所述第二器件层的器件上方的电互连结构，所述电互连结构具有与所述第一垂直连接元件连接的上表面。
4.根据权利要求1所述的半导体集成电路，其中，所述第一层间水平互连结构包括：
设置在所述第一衬底中并且电连接至所述第二器件层的器件的第一垂直连接元件，
设置在所述第一衬底中、所述第一垂直连接元件之上的第一水平层，以及
设置在第一衬底中、所述第一水平层之上并且通过所述第一垂直连接元件和所述第一水平层电连接至所述第一器件的第二水平层。
5.根据权利要求4所述的半导体集成电路，还包括：设置在所述第一衬底中并且将所述第一水平层电连接至所述第二水平层的第二垂直连接元件。
6.根据权利要求1所述的半导体集成电路，其中，所述第一层间水平互连结构还包括：位于所述第一衬底中并且与所述第二导电层平行或者垂直布置的第三导电层。
7.根据权利要求1所述的半导体集成电路，还包括通过第二层间水平互连结构与所述第一器件层电连接的第三器件层。
8.根据权利要求1所述的半导体集成电路，所述第一器件层在两侧上都具有器件。
9.一种集成电路，包括：
第一衬底，包括多个第一器件，以及
第一水平互连结构，设置在所述第一衬底中，
其中，所述第一水平互连结构包括从所述第一衬底之上观察时具有不同图案的第一导电层和第二导电层；
第二衬底，所述第二衬底包括多个第二器件，所述第一水平互连结构将一个或者多个第一器件电连接至一个或者多个第二器件。
10.根据权利要求9所述的集成电路，还包括所述第一衬底和所述第二衬底彼此电连接，因此所述第二衬底位于所述第一衬底下方。
11.根据权利要求10所述的集成电路，其中，将所述第一衬底沉积、喷涂、淋涂、旋涂或者接合至所述第二衬底。
12.根据权利要求11所述的集成电路，还包括：
第三衬底，包括堆叠至所述第一衬底上的多个第三器件，以及
第二水平连接结构，位于所述第三衬底内。
13.根据权利要求9所述的集成电路，其中，所述第二衬底位于所述第一衬底下方，其中，所述第一衬底的第一面面向所述第二衬底的第二面。
14.根据权利要求9所述的集成电路，其中，所述第一水平互连结构是铜、银、钨或者铝。
15.根据权利要求9所述的集成电路，其中，所述第一水平互连结构包括：Ta、Ti、TaN、TiW、TiWN或者TiN阻挡层；以及围绕所述阻挡层的介电层。
16.根据权利要求12所述的集成电路，其中，所述第一水平互连结构和所述第二水平连接结构具有相同或者不同数量的导电层或者具有相同或者不同图案的导电层。
17.一种制造堆叠CMOS器件的方法，包括：
形成具有第一衬底的包括多个第一器件的第一器件层，
在所述第一器件层上施加第二衬底，
在所述第二衬底中形成第一导电层，
在所述第二衬底中、在所述第一导电层上方形成第二导电层，以及
在所述第二衬底上形成多个第二器件，所述多个第二器件通过所述第二衬底中的所述第一导电层和所述第二导电层电连接至所述多个第一器件。
18.根据权利要求17所述的制造堆叠CMOS器件的方法，还包括：在所述第二衬底中形成垂直导电连接件以将所述第一导电层电连接至所述第二导电层。
19.根据权利要求18所述的制造堆叠CMOS器件的方法，其中，所述垂直导电连接件从之上观察时具有落入所述第一导电层的外边缘内的正方形状周界或者圆形周界。
20.根据权利要求17所述的制造堆叠CMOS器件的方法，其中，所述第一导电层是水平连接结构，并且其中，所述第二导电层是与所述第一导电层垂直的水平连接结构。
CN201410765376.1A 2013-12-11 2014-12-11 用于堆叠的cmos器件的连接技术 Active CN104716087B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/102,548 US9443758B2 (en) 2013-12-11 2013-12-11 Connecting techniques for stacked CMOS devices
US14/102,548 2013-12-11

Publications (2)

Publication Number Publication Date
CN104716087A CN104716087A (zh) 2015-06-17
CN104716087B true CN104716087B (zh) 2019-01-18

Family

ID=53271950

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410765376.1A Active CN104716087B (zh) 2013-12-11 2014-12-11 用于堆叠的cmos器件的连接技术

Country Status (3)

Country Link
US (5) US9443758B2 (zh)
KR (1) KR101751582B1 (zh)
CN (1) CN104716087B (zh)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9443758B2 (en) 2013-12-11 2016-09-13 Taiwan Semiconductor Manufacturing Co., Ltd. Connecting techniques for stacked CMOS devices
US9449919B2 (en) * 2015-02-12 2016-09-20 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device, layout design and method for manufacturing a semiconductor device
US10236886B2 (en) 2016-12-28 2019-03-19 Qualcomm Incorporated Multiple via structure for high performance standard cells
KR102336827B1 (ko) 2017-06-08 2021-12-09 삼성전자주식회사 반도체 장치
KR102585881B1 (ko) 2018-06-04 2023-10-06 삼성전자주식회사 반도체 소자 및 그 제조 방법.
EP3651188B1 (en) * 2018-11-12 2021-05-19 IMEC vzw A method for contacting a buried interconnect rail from the back side of an ic
CN110494969B (zh) * 2019-06-27 2020-08-25 长江存储科技有限责任公司 在形成三维存储器器件的阶梯结构中的标记图案
KR20210051346A (ko) 2019-10-30 2021-05-10 삼성전자주식회사 발진기 구조체 및 발진기 구조체를 포함하는 전자 장치

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1959983A (zh) * 2005-11-03 2007-05-09 国际商业机器公司 半导体器件及其制造方法
US8563403B1 (en) * 2012-06-27 2013-10-22 International Business Machines Corporation Three dimensional integrated circuit integration using alignment via/dielectric bonding first and through via formation last

Family Cites Families (84)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6034438A (en) * 1996-10-18 2000-03-07 The Regents Of The University Of California L-connect routing of die surface pads to the die edge for stacking in a 3D array
US6525414B2 (en) * 1997-09-16 2003-02-25 Matsushita Electric Industrial Co., Ltd. Semiconductor device including a wiring board and semiconductor elements mounted thereon
JP3064999B2 (ja) * 1997-11-13 2000-07-12 日本電気株式会社 半導体装置およびその製造方法
FR2771843B1 (fr) * 1997-11-28 2000-02-11 Sgs Thomson Microelectronics Transformateur en circuit integre
US7098506B2 (en) * 2000-06-28 2006-08-29 Renesas Technology Corp. Semiconductor device and method for fabricating the same
TW569424B (en) * 2000-03-17 2004-01-01 Matsushita Electric Ind Co Ltd Module with embedded electric elements and the manufacturing method thereof
US6451680B1 (en) * 2001-01-31 2002-09-17 United Microelectronics Corp. Method for reducing borderless contact leakage by OPC
JP4932088B2 (ja) * 2001-02-19 2012-05-16 ルネサスエレクトロニクス株式会社 絶縁ゲート型半導体装置の製造方法
TW560017B (en) * 2001-07-12 2003-11-01 Hitachi Ltd Semiconductor connection substrate
JP2003243797A (ja) * 2002-02-19 2003-08-29 Matsushita Electric Ind Co Ltd モジュール部品
JP2003264253A (ja) * 2002-03-12 2003-09-19 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
JP3940694B2 (ja) * 2003-04-18 2007-07-04 株式会社東芝 半導体装置及びその製造方法
JP2005109221A (ja) * 2003-09-30 2005-04-21 Toshiba Corp ウェーハレベルパッケージ及びその製造方法
JP4340517B2 (ja) * 2003-10-30 2009-10-07 Ｏｋｉセミコンダクタ株式会社 半導体装置及びその製造方法
JP4514188B2 (ja) * 2003-11-10 2010-07-28 キヤノン株式会社 光電変換装置及び撮像装置
US7348658B2 (en) * 2004-08-30 2008-03-25 International Business Machines Corporation Multilayer silicon over insulator device
JP4674850B2 (ja) * 2005-02-25 2011-04-20 ルネサスエレクトロニクス株式会社 半導体装置
KR100702011B1 (ko) * 2005-03-16 2007-03-30 삼성전자주식회사 다중 게이트 트랜지스터들을 채택하는 씨모스 에스램 셀들및 그 제조방법들
US8105941B2 (en) * 2005-05-18 2012-01-31 Kolo Technologies, Inc. Through-wafer interconnection
JP4551321B2 (ja) * 2005-07-21 2010-09-29 新光電気工業株式会社 電子部品実装構造及びその製造方法
US7863187B2 (en) * 2005-09-01 2011-01-04 Micron Technology, Inc. Microfeature workpieces and methods for forming interconnects in microfeature workpieces
KR100642763B1 (ko) * 2005-09-06 2006-11-10 삼성전자주식회사 반도체 소자의 ＴｉＮ 막 구조, 그 제조 방법, ＴｉＮ 막구조를 채용하는 반도체 소자 및 그 제조방법
WO2007049458A1 (ja) * 2005-10-26 2007-05-03 Murata Manufacturing Co., Ltd. 積層型電子部品、電子装置および積層型電子部品の製造方法
JP4575274B2 (ja) * 2005-10-31 2010-11-04 富士通セミコンダクター株式会社 パターンレイアウト、レイアウトデータの生成方法及び半導体装置
JP4609317B2 (ja) * 2005-12-28 2011-01-12 カシオ計算機株式会社 回路基板
US7282391B1 (en) * 2006-03-21 2007-10-16 International Business Machines Corporation Method for precision assembly of integrated circuit chip packages
US8124971B2 (en) * 2007-03-30 2012-02-28 Sandisk 3D Llc Implementation of diffusion barrier in 3D memory
US8435895B2 (en) * 2007-04-04 2013-05-07 Novellus Systems, Inc. Methods for stripping photoresist and/or cleaning metal regions
DE102007020288B4 (de) * 2007-04-30 2013-12-12 Epcos Ag Elektrisches Bauelement
JP2009076879A (ja) * 2007-08-24 2009-04-09 Semiconductor Energy Lab Co Ltd 半導体装置
JP5222509B2 (ja) * 2007-09-12 2013-06-26 ルネサスエレクトロニクス株式会社 半導体装置
JP5366517B2 (ja) * 2007-12-03 2013-12-11 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP5265183B2 (ja) * 2007-12-14 2013-08-14 新光電気工業株式会社 半導体装置
JP5271562B2 (ja) * 2008-02-15 2013-08-21 本田技研工業株式会社 半導体装置および半導体装置の製造方法
US8110342B2 (en) * 2008-08-18 2012-02-07 United Microelectronics Corp. Method for forming an opening
WO2010024233A1 (ja) * 2008-08-27 2010-03-04 日本電気株式会社 機能素子を内蔵可能な配線基板及びその製造方法
JP2010074072A (ja) * 2008-09-22 2010-04-02 Nec Corp 半導体装置および半導体装置の製造方法
JP2010114434A (ja) * 2008-10-08 2010-05-20 Ngk Spark Plug Co Ltd 部品内蔵配線基板及びその製造方法
JP5571306B2 (ja) * 2008-12-17 2014-08-13 ローム株式会社 半導体装置
JP5308145B2 (ja) * 2008-12-19 2013-10-09 ルネサスエレクトロニクス株式会社 半導体装置
US8158515B2 (en) * 2009-02-03 2012-04-17 International Business Machines Corporation Method of making 3D integrated circuits
US8487444B2 (en) * 2009-03-06 2013-07-16 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional system-in-package architecture
US8026608B2 (en) * 2009-03-24 2011-09-27 General Electric Company Stackable electronic package
US9793275B2 (en) * 2009-08-14 2017-10-17 Hewlett Packard Enterprise Development Lp Multilayer circuit
US8476145B2 (en) * 2010-10-13 2013-07-02 Monolithic 3D Inc. Method of fabricating a semiconductor device and structure
US8742476B1 (en) * 2012-11-27 2014-06-03 Monolithic 3D Inc. Semiconductor device and structure
US8450804B2 (en) * 2011-03-06 2013-05-28 Monolithic 3D Inc. Semiconductor device and structure for heat removal
CN104867984B (zh) * 2009-12-28 2018-11-06 株式会社半导体能源研究所 制造半导体装置的方法
US20110156195A1 (en) * 2009-12-31 2011-06-30 Tivarus Cristian A Interwafer interconnects for stacked CMOS image sensors
US20110156197A1 (en) * 2009-12-31 2011-06-30 Tivarus Cristian A Interwafer interconnects for stacked CMOS image sensors
US8541819B1 (en) * 2010-12-09 2013-09-24 Monolithic 3D Inc. Semiconductor device and structure
US8618654B2 (en) * 2010-07-20 2013-12-31 Marvell World Trade Ltd. Structures embedded within core material and methods of manufacturing thereof
US8535989B2 (en) * 2010-04-02 2013-09-17 Intel Corporation Embedded semiconductive chips in reconstituted wafers, and systems containing same
US8525342B2 (en) * 2010-04-12 2013-09-03 Qualcomm Incorporated Dual-side interconnected CMOS for stacked integrated circuits
US8455297B1 (en) * 2010-07-07 2013-06-04 International Business Machines Corporation Method to fabricate high performance carbon nanotube transistor integrated circuits by three-dimensional integration technology
US8642416B2 (en) * 2010-07-30 2014-02-04 Monolithic 3D Inc. Method of forming three dimensional integrated circuit devices using layer transfer technique
US8901613B2 (en) * 2011-03-06 2014-12-02 Monolithic 3D Inc. Semiconductor device and structure for heat removal
US8519444B2 (en) * 2010-09-10 2013-08-27 Taiwan Semiconductor Manufacturing Company, Ltd. Modified design rules to improve device performance
US8643191B2 (en) * 2012-01-26 2014-02-04 International Business Machines Corporation On-chip radial cavity power divider/combiner
US8975670B2 (en) * 2011-03-06 2015-03-10 Monolithic 3D Inc. Semiconductor device and structure for heat removal
TW201238024A (en) * 2011-03-11 2012-09-16 Univ Nat Chiao Tung Three-dimensional complementary metal oxide semiconductor device
US8338294B2 (en) * 2011-03-31 2012-12-25 Soitec Methods of forming bonded semiconductor structures including two or more processed semiconductor structures carried by a common substrate, and semiconductor structures formed by such methods
US8546946B2 (en) * 2011-04-20 2013-10-01 Nanya Technology Corp. Chip stack package having spiral interconnection strands
US8952540B2 (en) * 2011-06-30 2015-02-10 Intel Corporation In situ-built pin-grid arrays for coreless substrates, and methods of making same
US8617925B2 (en) * 2011-08-09 2013-12-31 Soitec Methods of forming bonded semiconductor structures in 3D integration processes using recoverable substrates, and bonded semiconductor structures formed by such methods
US8557684B2 (en) * 2011-08-23 2013-10-15 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional integrated circuit (3DIC) formation process
US8780576B2 (en) * 2011-09-14 2014-07-15 Invensas Corporation Low CTE interposer
JP5864180B2 (ja) * 2011-09-21 2016-02-17 新光電気工業株式会社 半導体パッケージ及びその製造方法
US9029173B2 (en) * 2011-10-18 2015-05-12 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US9496255B2 (en) * 2011-11-16 2016-11-15 Qualcomm Incorporated Stacked CMOS chipset having an insulating layer and a secondary layer and method of forming same
US8510699B1 (en) * 2012-03-09 2013-08-13 International Business Machines Corporation Performance driven layout optimization using morphing of a basis set of representative layouts
US9865657B2 (en) * 2012-03-15 2018-01-09 Sony Semiconductor Solutions Corporation Solid-state imaging device and electronic apparatus
US8557632B1 (en) * 2012-04-09 2013-10-15 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
TW201405758A (zh) * 2012-07-19 2014-02-01 矽品精密工業股份有限公司 具有防電磁波干擾之半導體元件
US8810006B2 (en) * 2012-08-10 2014-08-19 Taiwan Semiconductor Manufacturing Company, Ltd. Interposer system and method
US9589815B2 (en) * 2012-11-08 2017-03-07 Nantong Fujitsu Microelectronics Co., Ltd. Semiconductor IC packaging methods and structures
US9081932B2 (en) * 2013-02-01 2015-07-14 Qualcomm Incorporated System and method to design and test a yield sensitive circuit
JP5814959B2 (ja) * 2013-02-21 2015-11-17 株式会社東芝 半導体装置及びその製造方法
US9123547B2 (en) * 2013-03-13 2015-09-01 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked semiconductor device and method of forming the same
US9209134B2 (en) * 2013-03-14 2015-12-08 Intermolecular, Inc. Method to increase interconnect reliability
US9079761B2 (en) * 2013-03-14 2015-07-14 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked semiconductor device and method of forming the same related cases
US9443758B2 (en) * 2013-12-11 2016-09-13 Taiwan Semiconductor Manufacturing Co., Ltd. Connecting techniques for stacked CMOS devices
US9281211B2 (en) * 2014-02-10 2016-03-08 International Business Machines Corporation Nanoscale interconnect structure
KR102664314B1 (ko) * 2016-12-29 2024-05-14 삼성전자주식회사 이미지 센서

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1959983A (zh) * 2005-11-03 2007-05-09 国际商业机器公司 半导体器件及其制造方法
US8563403B1 (en) * 2012-06-27 2013-10-22 International Business Machines Corporation Three dimensional integrated circuit integration using alignment via/dielectric bonding first and through via formation last

Also Published As

Publication number Publication date
US20160336289A1 (en) 2016-11-17
US9443758B2 (en) 2016-09-13
CN104716087A (zh) 2015-06-17
US11532586B2 (en) 2022-12-20
US9853008B2 (en) 2017-12-26
US10497661B2 (en) 2019-12-03
US20200027854A1 (en) 2020-01-23
KR20150068302A (ko) 2015-06-19
US20180108635A1 (en) 2018-04-19
US20200027853A1 (en) 2020-01-23
KR101751582B1 (ko) 2017-06-27
US20150162295A1 (en) 2015-06-11
US11217553B2 (en) 2022-01-04

Similar Documents

Publication Publication Date Title
CN104716087B (zh) 用于堆叠的cmos器件的连接技术
KR102167599B1 (ko) 칩 스택 임베디드 패키지
US7807512B2 (en) Semiconductor packages and methods of fabricating the same
US9130024B2 (en) Three-dimensional semiconductor device
CN107851615A (zh) 独立3d堆叠
CN106935563B (zh) 电子封装件及其制法与基板结构
US20150048509A1 (en) Cmos compatible wafer bonding layer and process
US9947644B2 (en) Semiconductor package
TW200901426A (en) Molded reconfigured wafer, stack package using the same, and method for manufacturing the stack package
KR102012505B1 (ko) 토큰 링 루프를 갖는 스택 패키지
KR20090043896A (ko) 칩 적층 패키지
US10249587B1 (en) Semiconductor device including optional pad interconnect
CN106206476A (zh) 电子封装件及其制法
KR20180112394A (ko) 반도체 패키지 제조 방법 및 반도체 패키지
CN104766806B (zh) 晶圆三维集成的方法
CN103681587B (zh) 应力降低装置
TWI685944B (zh) 三維直通矽晶貫孔結構
US8907464B2 (en) Helix substrate and three-dimensional package with same
CN104766828B (zh) 晶圆三维集成的方法
KR100871708B1 (ko) 딤플을 구비하는 칩, 그 제조방법 및 그 칩을 이용한패키지
KR100843232B1 (ko) 측면패드를 구비하는 칩, 그 제조방법 및 그 칩을 이용한패키지
KR20140081550A (ko) 배선 구조물을 구비하는 패키지 기판 구조물 및 이를 포함하는 반도체 패키지, 패키지 기판 구조물 및 반도체 패키지의 제조 방법
CN104900635A (zh) 半导体封装件及其半导体结构
KR20110078557A (ko) 3차원 집적 소자 및 그 제조 방법
US20130154111A1 (en) Semiconductor device including through electrode and method of manufacturing the same and stacked package including semiconductor device and method of manufacturing the same

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant