TW201405758A - 具有防電磁波干擾之半導體元件 - Google Patents

具有防電磁波干擾之半導體元件 Download PDF

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Publication number
TW201405758A
TW201405758A TW101125981A TW101125981A TW201405758A TW 201405758 A TW201405758 A TW 201405758A TW 101125981 A TW101125981 A TW 101125981A TW 101125981 A TW101125981 A TW 101125981A TW 201405758 A TW201405758 A TW 201405758A
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Taiwan
Prior art keywords
metal layer
semiconductor
electromagnetic wave
wave interference
interference prevention
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TW101125981A
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English (en)
Inventor
宋澤世
江文榮
李信宏
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矽品精密工業股份有限公司
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Application filed by 矽品精密工業股份有限公司 filed Critical 矽品精密工業股份有限公司
Priority to TW101125981A priority Critical patent/TW201405758A/zh
Priority to CN201210264661.6A priority patent/CN103579197B/zh
Priority to US13/728,112 priority patent/US20140021591A1/en
Publication of TW201405758A publication Critical patent/TW201405758A/zh

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Abstract

一種具有防電磁波干擾(EMI)之半導體元件，係包括：基材，係具有貫穿之第一與第二導電穿孔；線路重佈層，係形成於該基材上且具有電性連接墊；以及金屬層，係形成於該線路重佈層上且具有開口，以令該些電性連接墊位於該開口內而未電性連接該金屬層，而令該第二導電穿孔與該金屬層構成屏蔽結構，以避免電磁波由該線路重佈層或該半導體元件之側面進出而發生EMI現象。

Description

具有防電磁波干擾之半導體元件
本發明係有關一種半導體元件，尤指一種具有防電磁波干擾之半導體元件。
近年來，隨著消費者對於電子產品功能多樣化與體積輕薄化的需求與日俱增，在一定面積上整合更多晶片與功能遂成為封裝技術之趨勢，致使表面置放式之封裝件已不符合半導體封裝件微型化(miniaturization)的封裝需求，故遂發展出三維(3D)晶片堆疊技術。
所述之三維晶片結構是晶片立體堆疊化的整合，而目前三維晶片(3D IC)技術係將不同功能、性質或基板的晶片，各自採用最合適的製程分別製作後，再利用矽穿孔(Through-Silicon Via,TSV)技術進行立體堆疊整合，以有效縮短線路傳導路徑之長度，因而能降低導通電阻，且能減少晶片面積，進而具有體積小、高整合度、高效率、降低耗電量等優點，並同時符合數位電子輕薄短小之需求。然而，堆疊之晶片間容易互相電磁波干擾(Electromagnetic Interference,EMI)，故各該晶片之間的EMI問題更顯重要。
如第1圖所示，係提供一種3D晶片堆疊之半導體封裝件1，係於一承載件10上堆疊兩具有導電矽穿孔110a,110b之晶片11a,11b，該兩晶片11a,11b間係藉由一絕緣層14相結合，且該下層晶片11b與承載件10之間係 填充底膠16，並以封裝膠體13封裝該些晶片11a,11b。
習知具有導電矽穿孔110a,110b之晶片11a,11b係於其中一側形成線路重佈層(Redistribution layer,RDL)(圖略)，以結合導電元件15,111，俾供堆疊其它半導體元件。
惟，習知半導體封裝件1中，該些晶片11a,11b之間僅具有絕緣層14，而並無任何屏蔽結構，故當該些晶片11a,11b在高速高頻運作時，會產生較強的電磁輻射，而影響該兩晶片11a,11b上的訊號，即發生EMI現象，因而造成該半導體封裝件1操作不良。
因此，如何克服上述習知技術之半導體封裝件內部晶片發生EMI現象的問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失，本發明係提供一種具有防電磁波干擾之半導體元件，係包括：一基材，係具有相對之第一表面與第二表面，且該基材中具有連通該第一及第二表面之複數第一導電穿孔與複數第二導電穿孔；一線路重佈層，係形成於該基材之第一表面上，且具有複數電性連接墊，該電性連接墊係電性導通該第一導電穿孔；以及一第一金屬層，係形成於該線路重佈層上且電性導通該第二導電穿孔，使該第二導電穿孔與該第一金屬層構成屏蔽結構，且該第一金屬層具有複數第一開口，以令該電性連接墊位於該第一開口內而未電性連接該第一金屬層。
前述之半導體元件中，該些電性連接墊係接置至少一 電子元件。其中，該電子元件係為主動元件、被動元件或中介板。
本發明又提供一種半導體堆疊結構，係包括：前述之具有防電磁波干擾之半導體元件，係作為第一半導體元件；以及第二半導體元件，係與該第一半導體元件之結構相同，且該第二半導體元件以其基材之第二表面之一側接置於該第一半導體元件具該第一金屬層之一側上。
前述之半導體堆疊結構及其半導體元件中，該些第二導電穿孔係排列成環形，以包圍該些第一導電穿孔。
前述之半導體堆疊結構及其半導體元件中，復包括一絕緣保護層，係形成於該線路重佈層與該第一金屬層上，且外露該些電性連接墊。其中，該絕緣保護層復外露該第一金屬層之部分表面。
前述之半導體堆疊結構及其半導體元件中，復包括一線路增層結構，係形成於該基材之第二表面上，且具有複數電性接觸墊，該電性接觸墊係電性導通該第一導電穿孔。又包括一第二金屬層，係形成於該線路增層結構上且電性導通該第二導電穿孔，使該屏蔽結構復具有該第二金屬層，且該第二金屬層具有複數第二開口，以令該電性接觸墊位於該第二開口內而未連接該第二金屬層。另包括一絕緣保護層，係形成於該線路增層結構與該第二金屬層上，且外露該些電性接觸墊。其中，該絕緣保護層復外露該第二金屬層之部分表面。
由上可知，本發明之半導體堆疊結構及其具有防電磁 波干擾之半導體元件，係藉由藉由第一金屬層與第二導電穿孔作為屏蔽結構，以避免電磁波由該RDL或該具有防電磁波干擾之半導體元件之側面進出，故能避免該具有防電磁波干擾之半導體元件與其它鄰近之電子元件(或第二半導體元件)發生EMI現象。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“底”、“頂”、“第一”、“第二”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A、2A’及2B圖係為本發明之具有防電磁波干擾之半導體元件2之第一實施例之剖面與下視示意圖。如第2A圖所示，所述之半導體元件2係包括：一基材20、一線路重佈層(Redistribution layer,RDL)21、一第一金屬層 22以及一絕緣保護層23。
所述之基材20係為中介板(interposer)、晶片或晶圓，且具有相對之第一表面20a(於本實施例中為底面)與第二表面20b(於本實施例中為頂面)，且該基材20中具有連通該第一及第二表面20a,20b之複數第一導電穿孔200a與複數第二導電穿孔200b。
於本實施例中，該些第二導電穿孔200b係排列成環形，以包圍該些第一導電穿孔200a，如第2A’圖所示。
於另一實施例中，可設置複數電子元件(圖略)於該第二表面20b上。
所述之線路重佈層21係透過線路增層製程而形成於該基材20之第一表面20a上，且具有複數電性連接墊213，該些電性連接墊213係電性導通該些第一導電穿孔200a。
於本實施例中，該線路重佈層21係具有至少一介電層210、形成於該介電層210上之線路層211及形成於該介電層210中之複數導電盲孔212，該些導電盲孔212係電性連接該線路層211、第一與第二導電穿孔200a,200b，且該最外層之線路層211上具有該些電性連接墊213。
再者，該線路重佈層21中可嵌埋被動元件，例如電容、電感、電阻等，且嵌埋之方式繁多，並無特別限制。
所述之第一金屬層22係形成於該線路重佈層21之最外層之介電層210上，亦即該第一金屬層22與該電性連接墊213位於同一層，且該第一金屬層22電性導通該些第二 導電穿孔200b，以令該些第二導電穿孔200b與該第一金屬層22構成屏蔽結構2a。又該第一金屬層22具有複數第一開口220，以令該些電性連接墊213對應位於該些第一開口220內而未電性連接該第一金屬層22，如第2A’圖所示。
於本實施例中，該第一金屬層22可與該些電性連接墊213一同以圖案化製程完成。
所述之絕緣保護層23係形成於該線路重佈層21與該第一金屬層22上，且外露該些電性連接墊213與該第一金屬層22之部分表面(作為接地墊221之用，俾供外接之電子元件進行接地)。
於本實施例中，該絕緣保護層23具有複數開孔230，以對應外露該些電性連接墊213與該接地墊221。
再者，該接地墊221可藉由該絕緣保護層23之開孔230定義，如第2A’圖所示之假想線L，故製作該些電性連接墊213時，不需製作該接地墊221。
又，於另一實施例中，該接地墊221’可由該第一開口220定義出其形狀，如第2B圖所示，亦即該接地墊221’與該些電性連接墊213一同製作，且藉由線路222電性導通該接地墊221’與該第一金屬層22。
本發明藉由該第一金屬層22作為屏蔽結構2a，可防止電磁輻射由該半導體元件2之底側(即該線路重佈層21)進出，以避免該半導體元件2與其它電子元件相互影響而發生EMI現象。
再者，藉由該些第二導電穿孔200b作為屏蔽結構2a，可防止電磁輻射由該半導體元件2之側面進出，以避免該半導體元件2與其它電子元件相互影響而發生EMI現象。當該些第二導電穿孔200b包圍該些第一導電穿孔200a時，其防止EMI發生之功效更佳。
第3A及3B圖係為本發明之具有防電磁波干擾之半導體元件2’之第二實施例之剖面示意圖。於第二實施例中，該基材20之第一表面20a係為頂面，該第二表面20b係為底面。
如第3A圖所示，所述之半導體元件2’復包括：一線路增層結構24及一第二金屬層25。
所述之線路增層結構24係形成於該基材20之第二表面20b上，且具有複數電性接觸墊243，該些電性接觸墊243係電性導通該第一導電穿孔200a。
於第二實施例中，該線路增層結構24與該線路重佈層21之製程及結構均大致相同，且該線路增層結構24之最外層之介電層240上具有該些電性接觸墊243。
所述之第二金屬層25係形成於該線路增層結構24之最外層之介電層240上，亦即該第二金屬層25與該電性接觸墊243位於同一層，且該第二金屬層25係電性導通該第二導電穿孔200b，使該第二導電穿孔200b、該第一金屬層22與該第二金屬層25構成屏蔽結構2a’。又該第二金屬層25具有一第二開口250，以令該些電性接觸墊243位於該第二開口250內而未連接該第二金屬層25。
於第二實施例中，該第二金屬層25係藉由該線路增層結構24之導電盲孔242電性導通該第二導電穿孔200b，且該第二金屬層25可與該些電性接觸墊243一同以圖案化製程完成。
再者，該半導體元件2’亦包括一絕緣保護層26，係形成於該線路增層結構24與該第二金屬層25上，且該絕緣保護層26具有複數開孔260，以對應外露該些電性接觸墊243及該第二金屬層25之部分表面(作為接地墊251之用)。
又，於後續封裝製程中，如第3B圖所示，該電性連接墊213與該接地墊221係可藉由如銲球之導電元件40接置如主動元件、晶片4、晶圓、中介板或其它半導體元件結構之電子元件；該電性接觸墊243與該接地墊251亦可藉由如銲球之導電元件50接置如封裝基板或電路板5之電子裝置。之後，形成封裝膠體6以包覆該半導體元件2’與晶片4。
本發明藉由該第一金屬層22作為屏蔽結構2a’，可防止電磁輻射由該半導體元件2’之線路重佈層21進出，以避免該半導體元件2’與晶片4相互影響而發生EMI現象。
再者，藉由該第二金屬層25作為屏蔽結構，可防止電磁輻射由該半導體元件2’之線路增層結構24進出，以避免該半導體元件2’與電路板5相互影響而發生EMI現象。
又，製作該線路重佈層21與該線路增層結構24時，一併完成該第一與第二金屬層22,25之製作，故於封裝製 程後，不需於該封裝膠體6上製作屏蔽層，不僅可簡化製程而降低成本，且可確保封裝件內之各電子元件間之訊號不會相互影響。
第4圖係為應用第二實施例之半導體元件2’之剖面示意圖。如第4圖所示，係提供一種半導體堆疊結構3，係包括：第二實施例所述之半導體元件2’(用以作為第一半導體元件)以及另一半導體元件(用以作為第二半導體元件3a)。
該半導體元件2’係設於該第二半導體元件3a上方。
所述之第二半導體元件3a係與該半導體元件2’之結構相同，且該第二半導體元件3a以其基材30之第二表面30b之一側接置於該半導體元件2’具該第一金屬層22之一側上，例如，藉如銲球之導電元件60結合該第二半導體元件3a之該電性接觸墊343及接地墊351與該半導體元件2’之電性連接墊213及接地墊221。
再者，於該半導體元件2’之線路增層結構24上係可接置一主動元件，例如晶片。於另一實施例中，該第二半導體元件3a之基材30之第二表面30b具有複數主動元件設置於其上。另一半導體元件2’之結構大致與第二半導體元件3a相同，並堆疊於其上。
於該半導體堆疊結構3中，係藉由該第一金屬層22作為屏蔽結構2a，可防止電磁輻射由該半導體元件2’之線路重佈層21進出，以避免該半導體元件2’與該第二半導體元件3a相互影響而發生EMI現象。
再者，可依此堆疊方式，堆疊複數個第一實施例所述之半導體元件2或複數個第二實施例所述之半導體元件2’。
綜上所述，本發明之具有防電磁波干擾之半導體元件及其半導體堆疊結構，主要藉由第一與第二金屬層作為防止縱向EMI發生之屏蔽結構，而藉由第二導電穿孔作為防止橫向EMI發生之屏蔽結構，以避免於單一封裝件中，內部各電子元件之訊號相互影響，故能有效避免於封裝件內部發生EMI現象。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
1‧‧‧半導體封裝件
10‧‧‧承載件
100‧‧‧導電通孔
11a,11b,4‧‧‧晶片
110a,110b‧‧‧導電矽穿孔
111,15,40,50,60‧‧‧導電元件
13,6‧‧‧封裝膠體
14‧‧‧絕緣層
16‧‧‧底膠
2,2’‧‧‧半導體元件
2a,2a’‧‧‧屏蔽結構
20,30‧‧‧基材
20a‧‧‧第一表面
20b,30b‧‧‧第二表面
200a‧‧‧第一導電穿孔
200b‧‧‧第二導電穿孔
21‧‧‧線路重佈層
210,240‧‧‧介電層
211,241‧‧‧線路層
212,242‧‧‧導電盲孔
213‧‧‧電性連接墊
22‧‧‧第一金屬層
220‧‧‧第一開口
221,221’,251,351‧‧‧接地墊
222‧‧‧線路
23,26‧‧‧絕緣保護層
230,260‧‧‧開孔
24‧‧‧線路增層結構
243,343‧‧‧電性接觸墊
25‧‧‧第二金屬層
250‧‧‧第二開口
3‧‧‧半導體堆疊結構
3a‧‧‧第二半導體元件
5‧‧‧電路板
L‧‧‧假想線
第1圖係為習知3D晶片堆疊之半導體封裝件的剖視示意圖；第2A圖係為本發明之具有防電磁波干擾之半導體元件之第一實施例之剖視示意圖；第2A’圖係為第2A圖(省略絕緣保護層)之下視示意圖；第2B圖係為第2A’圖(省略絕緣保護層)之另一實施例之下視示意圖；第3A圖係為本發明之具有防電磁波干擾之半導體元 件之第二實施例之剖視示意圖；第3B圖係為第3A圖進行封裝製程後之封裝件之剖視示意圖；以及第4圖係為本發明之半導體堆疊結構之剖視示意圖。
2‧‧‧半導體元件
2a‧‧‧屏蔽結構
20‧‧‧基材
20a‧‧‧第一表面
20b‧‧‧第二表面
200a‧‧‧第一導電穿孔
200b‧‧‧第二導電穿孔
21‧‧‧線路重佈層
210‧‧‧介電層
211‧‧‧線路層
212‧‧‧導電盲孔
213‧‧‧電性連接墊
22‧‧‧第一金屬層
220‧‧‧開口
221‧‧‧接地墊
23‧‧‧絕緣保護層
230‧‧‧開孔

Claims (11)

  1. 一種具有防電磁波干擾之半導體元件，係包括：一基材，係具有相對之第一表面與第二表面，且該基材中具有連通該第一及第二表面之複數第一導電穿孔與複數第二導電穿孔；一線路重佈層，係形成於該基材之第一表面上，且具有複數電性連接墊，該電性連接墊係電性導通該第一導電穿孔；以及一第一金屬層，係形成於該線路重佈層上且電性導通該第二導電穿孔，使該第二導電穿孔與該第一金屬層構成屏蔽結構，且該第一金屬層具有複數第一開口，以令該電性連接墊位於該第一開口內而未電性連接該第一金屬層。
  2. 如申請專利範圍第1項所述之具有防電磁波干擾之半導體元件，其中，該半導體元件係作為第一半導體元件，且復包括與該第一半導體元件之結構相同的第二半導體元件，該第二半導體元件以其基材之第二表面之一側接置於該第一半導體元件具該第一金屬層之一側上，以成為一半導體堆疊結構。
  3. 如申請專利範圍第1項所述之具有防電磁波干擾之半導體元件，其中，該些電性連接墊係接置至少一電子元件。
  4. 如申請專利範圍第3項所述之具有防電磁波干擾之半導體元件，其中，該電子元件係為主動元件、被動元 件或中介板。
  5. 如申請專利範圍第1、2或3項所述之具有防電磁波干擾之半導體元件，其中，該些第二導電穿孔係排列成環形，以包圍該些第一導電穿孔。
  6. 如申請專利範圍第1、2或3項所述之具有防電磁波干擾之半導體元件，復包括一絕緣保護層，係形成於該線路重佈層與該第一金屬層上，且外露該些電性連接墊。
  7. 如申請專利範圍第6項所述之具有防電磁波干擾之半導體元件，其中，該絕緣保護層復外露該第一金屬層之部分表面。
  8. 如申請專利範圍第1、2或3項所述之具有防電磁波干擾之半導體元件，復包括一線路增層結構，係形成於該基材之第二表面上，且具有複數電性接觸墊，該電性接觸墊係電性導通該第一導電穿孔。
  9. 如申請專利範圍第8項所述之具有防電磁波干擾之半導體元件，復包括一第二金屬層，係形成於該線路增層結構上且電性導通該第二導電穿孔，使該屏蔽結構復具有該第二金屬層，且該第二金屬層具有複數第二開口，以令該電性接觸墊位於該第二開口內而未連接該第二金屬層。
  10. 如申請專利範圍第9項所述之具有防電磁波干擾之半導體元件，復包括一絕緣保護層，係形成於該線路增層結構與該第二金屬層上，且外露該些電性接觸墊。
  11. 如申請專利範圍第10項所述之具有防電磁波干擾之半導體元件，其中，該絕緣保護層復外露該第二金屬層之部分表面。
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