TW202127625A - 電子封裝件及其製法 - Google Patents

電子封裝件及其製法 Download PDF

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Publication number
TW202127625A
TW202127625A TW109100324A TW109100324A TW202127625A TW 202127625 A TW202127625 A TW 202127625A TW 109100324 A TW109100324 A TW 109100324A TW 109100324 A TW109100324 A TW 109100324A TW 202127625 A TW202127625 A TW 202127625A
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Taiwan
Prior art keywords
carrier
shielding
item
electronic
patent application
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TW109100324A
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English (en)
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TWI718838B (zh
Inventor
蔡明汎
陳志偉
蔡宗賢
楊超雅
陳嘉揚
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矽品精密工業股份有限公司
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Priority to TW109100324A priority Critical patent/TWI718838B/zh
Priority to CN202010052362.0A priority patent/CN113078139A/zh
Priority to US16/997,173 priority patent/US11764162B2/en
Application granted granted Critical
Publication of TWI718838B publication Critical patent/TWI718838B/zh
Publication of TW202127625A publication Critical patent/TW202127625A/zh

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    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
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    • H01L2924/15192—Resurf arrangement of the internal vias
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    • H—ELECTRICITY
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    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
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    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Abstract

一種電子封裝件及其製法，係將複數屏蔽線係設於一承載件上且跨越一電子元件以遮蓋該電子元件，使該些屏蔽線作為屏蔽結構，避免該電子元件受外部電磁波干擾之問題。

Description

電子封裝件及其製法
本發明係有關一種半導體封裝製程，尤指一種具屏蔽結構之電子封裝件及其製法。
隨著電子產業的蓬勃發展，大部份的電子產品均朝向小型化及高速化的目標發展，尤其是通訊產業的發展已普遍將通訊裝置運用整合於各類電子產品，例如行動電話(Cell phone)、膝上型電腦(laptop)等。然而上述之電子產品需使用高頻的射頻晶片，且射頻晶片可能相鄰設置數位積體電路、數位訊號處理器(Digital Signal Processor，簡稱DSP)或基頻晶片(BB,Base Band)，造成電磁干擾(Electromagnetic Interference，簡稱EMI)問題，因此必需進行電磁屏蔽(Electromagnetic Shielding)處理。
習知避免EMI之射頻(Radio frequency，簡稱RF)模組之製法，如第1A至1C圖所示，係將複數射頻晶片11a,11b與非射頻式電子元件11電性連接在一封裝基板10上，再以係如環氧樹脂之封裝層13包覆各該射頻晶片11a,11b與該非射頻式電子元件11，並於該封裝層13上形成一金屬薄膜14。該射頻模組1藉由該封裝層13保護該射頻晶片11a,11b、非射頻式電 子元件11及封裝基板10，並避免外界水氣或污染物之侵害，且藉由該金屬薄膜14保護該些射頻晶片11a,11b免受外界EMI影響。
惟，習知射頻模組1之外圍雖可藉由包覆該金屬薄膜14以達到避免EMI之目的，但若射頻晶片11a,11b如為低頻元件，則單一金屬薄膜14作為屏障層仍難以防止電磁干擾。
因此，如何克服上述習知技術之問題，實已成為目前業界亟待克服之難題。
鑑於上述習知技術之種種缺失，本發明提供一種電子封裝件，係包括：承載件；電子元件，係設於該承載件上且電性連接該承載件；複數屏蔽線，係設於該承載件上且跨越該電子元件以遮蓋該電子元件，其中，該複數屏蔽線係相互交錯；以及封裝層，係形成於該承載件上以包覆該電子元件及屏蔽線。
本發明亦提供一種電子封裝件之製法，係包括：提供一設有至少一電子元件之承載件，且該電子元件係電性連接該承載件；形成複數屏蔽線於該承載件上，以令該屏蔽線跨越該電子元件，使該屏蔽線遮蓋該電子元件，其中，該複數屏蔽線係相互交錯；以及形成封裝層於該承載件上，以令該封裝層包覆該電子元件及屏蔽線。
前述之電子封裝件及其製法中，該屏蔽線之相對兩端部係分別連接至該承載件。
前述之電子封裝件及其製法中，該屏蔽線係為打線製程之銲線。
前述之電子封裝件及其製法中，該複數屏蔽線係沿其中一方向形成。
前述之電子封裝件及其製法中，該複數屏蔽線係沿多方向形成。
前述之電子封裝件及其製法中，該屏蔽線外露於該封裝層。
前述之電子封裝件及其製法中，該屏蔽線係為弧線，其弧頂外露於該封裝層。例如，該弧頂係齊平該封裝層之表面。
前述之電子封裝件及其製法中，復包括形成屏蔽件於該封裝層上。
由上可知，本發明之電子封裝件及其製法，主要藉由該屏蔽線跨越該電子元件，以作為屏蔽結構，藉以避免該電子元件受外部電磁波干擾之問題，且藉由交錯型屏蔽線以形成不規則通道，藉以破壞幅射路徑，故能達到更小的電磁幅射量，以提升電磁干擾之屏蔽效果。
再者，若該電子元件為低頻元件，則藉由埋設於該封裝層內之屏蔽線能提供較好的防電磁干擾效果。
1‧‧‧射頻模組
10‧‧‧封裝基板
11‧‧‧非射頻式電子元件
11a,11b‧‧‧射頻晶片
13,24‧‧‧封裝層
14‧‧‧金屬薄膜
2‧‧‧電子封裝件
20‧‧‧承載件
20a‧‧‧第一側
20b‧‧‧第二側
20’‧‧‧絕緣保護層
200‧‧‧電性接觸墊
201‧‧‧接地墊
202‧‧‧接地層
21‧‧‧電子元件
21a‧‧‧作用面
21b‧‧‧非作用面
22‧‧‧銲線
23,23’‧‧‧屏蔽線
23a,23b‧‧‧端部
230‧‧‧弧頂
24a‧‧‧第一表面
24b‧‧‧第二表面
25‧‧‧屏蔽件
S‧‧‧切割路徑
第1A至1C圖係為習知射頻模組之製法之剖面示意圖。
第2A至2E圖係為本發明之電子封裝件之製法之剖視示意圖。
第2B’及2B”圖係為第2B圖之不同態樣之局部上視示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“第一”、“第二”、“上”、及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A至2E圖係為本發明之電子封裝件2之製法之剖視示意圖。
如第2A圖所示，提供一承載件20及至少一電子元件21，該承載件20係具有相對之第一側20a與第二側20b，且該電子元件21係設於該承載件20之第一側20a上並電性連接該承載件20。
於本實施例中，該承載件20係為具有核心層與線路結構之基板(substrate)或無核心層(coreless)之線路結構，該線路結構係於介電材上形成線路層(圖略)，如扇出(fan out)型重佈線路層(redistribution layer，簡稱RDL)，且介電材係為如聚對二唑苯(Polybenzoxazole，簡稱PBO)、聚醯亞胺(Polyimide，簡稱PI)、預浸材(Prepreg，簡稱PP)等。例如，該基板之最外側具有線路層與絕緣保護層20’，該線路層包含複數外露於該絕緣保護層20’之電性接觸墊200與接地墊201，且該接地墊201 係電性連接該基板之內部線路之接地層202。應可理解地，該承載件20亦可為其它可供承載如晶片等電子元件之承載單元，例如導線架(lead-frame)或矽中介板(silicon interposer)等載件，並不限於上述。
再者，該電子元件21係為主動元件、被動元件或其組合者，且該主動元件係例如半導體晶片，而該被動元件係例如電阻、電容及電感。該電子元件21係為射頻晶片或其它半導體晶片，例如，藍芽晶片或無線熱點(Wi-Fi(Wireless Fidelity))晶片，其具有作用面21a與相對該作用面21a之非作用面21b，且該作用面21a上具有複數電極墊(圖略)，並以該非作用面21b設於該承載件20之第一側20a上，使該電子元件21以其電極墊藉由複數銲線22以打線方式電性連接該承載件20之線路層；或者，該電子元件21以該些電極墊藉由複數導電凸塊(圖略)以覆晶方式電性連接該線路層；亦或，該電子元件21可直接接觸該線路層以電性連接該線路層。然而，有關該電子元件21電性連接該承載件20之方式不限於上述。
如第2B圖所示，形成複數跨越該電子元件21之屏蔽線23於該承載件20之第一側20a上，令該些屏蔽線23遮蓋該電子元件21之作用面21a。
於本實施例中，該屏蔽線23之相對兩端部23a,23b分別連接至該些接地墊201。例如，兩屏蔽線23係於單一處交錯形成，如第2B’圖所示。
再者，該屏蔽線23係為打線製程之銲線，如弧形金線，針對單一電子元件21沿其中一方向(如X或Y方向)佈設複數條屏蔽線23，如第2B’圖所示；或者，針對單一電子元件21沿多方向(如X方向及Y方向)佈設複數條屏蔽線23,23’，如第2B”圖所示。
如第2C圖所示，形成一封裝層24於該承載件20之第一側20a上，以令該封裝層24包覆該電子元件21、銲線22及屏蔽線23。
於本實施例中，該封裝層24係為絕緣材，如聚醯亞胺(polyimide，簡稱PI)、乾膜(dry film)、如環氧樹脂(epoxy)之封裝膠體或封裝材(molding compound)。例如，該封裝層24之製程可選擇液態封膠(liquid compound)、噴塗(injection)、壓合(lamination)或模壓(compression molding)等方式形成於該承載件20上。
再者，該封裝層24係具有相對之第一表面24a與第二表面24b，以令該封裝層24以其第二表面24b結合於該承載件20之第一側20a上，且令該屏蔽線23之至少部分表面外露於該封裝層24之第一表面24a。例如，可藉由整平製程，使該封裝層24之第一表面24a齊平該屏蔽線23之弧頂230，以令該屏蔽線23之弧頂230外露於該封裝層24之第一表面24a。具體地，該整平製程係藉由研磨方式，移除該封裝層24之部分材質。應可理解地，有關外露該屏蔽線23之方式繁多，如開孔，並不限於上述。
如第2D圖所示，形成一屏蔽件25於該封裝層24之第一表面24a上，且令該屏蔽件25接觸該屏蔽線23。
於本實施例中，該屏蔽件25係為導電材，其材質不同於該封裝層24之材質。例如，該屏蔽件25係為導電層，如銅(Cu)、鎳(Ni)、鐵(Fe)或鋁(Al)等，其係以電鍍、如濺鍍(sputtering)之化學鍍膜、塗佈(coating)或其它方式形成。
如第2E圖所示，沿如第2D圖所示之切割路徑S進行切單製程，以獲取複數電子封裝件2，且可於該承載件20之第二側20b上形成複數如銲球之導電元件(圖略)，供該電子封裝件2接置一如電路板之電子裝置(圖略)。
於本實施例中，該電子封裝件2係為可發出電磁波者，如射頻(Radio frequency，簡稱RF)模組。
因此，本發明之製法主要藉由該屏蔽線23,23’跨越該電子元件21，以作為屏蔽結構，藉以避免該電子元件21受外部電磁波干擾之問題，且藉由交錯型屏蔽線23,23’以形成不規則通道，藉以破壞幅射路徑，達到更小的電磁幅射量，以提升電磁干擾之屏蔽效果。
再者，若該電子元件21為低頻元件，則藉由將該些屏蔽線23,23’埋設於該封裝層24內以更靠近該電子元件21，使該些屏蔽線23,23’能提供較好的防電磁干擾效果。
本發明亦提供一種電子封裝件2，係包括：一承載件20、一電子元件21以及複數屏蔽線23。
所述之承載件20係具有複數接地墊201。
所述之電子元件21係設於該承載件20上且電性連接該承載件20。
所述之屏蔽線23係設於該承載件20上且跨越該電子元件21以遮蓋該電子元件21，其中，該複數屏蔽線23係相互交錯。
所述之封裝層24係形成於該承載件20上以包覆該電子元件21及屏蔽線23。
於一實施例中，該屏蔽線23之相對兩端部23a,23b係分別連接至該承載件20之接地墊201。
於一實施例中，該屏蔽線23係為打線製程之銲線。
於一實施例中，該複數屏蔽線23係對應該電子元件沿其中一方向佈設。
於一實施例中，該複數屏蔽線23,23’係對應該電子元件沿多方向佈設。
於一實施例中，該屏蔽線23外露於該封裝層24。
於一實施例中，該屏蔽線23係為弧線，其弧頂230外露於該封裝層24。例如，該弧頂230係齊平該封裝層24之第一表面24a。
於一實施例中，所述之電子封中件2復包括一形成於該封裝層24上之屏蔽件25。
綜上所述，本發明之電子封裝件及其製法，係藉由該屏蔽線之設計，以避免該電子元件受外部電磁波干擾之問題。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2‧‧‧電子封裝件
20‧‧‧承載件
20a‧‧‧第一側
20b‧‧‧第二側
200‧‧‧電性接觸墊
201‧‧‧接地墊
202‧‧‧接地層
21‧‧‧電子元件
22‧‧‧銲線
23‧‧‧屏蔽線
24‧‧‧封裝層
24a‧‧‧第一表面
24b‧‧‧第二表面
25‧‧‧屏蔽件

Claims (18)

  1. 一種電子封裝件，係包括；
    承載件；
    電子元件，係設於該承載件上且電性連接該承載件；
    複數屏蔽線，係設於該承載件上且跨越該電子元件，其中，該複數屏蔽線係相互交錯；以及
    封裝層，係形成於該承載件上以包覆該電子元件及屏蔽線。
  2. 如申請專利範圍第1項所述之電子封裝件，其中，各該屏蔽線之相對兩端部係分別連接至該承載件。
  3. 如申請專利範圍第1項所述之電子封裝件，其中，該屏蔽線係為打線製程之銲線。
  4. 如申請專利範圍第1項所述之電子封裝件，其中，該複數屏蔽線係相對該電子元件沿其中一方向佈設。
  5. 如申請專利範圍第1項所述之電子封裝件，其中，該複數屏蔽線係相對該電子元件沿多方向佈設。
  6. 如申請專利範圍第1項所述之電子封裝件，其中，該屏蔽線係部分外露於該封裝層。
  7. 如申請專利範圍第1項所述之電子封裝件，其中，該屏蔽線係為弧線，且其弧頂係外露於該封裝層。
  8. 如申請專利範圍第7項所述之電子封裝件，其中，該弧頂係齊平該封裝層之表面。
  9. 如申請專利範圍第1項所述之電子封裝件，復包括設於該封裝層上之屏蔽件。
  10. 一種電子封裝件之製法，係包括：
    提供一設有至少一電子元件之承載件，且該電子元件係電性連接該承載件；
    形成複數屏蔽線於該承載件上，且令該屏蔽線跨越該電子元件，其中，該複數屏蔽線係相互交錯；以及
    形成封裝層於該承載件上，以令該封裝層包覆該電子元件及屏蔽線。
  11. 如申請專利範圍第10項所述之電子封裝件之製法，其中，各該屏蔽線之相對兩端部係分別連接至該承載件。
  12. 如申請專利範圍第10項所述之電子封裝件之製法，其中，該屏蔽線係為打線製程之銲線。
  13. 如申請專利範圍第10項所述之電子封裝件之製法，其中，該複數屏蔽線係沿其中一方向形成。
  14. 如申請專利範圍第10項所述之電子封裝件之製法，其中，該複數屏蔽線係沿多方向形成。
  15. 如申請專利範圍第10項所述之電子封裝件之製法，其中，該屏蔽線係部分外露於該封裝層。
  16. 如申請專利範圍第10項所述之電子封裝件之製法，其中，該屏蔽線係為弧線，且其弧頂係外露於該封裝層。
  17. 如申請專利範圍第16項所述之電子封裝件之製法，其中，該弧頂係齊平該封裝層之表面。
  18. 如申請專利範圍第10項所述之電子封裝件之製法，復包括形成屏蔽件於該封裝層上。
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