TW202349642A - 電子封裝件及其製法 - Google Patents

電子封裝件及其製法 Download PDF

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TW202349642A
TW202349642A TW111122068A TW111122068A TW202349642A TW 202349642 A TW202349642 A TW 202349642A TW 111122068 A TW111122068 A TW 111122068A TW 111122068 A TW111122068 A TW 111122068A TW 202349642 A TW202349642 A TW 202349642A
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Taiwan
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electronic
package
shielding
manufacturing
load
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TW111122068A
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TWI831241B (zh
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吳哲齊
李建唐
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矽品精密工業股份有限公司
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Priority to TW111122068A priority Critical patent/TWI831241B/zh
Priority to CN202210713840.7A priority patent/CN117276250A/zh
Priority to US17/897,673 priority patent/US20230402398A1/en
Publication of TW202349642A publication Critical patent/TW202349642A/zh
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Publication of TWI831241B publication Critical patent/TWI831241B/zh

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Abstract

一種電子封裝件，係於一承載結構上設置一封裝模組及一屏蔽件，以令該屏蔽件遮蓋該封裝模組之上方與側面，以止擋該封裝模組向外之輻射，避免該承載結構上之其它電子組件遭受該封裝模組之電磁干擾而無法正常傳輸之問題。

Description

電子封裝件及其製法
本發明係有關一種半導體裝置，尤指一種具屏蔽件之電子封裝件及其製法。
隨著半導體技術的演進，半導體產品已開發出不同封裝產品型態，而為提升電性品質，多種半導體產品具有屏蔽之功能，以防止電磁干擾(Electromagnetic Interference，簡稱EMI)產生。
如圖1所示，習知避免EMI之射頻(Radio frequency，簡稱RF)模組1係將複數如射頻及非射頻式晶片之電子元件10藉由導電凸塊11或導線12電性連接在一線路結構15上側，且將金屬框架14設於該線路結構15上並位於各該電子元件10之間，再以係如環氧樹脂之包覆層13包覆各該電子元件10與該金屬框架14，並於該包覆層13上形成一接觸該金屬框架14之金屬層19，之後於該線路結構15下側藉由複數銲錫凸塊17設於一封裝基板18上，以藉由該金屬框架14與該金屬層19保護該些電子元件10免受外界EMI影響。
惟，習知射頻模組1中，該線路結構15因配置有天線層150而會產生向外之輻射F，致使該封裝基板18上之其它天線組件之訊號將受到該射頻模組1之電磁干擾，而使產品無法正常運作。
因此，如何克服上述習知技術的問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失，本發明係提供一種電子封裝件，係包括：封裝模組，係設於該承載結構之其中一側上，其中，該封裝模組係包含有一電性連接該承載結構之線路結構、至少一設於該線路結構上並電性連接該線路結構之電子元件、以及設於該線路結構上並圍繞該電子元件之屏蔽體；屏蔽件，係設於該承載結構上以遮蓋該封裝模組，其中，該屏蔽件係包含一遮蓋該電子元件之金屬片及至少一用以支撐該金屬片於該承載結構上之屏蔽腳，以令該屏蔽腳遮蓋該封裝模組之側面；以及散熱件，係設於該承載結構上且連接該屏蔽件。
本發明亦提供一種電子封裝件之製法，係包括：提供承載結構與封裝模組，該封裝模組係包含有一線路結構、及至少一設於該線路結構上並電性連接該線路結構之電子元件；將該封裝模組設於該承載結構之其中一側上，使該線路結構電性連接該承載結構；以及將屏蔽件設於該承載結構上，以令該屏蔽件遮蓋該封裝模組，其中，該屏蔽件係包含一遮蓋該電子元件之金屬片及至少一用以支撐該金屬片於該承載結構上之屏蔽腳，使該屏蔽腳遮蓋該封裝模組之側面。
前述之製法中，該線路結構上復設置屏蔽體。例如，該屏蔽體圍繞該電子元件；或者，該線路結構上係配置複數該電子元件，以令該屏蔽體位於相鄰兩該電子元件之間。亦或，該屏蔽體接觸該金屬片。
前述之電子封裝件及其製法中，該封裝模組藉由複數導電元件設於該承載結構上。
前述之電子封裝件及其製法中，該承載結構之另一側設有複數銲球。
前述之電子封裝件及其製法中，該承載結構係具有至少一電性連接該屏蔽腳之接地部。
前述之製法中，復包括設於該承載結構上之散熱件，其連接該屏蔽件。例如，該承載結構係具有至少一電性連接該散熱件之接地部。
由上可知，本發明之電子封裝件及其製法中，主要藉由該屏蔽件(或屏蔽腳)遮擋該封裝模組之側面，以有效止擋該線路結構向外之輻射，避免該承載結構上之其它電子組件遭受該封裝模組之電磁干擾而無法正常傳輸之問題，故相較於習知技術，本發明之電子封裝件可提升產品之可靠性。
1:射頻模組
10,20:電子元件
11:導電凸塊
12:導線
13,23:包覆層
14:金屬框架
15,25:線路結構
150:天線層
17:銲錫凸塊
18:封裝基板
19:金屬層
2:電子封裝件
2a:封裝模組
20a:作用面
20b:非作用面
200:電極墊
21:導電體
22:保護層
23a:第一表面
23b:第二表面
230:穿孔
24:屏蔽體
250:介電層
251:線路層
252:天線部
26:凸塊底下金屬層
27:導電元件
270:底膠
28:承載結構
28a:接地部
280:銲球
281:止擋件
29:屏蔽件
290:金屬片
291:屏蔽腳
3:天線組件
30:散熱件
300:散熱體
301:支撐腳
31:黏著層
9:承載件
90:離型層
F:輻射
S:切割路徑
圖1係為習知射頻模組之剖視示意圖。
圖2A至圖2H係為本發明之電子封裝件之製法之剖視示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「上」、「第一」、「第二」、「一」等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
圖2A至圖2H係為本發明之電子封裝件2之製法的剖面示意圖。
如圖2A所示，於一承載件9上設置複數相互間隔排列之電子元件20。
所述之承載件9例如為半導體材質(如矽或玻璃)之板體，其上以例如塗佈方式形成有一離型層90，以結合該複數電子元件20。
所述之電子元件20係為主動元件、被動元件或其組合者，且該主動元件係例如半導體晶片，而該被動元件係例如電阻、電容及電感。
於本實施例中，該電子元件20係為半導體晶片，如為圖形處理器(graphics processing unit，簡稱GPU)、高頻寬記憶體(High Bandwidth Memory，稱HBM)等，其具有相對之作用面20a及非作用面20b，並以其非作用面20b藉由膠材(圖略)設於該離型層90上，且該作 用面20a具有複數電極墊200。進一步，該電極墊200上可形成如銅柱或錫球之導電體21，且該作用面20a上設有一保護層22，使該保護層22覆蓋該些電極墊200與該些導電體21，並令該導電體21之端面外露於該保護層22。
再者，該保護層22係為絕緣材，如氮化矽(SiN)等之氮化物，且可藉由整平製程，如研磨方式，移除該保護層22之部分材質及該導電體21之部分材質，使該保護層22之頂面齊平該導電體21之端面，以令該導電體21之端面外露出該保護層22。
如圖2B所示，形成一包覆層23於該承載件9上，使該包覆層23包覆該些電子元件20，其中，該包覆層23係具有相對之第一表面23a與第二表面23b，且令該保護層22與該導電體21之端面外露出該包覆層23之第一表面23a，並令該包覆層23以其第二表面23b結合至該承載件9上。
於本實施例中，該包覆層23係為絕緣材，如聚醯亞胺(polyimide，簡稱PI)、乾膜(dry film)、如環氧樹脂(epoxy)之封裝膠體或封裝材(molding compound)。例如，該包覆層23之製程可選擇液態封膠(liquid compound)、噴塗(injection)、壓合(lamination)或模壓(compression molding)等方式形成於該承載件9之離型層90上。
再者，可藉由整平製程，使該包覆層23之第一表面23a齊平該保護層22之頂面與該導電體21之端面，以令該導電體21之端面外露出該包覆層23之第一表面23a。例如，該整平製程係藉由研磨方式，移除該保護層22之部分材質、該導電體21之部分材質與該包覆層23之部分材質。
如圖2C所示，以雷射方式於該包覆層23之第一表面23a上形成複數穿孔230，以令該些穿孔230連通該包覆層23之第一表面23a與第二表面23b，使該承載件9(或該離型層90)之部分表面外露於該些穿孔230。
於本實施例中，該些穿孔230係圍繞該些電子元件20，以於各該電子元件20之間配置有至少一穿孔230。
如圖2D所示，形成金屬材於該些穿孔230中，以令該些穿孔230中之金屬材作為屏蔽體24，使各該電子元件20之間配置有屏蔽體24。
於本實施例中，該屏蔽體24係為電鍍金屬、填充材料或導電膠，其呈柱狀或牆狀。
如圖2E所示，形成一線路結構25於該包覆層23之第一表面23a與該複數電子元件20之作用面20a上，且令該線路結構25電性連接該複數電子元件20。
於本實施例中，該線路結構25係包含至少一介電層250及結合該介電層250之線路層251，且該線路層251具有天線部252。例如，形成該介電層250之材質係如聚對二唑苯(Polybenzoxazole，簡稱PBO)、聚醯亞胺(Polyimide，簡稱PI)、預浸材(Prepreg，簡稱PP)或其它等之介電材，且可採用線路重佈層(redistribution layer，簡稱RDL)製程形成該線路層251與該介電層250。
再者，最內側之線路層251藉由該些導電體21電性連接該些電極墊200，且於最外側之線路層251上具有凸塊底下金屬層(Under Bump Metallurgy，簡稱UBM)26，以結合複數如銲球之導電元件27，供後續製程中接置其它外部元件。
又，該些屏蔽體24可電性連接該線路層251或未電性連接該線路層251。
如圖2F所示，移除該承載件9與該離型層90，以外露該些屏蔽體24、該包覆層23之第二表面23b與該電子元件20之非作用面20b，且沿如圖2E所示之切割路徑S進行切單製程，以獲取包含複數電子元件20之封裝模組2a。
如圖2G所示，將該封裝模組2a藉由該些導電元件27設於一承載結構28上。
所述之承載結構28係為封裝用載板形式，例如為具有核心層與線路結構之封裝基板、無核心層(coreless)形式線路結構之封裝基板、具導電矽穿孔(Through-silicon via，簡稱TSV)之矽中介板(Through Silicon interposer，簡稱TSI)或其它板型，其包含至少一佈線層，如至少一扇出(fan out)型重佈線路層(redistribution layer，簡稱RDL)，其具有接地部28a。應可理解地，該承載結構28亦可為其它承載晶片之板材，如導線架(lead frame)、晶圓(wafer)、或其它具有金屬佈線(routing)之板體等，並不限於上述。
於本實施例中，該承載結構28之載板製程方式繁多，例如，可採用晶圓製程製作線路層，透過化學氣相沉積(Chemical vapor deposition，簡稱CVD)形成氮化矽或氧化矽以作為絕緣層；或者，可採用一般非晶圓製程方式形成線路層，即採用成本較低之高分子介電材作為絕緣層，如聚醯亞胺(Polyimide，簡稱PI)、聚對二唑苯(Polybenzoxazole，簡稱PBO)、預浸材(Prepreg，簡稱PP)、封裝膠體(molding compound)、感光型介電層或其它材質等以塗佈方式形成之。
再者，該承載結構28於其下側可形成複數銲球280，以接置一如電路板之電子裝置(圖略)。
又，可藉由底膠270包覆該些導電元件27。進一步，於該承載結構28上可依需求配置止擋件281，以限制該底膠270之流動區域。
如圖2H所示，設置一屏蔽件29於該承載結構28上以遮蓋該封裝模組2a之上方與側面，令該屏蔽件29接觸該屏蔽體24以遮蓋該些電子元件20與線路結構25之側面。
於本實施例中，該屏蔽件29係為架體，其包含金屬片290及至少一用以支撐該金屬片290於該承載結構28上之屏蔽腳291，其形成材質係為金屬或非金屬(如石墨)之導電材質。例如，該屏蔽腳291並未接觸該封裝模組2a之側面，使該屏蔽腳291與該封裝模組2a之間保持間隔，如空曠空間，供於該屏蔽腳291與該封裝模組2a之間置放其它功能元件，如被動元件，以提升該承載結構28上之佈線設計之靈活度。
再者，該金屬片290係接觸該屏蔽體24與該電子元件20之非作用面20b，且該屏蔽腳291係可電性連接該接地部28a。較佳者，該金屬片290覆蓋該封裝模組2a之全部上方以遮蓋該電子元件20之全部非作用面20b。
又，可於該承載結構28上設置一散熱件30，其連接該屏蔽件29以對該電子元件20散熱。例如，該散熱件30之結構形式係對應該屏蔽件29之結構形式。
所述之散熱件30係具有一散熱體300與複數設於該散熱體300下側之支撐腳301，該散熱體30係為散熱片型式，並以下側結合該屏蔽件29之金屬片290，且該支撐腳301係藉由如絕緣膠或導電膏之黏著層31結合於該承載結構28上。
另外，該支撐腳301亦可電性連接該接地部28a，且該些止擋件281係位於該支撐腳301與該屏蔽腳291之間。
因此，本發明之製法，主要藉由該屏蔽件29(或屏蔽腳291)遮擋該封裝模組2a(或該線路結構25)之側面，以有效止擋該線路結構25之天線部252向外之輻射，使該承載結構28上之其它天線組件3免於遭受該封裝模組2a之電磁干擾，故相較於習知技術，本發明之電子封裝件2能有效維持產品之正常運作，以提升產品之可靠性。
進一步，本發明之電子封裝件2藉由多組屏蔽機制(該屏蔽件29與該屏蔽體24)之配置，以更有效保護該電子元件20免受電磁干擾之影響，使產品之可靠性更佳。
本發明亦提供一種電子封裝件2，係包括：一承載結構28、一封裝模組2a以及一屏蔽件29。
所述之封裝模組2a係設於該承載結構28之其中一側上，其中，該封裝模組2a係包含有一電性連接該承載結構28之線路結構25，以及至少一設於該線路結構25上並電性連接該線路結構25之電子元件20。
所述之屏蔽件29係設於該承載結構28上以遮蓋該封裝模組2a，其中，該屏蔽件29係包含一遮蓋該電子元件20之金屬片290及至少一用以支撐該金屬片290於該承載結構28上之屏蔽腳291，以令該屏蔽腳291遮蓋該封裝模組2a之側面。
於一實施例中，該線路結構25上復設置至少一屏蔽體24。例如，該屏蔽體24圍繞該電子元件20。或者，該線路結構25上係配置複數該電子元件20，以令該屏蔽體24位於相鄰兩該電子元件20之間。亦或，該屏蔽體24接觸該金屬片290。
於一實施例中，該封裝模組2a藉由複數導電元件27設於該承載結構28上。
於一實施例中，該承載結構28之另一側設有複數銲球280。
於一實施例中，該承載結構28係具有至少一電性連接該屏蔽腳291之接地部28a。
於一實施例中，所述之電子封裝件2復包括設於該承載結構28上之散熱件30，其連接該屏蔽件29。例如，該承載結構28係具有至少一電性連接該散熱件30之接地部28a。
綜上所述，本發明之電子封裝件及其製法，係藉由該屏蔽件(或屏蔽腳)遮擋該封裝模組之側面，以有效止擋該線路結構向外之輻射，避免該承載結構上之其它電子組件遭受該封裝模組之電磁干擾而無法正常傳輸之問題，故相較於習知技術，本發明之電子封裝件能有效提升產品之可靠性。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2:電子封裝件
2a:封裝模組
20:電子元件
23:包覆層
24:屏蔽體
25:線路結構
28:承載結構
28a:接地部
280:銲球
281:止擋件
29:屏蔽件
290:金屬片
291:屏蔽腳
3:天線組件
30:散熱件
300:散熱體
301:支撐腳
31:黏著層

Claims (17)

  1. 一種電子封裝件，係包括：
    承載結構；
    封裝模組，係設於該承載結構之其中一側上，其中，該封裝模組係包含有一電性連接該承載結構之線路結構、至少一設於該線路結構上並電性連接該線路結構之電子元件、以及設於該線路結構上並圍繞該電子元件之屏蔽體；
    屏蔽件，係設於該承載結構上以遮蓋該封裝模組，其中，該屏蔽件係包含一遮蓋該電子元件之金屬片及至少一用以支撐該金屬片於該承載結構上之屏蔽腳，以令該屏蔽腳遮蓋該封裝模組之側面；以及
    散熱件，係設於該承載結構上且連接該屏蔽件。
  2. 如請求項1所述之電子封裝件，其中，該線路結構上係配置複數該電子元件，以令該屏蔽體位於相鄰兩該電子元件之間。
  3. 如請求項1所述之電子封裝件，其中，該屏蔽體接觸該金屬片。
  4. 如請求項1所述之電子封裝件，其中，該封裝模組藉由複數導電元件設於該承載結構上。
  5. 如請求項1所述之電子封裝件，其中，該承載結構之另一側設有複數銲球。
  6. 如請求項1所述之電子封裝件，其中，該承載結構係具有至少一電性連接該屏蔽腳之接地部。
  7. 如請求項1所述之電子封裝件，其中，該承載結構係具有至少一電性連接該散熱件之接地部。
  8. 一種電子封裝件之製法，係包括：
    提供一封裝模組，其中，該封裝模組係包含有一線路結構以及至少一設於該線路結構上並電性連接該線路結構之電子元件；
    將該封裝模組設於一承載結構之其中一側上，使該線路結構電性連接該承載結構；以及
    將屏蔽件設於該承載結構上，以令該屏蔽件遮蓋該封裝模組，其中，該屏蔽件係包含一遮蓋該電子元件之金屬片及至少一用以支撐該金屬片於該承載結構上之屏蔽腳，使該屏蔽腳遮蓋該封裝模組之側面。
  9. 如請求項8所述之電子封裝件之製法，其中，該線路結構上復設置有屏蔽體。
  10. 如請求項9所述之電子封裝件之製法，其中，該屏蔽體圍繞該電子元件。
  11. 如請求項9所述之電子封裝件之製法，其中，該線路結構上係配置複數該電子元件，以令該屏蔽體位於相鄰兩該電子元件之間。
  12. 如請求項9所述之電子封裝件之製法，其中，該屏蔽體接觸該金屬片。
  13. 如請求項8所述之電子封裝件之製法，其中，該封裝模組藉由複數導電元件設於該承載結構上。
  14. 如請求項8所述之電子封裝件之製法，其中，該承載結構之另一側設有複數銲球。
  15. 如請求項8所述之電子封裝件之製法，其中，該承載結構係具有至少一電性連接該屏蔽腳之接地部。
  16. 如請求項8所述之電子封裝件之製法，復包括設於該承載結構上且連接該屏蔽件之散熱件。
  17. 如請求項16所述之電子封裝件之製法，其中，該承載結構係具有至少一電性連接該散熱件之接地部。
TW111122068A 2022-06-14 2022-06-14 電子封裝件及其製法 TWI831241B (zh)

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