TW202406031A - 電子封裝件及其製法 - Google Patents

電子封裝件及其製法 Download PDF

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TW202406031A
TW202406031A TW111127968A TW111127968A TW202406031A TW 202406031 A TW202406031 A TW 202406031A TW 111127968 A TW111127968 A TW 111127968A TW 111127968 A TW111127968 A TW 111127968A TW 202406031 A TW202406031 A TW 202406031A
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Taiwan
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electronic
electronic package
strong
area
conductive pillars
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TW111127968A
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English (en)
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TWI837742B (zh
Inventor
卜昭強
何祈慶
符毅民
王愉博
蔡芳霖
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矽品精密工業股份有限公司
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Priority to TW111127968A priority Critical patent/TWI837742B/zh
Priority to CN202210931608.0A priority patent/CN117524993A/zh
Priority to US17/950,914 priority patent/US20240038685A1/en
Publication of TW202406031A publication Critical patent/TW202406031A/zh
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Publication of TWI837742B publication Critical patent/TWI837742B/zh

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Abstract

一種電子封裝件，係於包覆層中嵌埋電子結構與複數導電柱，且於該包覆層上形成線路結構，並於該包覆層之側面結合強固件，同時將複數電子元件設於該線路結構上且電性連接該線路結構，以令該電子結構藉由該線路結構電性橋接任二電子元件，俾藉由該強固件之設計，以增強該電子封裝件之結構強度，避免發生翹曲。

Description

電子封裝件及其製法
本發明係有關一種半導體裝置，尤指一種具橋接元件之電子封裝件及其製法。
隨著電子產業的蓬勃發展，電子產品也逐漸邁向多功能、高性能的趨勢。同時，目前應用於晶片封裝領域之技術，包含有例如晶片尺寸構裝(Chip Scale Package，簡稱CSP)、晶片直接貼附封裝(Direct Chip Attached，簡稱DCA)或多晶片模組封裝(Multi-Chip Module，簡稱MCM)等覆晶型態的封裝模組等。
圖1係為習知半導體封裝件1之剖面示意圖，該半導體封裝件1包括：包覆層15、一嵌埋於該包覆層15中之橋接晶片10與複數導電柱13、一設於該包覆層15上側15a並電性連接該橋接晶片10與複數導電柱13之第一佈線結構11、複數設於該第一佈線結構11上之電子元件16、用以包覆複數該電子元件16之封裝層18、一設於該包覆層15下側15b並電性連接該複數導電柱13之第二佈線結構12、以及複數設於該第二佈線結構12上且電性連接該第二佈線結構12之導電元件17。
所述之第一佈線結構11係包括複數絕緣層110、設於該複數絕緣層110上之複數佈線層111及電性連接各該佈線層111之複數導電盲孔112，以令該複數導電盲孔112電性連接該複數導電柱13與該複數佈線層111，且最外層之佈線層111具有複數微墊(u-pad)規格之電性接觸墊113。
所述之電子元件16係為功能晶片，其具有複數電極墊160，以結合如微凸塊(u-bump)規格之導電凸塊161，使該電子元件16藉由覆晶方式將導電凸塊161銲接於該電性接觸墊113上，再以底膠162包覆該些導電凸塊161。
惟，習知半導體封裝件1中，隨著產品功能性需求大增，該電子元件16之功能需求也隨之增加，故該第一佈線結構11及該第二佈線結構12之線路佈設面積隨之增大，於此情況下，整體版面之寬度增加，致使結構強度極弱，因而容易受高溫影響而產生翹曲(warpage)，造成該佈線層111或該第二佈線結構12之線路斷裂。
因此，如何克服上述習知技術之問題，實已成為目前業界亟待克服之難題。
鑑於上述習知技術之種種缺失，本發明係提供一種電子封裝件，係包括：一包覆層，係具有相對之第一表面與第二表面及鄰接該第一表面與第二表面之側面；電子結構，係嵌埋於該包覆層中；複數導電柱，係嵌埋於該包覆層中；強固件，係設於該包覆層之側面上；線路結構，係形成於該包覆層之第一表面上且電性連接該複數導電柱與該電子結構而未電性連接該強固件；以及複數 電子元件，係設於該線路結構上且電性連接該線路結構，以令該電子結構作為橋接元件藉由該線路結構而電性橋接該複數電子元件之至少二者。
本發明亦提供一種電子封裝件之製法，係包括：於一承載件上形成複數導電柱，並設置強固件及電子結構；形成包覆層於該承載件上，以令該包覆層包覆該複數導電柱、強固件及電子結構；形成線路結構於該包覆層之第一表面上，且令該線路結構電性連接該複數導電柱與該電子結構而未電性連接該強固件；設置複數電子元件於該線路結構上，且該複數電子元件電性連接該線路結構，以令該電子結構作為橋接元件藉由該線路結構而電性橋接該複數電子元件之至少二者；以及移除該承載件。
前述之電子封裝件及其製法中，該強固件係為金屬框架或非金屬材質之框架。
前述之電子封裝件及其製法中，該強固件之寬度係至少35微米。
前述之電子封裝件及其製法中，該強固件之寬度係大於或等於各該導電柱之寬度。
前述之電子封裝件及其製法中，該強固件係呈環形。
前述之電子封裝件及其製法中，該強固件係環繞該電子結構。
前述之電子封裝件及其製法中，該強固件係具有至少一導引孔。
前述之電子封裝件及其製法中，該電子結構係定義有水平中線，以將該包覆層區分成相對之第一區域與第二區域，以令位於該第一區域中之導電柱的數量多於位於該第二區域中之導電柱的數量，使該強固件對應該第二區域處的寬度大於該強固件對應該第一區域處之寬度。
前述之電子封裝件及其製法中，復包括於該包覆層上形成複數導電元件，以令該複數導電元件電性連接該複數導電柱而未電性連接該強固件。
由上可知，本發明之電子封裝件及其製法中，主要藉由該強固件之設計，以增強該電子封裝件之結構強度，故相較於習知技術，本發明可避免該電子封裝件發生翹曲之問題。
1:半導體封裝件
10:橋接晶片
100,160,260:電極墊
11:第一佈線結構
110,200,24:絕緣層
111:佈線層
112:導電盲孔
113,202:電性接觸墊
12:第二佈線結構
13,23:導電柱
15,25:包覆層
15a:上側
15b:下側
16,26:電子元件
161,261:導電凸塊
162,262:底膠
17,27:導電元件
18,28:封裝層
2:電子封裝件
2a:電子結構
20:線路結構
201:線路重佈層
21:電子主體
21a:第一導電體
21b:第一保護層
210:導電穿孔
22:線路部
22a:第二導電體
22b:第二保護層
220:鈍化層
221:導電跡線
23a,23b:端面
25a:第一表面
25b:第二表面
25c:側面
26:電子元件
26a:作用面
27a:銲錫材料
270:金屬體
271:銅柱
29,39,491,492,493:強固件
290:導引孔
3:封裝基板
30:銲球
31:功能件
49:遮罩結構
490:蓋體
9:承載件
90:離型層
91:金屬層
A1:第一區域
A2:第二區域
D,D1,D2,R:寬度
L:水平中線
S:切割路徑
圖1係為習知半導體封裝件之剖視示意圖。
圖2A至圖2H係為本發明之電子封裝件之製法之剖視示意圖。
圖2B-1係為圖2B之局部上視示意圖。
圖2C-1係為圖2C之局部上視示意圖。
圖2H-1係為圖2H之另一態樣之剖視示意圖。
圖3係為圖2H之後續製程之剖視示意圖。
圖4A係為圖2B之製程之另一實施例之剖視示意圖。
圖4B係為圖4A之局部立體示意圖。
圖4C係為圖4B之另一態樣之平面示意圖。
圖4D係為圖4B之其它態樣之立體示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的 下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「上」、「第一」、「第二」、「一」等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
圖2A至圖2H係為本發明之電子封裝件2之製法之剖面示意圖。
如圖2A所示，提供一電子結構2a及一其上配置有絕緣層24之承載件9，並於該承載件9上形成複數導電柱23。
於本實施例中，該承載件9例如為半導體材質(如矽或玻璃)之板體，其上以例如塗佈方式依序形成有一離型層90與一如鈦/銅之金屬層91，使該絕緣層24形成於該金屬層91上。例如，形成該絕緣層24之材質係如聚對二唑苯(Polybenzoxazole，簡稱PBO)、聚醯亞胺(Polyimide，簡稱PI)、預浸材(Prepreg，簡稱PP)或其它等之介電材。
再者，形成該複數導電柱23之材質係為如銅之金屬材或銲錫材，且該複數導電柱23係延伸穿過該絕緣層24以接觸該金屬層91。例如，藉由曝光顯影方式，於該絕緣層24上係形成複數外露該金屬層91之開口，以藉由該金屬層91從該開口中電鍍形成該複數導電柱23。
所述之電子結構2a係包含一電子主體21、一線路部22、形成於該電子主體21上之複數第一導電體21a、及形成於該線路部22上且電性連接該線路部22之複數第二導電體22a。接著，將一第一保護層21b形成於該電子主體21上，以令該第一保護層21b包覆該複數第一導電體21a，且將一第二保護層22b形成於該線路部22上以令該第二保護層22b包覆該複數第二導電體22a。
於本實施例中，該電子主體21係為矽基材，如半導體晶片，其具有複數貫穿該電子主體21之導電穿孔210，如導電矽穿孔(Through-silicon via，簡稱TSV)，以電性連接該線路部22與該複數第一導電體21a。例如，該線路部 22係包含至少一鈍化層220及結合該鈍化層220之導電跡線221，以令該導電跡線221電性連接該導電穿孔210與該複數第二導電體22a。應可理解地，有關具有該導電穿孔210之元件結構之態樣繁多，並無特別限制。
再者，該第一導電體21a與第二導電體22a係為如銅柱之金屬柱，且該第一保護層21b係為絕緣膜或聚醯亞胺(Polyimide，簡稱PI)材質，其未外露該第一導電體21a，而該第二保護層22b係為非導電膜(Non-Conductive Film，簡稱NCF)或其它易於黏著該絕緣層24之材質。例如，於該電子結構2a之線路部22上係先製作該第二導電體22a，再黏貼該非導電膜(該第二保護層22b)。應可理解地，該電子結構2a亦可不形成該第二保護層22b，而於後續(如圖2B所示之製程中)使用傳統點膠(即底膠)製程，但該第二導電體22a係採用小間距(Pitch)、低高度及高密度等配置規格，因而不利於傳統底膠(underfill)之毛細流動，故選擇非導電膜作為該第二保護層22b之方式較佳。
如圖2B所示，將該電子結構2a以其上之第二保護層22b結合於該絕緣層24上，且將至少一強固件29設於該絕緣層24上。
於本實施例中，該強固件29係為金屬框架或非金屬材之框架，其以黏貼方式或其它方式固定於該絕緣層24上。例如，該強固件29係呈環形，如圖2B-1所示，以圍繞該電子結構2a與該些導電柱23。
再者，該強固件29之寬度D係至少35微米(um)，且該強固件29之寬度D係大於該導電柱23之寬度R。
另請參閱圖4A，於其它實施例中，強固件491亦可為遮罩結構49之一部分，其設於一蓋體490上，以令該強固件491立設於該絕緣層24上，使該蓋體490遮蓋該電子結構2a與該些導電柱23。例如，該蓋體490可為矩形片狀，且該強固件491為牆狀(如圖4B所示)，亦可為柵狀(如圖4C所示之強固件492)或柱狀(如圖4D所示之設於該蓋體490角落處之強固件493)。
因此，有關該強固件29,491,492,493之態樣繁多，並無特別限制。
如圖2C所示，接續圖2B之製程，形成一包覆層25於該絕緣層24上，以令該包覆層25包覆該電子結構2a、該強固件29與該些導電柱23，其中，該包覆層25係具有相對之第一表面25a與第二表面25b，且令該第一保護層21b、該第一導電體21a之端面與該導電柱23之端面23a外露於該包覆層25之第一表面25a，並令該包覆層25以其第二表面25b結合至該絕緣層24上。
於本實施例中，該包覆層25係為絕緣材，如聚醯亞胺(polyimide，簡稱PI)、乾膜(dry film)、如環氧樹脂(epoxy)之封裝膠體或封裝材(molding compound)。例如，該包覆層25之製程可選擇液態封膠(liquid compound)、噴塗(injection)、壓合(lamination)或模壓(compression molding)等方式形成於該絕緣層24上。
再者，可藉由整平製程，使該包覆層25之第一表面25a齊平該第一保護層21b、該強固件29、該導電柱23之端面23a與該第一導電體21a之端面，以令該強固件29、該導電柱23之端面23a與該第一導電體21a之端面外露於該包覆層25之第一表面25a。例如，該整平製程係藉由研磨方式，移除該強固件29之部分材質、該第一保護層21b之部分材質、該導電柱23之部分材質、該第一導電體21a之部分材質與該包覆層25之部分材質。應可理解地，若接續圖4A之製程，可藉由整平製程，一併研磨移除該蓋體490，以呈現如圖2C所示之態樣，使該強固件491,492,493(如同圖2C所示之強固件29)齊平及外露於該包覆層25之第一表面25a。
又，如圖2C-1所示，該電子結構2a係定義有水平中線L，以將該包覆層25區分成相對之第一區域A1與第二區域A2，以當該第一區域A1中之該導電柱23之數量多於該第二區域A2中的該導電柱23之數量時，該強固件29對應該第二區域A2處的寬度D2大於該強固件29對應該第一區域A1處之寬度D1。
另外，該強固件29可具有至少一導引孔290，供該包覆層25經由該導引孔290流入該強固件29內，以包覆該電子結構2a與該些導電柱23。例如，該強固件29配置複數個導引孔290而呈非連續環狀，以利於該包覆層25之膠材之流動，且該導引孔290之位置係偏離該電子結構2a之水平中線L，以避免該包覆層25之膠材直接衝撞該電子結構2a而導致該電子結構2a碎裂之問題。
如圖2D所示，形成一線路結構20於該包覆層25之第一表面25a上，且令該線路結構20電性連接該複數導電柱23與該複數第一導電體21a，而未電性連接該強固件29。
於本實施例中，該線路結構20係包括至少一絕緣層200及設於該絕緣層200上之線路重佈層(redistribution layer，簡稱RDL)201，其中，最外層之絕緣層200可作為防銲層，且令最外層之線路重佈層201外露於該防銲層，俾供作為電性接觸墊202，如微墊(micro pad，俗稱μ-pad)。
再者，形成該線路重佈層201之材質係為銅，且形成該絕緣層200之材質係為如聚對二唑苯(Polybenzoxazole，簡稱PBO)、聚醯亞胺(Polyimide，簡稱PI)、預浸材(Prepreg，簡稱PP)等之介電材、或如綠漆、油墨等之防銲材。
如圖2E所示，設置複數電子元件26於該線路結構20上，再以一封裝層28包覆該些電子元件26。
於本實施例中，該電子元件26係為主動元件、被動元件或其二者組合，且該主動元件係例如半導體晶片，而該被動元件係例如電阻、電容及電感。於一實施態樣中，該電子元件26係例如為圖形處理器(graphics processing unit，簡稱GPU)、高頻寬記憶體(High Bandwidth Memory，簡稱HBM)等半導體晶片，並無特別限制，且該電子結構2a係作為橋接元件(Bridge die)，其藉由該第一導電體21a電性連接該線路結構20，以電性橋接至少二電子元件26。
再者，該電子元件26之作用面26a係具有複數電極墊260，以藉由複數含有銲錫材料之導電凸塊261電性連接該電性接觸墊202，且該封裝層28可同時包覆該些電子元件26與該些導電凸塊261。於本實施例中，可形成一凸塊底下金屬層(Under Bump Metallurgy，簡稱UBM)(圖略)於該電性接觸墊202上，以利於結合該導電凸塊261。
又，該封裝層28係為絕緣材，如聚醯亞胺(polyimide，簡稱PI)、乾膜(dry film)、如環氧樹脂(epoxy)之封裝膠體或封裝材(molding compound)，其可用壓合(lamination)或模壓(molding)之方式形成於該線路結構20上。應可理解地，形成該封裝層28之材質可相同或不相同該包覆層25之材質。
另外，亦可先形成底膠262於該電子元件26與該線路結構20之間以包覆該些導電凸塊261，再形成該封裝層28以包覆該底膠262與該電子元件26。
如圖2F所示，移除該承載件9及其上之離型層90，再移除該金屬層91，以外露出該絕緣層24及導電柱23之另一端面23b。
於本實施例中，於剝離該離型層90時，藉由該金屬層91作為阻障之用，以避免破壞該絕緣層24，且待移除該承載件9及其上之離型層90後，再以蝕刻方式移除該金屬層91，此時，該導電柱23外露於該絕緣層24，而該電子結構2a與該強固件29並未外露於該絕緣層24。
如圖2G所示，形成複數導電元件27於該絕緣層24上，且令該些導電元件27電性連接該複數導電柱23與該複數第二導電體22a。
於本實施例中，於該絕緣層24上進行開孔製程，以令該些第二導電體22a外露於該絕緣層24，俾供結合該複數導電元件27。例如，藉由雷射方式於該絕緣層24上形成複數開孔，以令該些第二導電體22a外露出該些開孔，使該複數導電元件27形成於該複數開孔中以電性連接該第二導電體22a，其中，各該 導電元件27係包含一金屬體(如UBM或線路)270、及設結合該金屬體270之銅柱271，以於該銅柱271之端面上形成如銲錫凸塊或銲球之銲錫材料27a。
應可理解的是，當接點(IO)之數量不足(如該導電元件27的數量已無法滿足產品需求)時，仍可於該絕緣層24上藉由RDL製程進行增層作業。
如圖2H所示，沿如圖2G所示之切割路徑S進行切單製程，以獲取複數電子封裝件2，其中，該強固件29位於該切割路徑S上，故於切單製程後，該包覆層25將形成有複數鄰接該第一表面25a與第二表面25b之側面25c，且該強固件29係設於該包覆層25之側面25c上以外露於該包覆層25。
於本實施例中，可藉由整平製程，如研磨方式，移除該封裝層28之部分材質，使該封裝層28之上表面齊平該電子元件26之上表面，以令該電子元件26外露於該封裝層28。
再者，該強固件29可依需求佈設於該絕緣層24上之任意位置。例如圖2H-1所示，將該強固件39設於該導電柱23與該電子結構2a之間，且嵌埋於該包覆層25中。
又，於後續製程中，可將該電子封裝件2藉由該些導電元件27設置於一封裝基板3上，如圖3所示，且該封裝基板3下側進行植球製程以形成複數如銲球30，供該封裝基板3以其複數銲球30設於一電路板(圖略)上。
另外，該封裝基板3上可依需求設置功能件31，如金屬框，以消除應力集中之問題而避免該封裝基板3發生翹曲之情況。
因此，本發明之製法主要藉由在形成該包覆層25前，於該絕緣層24上設置該強固件29,39，以增強該電子封裝件2於製程中之結構強度，故相較於習知技術，本發明能有效避免該電子封裝件2於製程之前後發生翹曲之問題。
再者，該電子結構2a作為橋接元件(Bridge die)，以直接電性導通上方至少兩個主動晶片(電子元件26)，使電性路徑縮短，且各接點(IO)或各電 性接觸墊202之間距(pitch)可依需求有效縮減，而該線路結構20之上下層之間的電性連接用的線路重佈層201之層數也可變少，以增加製程良率。
又，該電子結構2a具有導電穿孔210，使部分電性路徑(如電源)可透過該電子結構2a直接上下傳遞至所需之處(如該封裝基板3或該電子元件26)，以縮短電性路徑，而提升電性表現。
本發明亦提供一種電子封裝件2，係包括：一包覆層25、一電子結構2a、複數導電柱23、至少一強固件29,39、一線路結構20以及複數電子元件26。
所述之包覆層25係具有相對之第一表面25a與第二表面25b。
所述之電子結構2a係嵌埋於該包覆層25中。
所述之導電柱23係嵌埋於該包覆層25中。
所述之強固件29,39係結合該包覆層25上。
所述之線路結構20係形成於該包覆層25之第一表面25a上且電性連接該複數導電柱23與該電子結構2a而未電性連接該強固件29,39。
所述之電子元件26係設於該線路結構20上且電性連接該線路結構20，以令該電子結構2a作為橋接元件，使該橋接元件藉由該線路結構20電性橋接該複數電子元件26之至少二者。
於一實施例中，該強固件29,39係為金屬框架或非金屬材質之框架。
於一實施例中，該強固件29,39之寬度D,D1,D2係至少35微米。
於一實施例中，該強固件29,39之寬度D,D1,D2係大於或等於該導電柱23之寬度R。
於一實施例中，該強固件29,39係呈環形。
於一實施例中，該強固件29,39係環繞該電子結構。
於一實施例中，該強固件29,39係具有至少一導引孔290。
於一實施例中，該電子結構2a係定義有一水平中線L，以將該包覆層25區分成相對之第一區域A1與第二區域A2，以令該水平中線L所區分之第一區域A1中之該導電柱23之數量多於該水平中線L所區分之第二區域A2中的導電柱23之數量，使該強固件29對應該水平中線L所區分之第二區域A2處的寬度D2大於該強固件29對應該水平中線L所區分之第一區域A1處之寬度D1。
於一實施例中，所述之電子封裝件2復包括複數設於該包覆層25第二表面25b上之導電元件27，其電性連接該複數導電柱23而未電性連接該強固件29,39。
綜上所述，本發明之電子封裝件及其製法，係藉由該強固件之設計，以增強該電子封裝件之結構強度，故本發明能有效避免該電子封裝件發生翹曲之問題。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2:電子封裝件
2a:電子結構
20:線路結構
23:導電柱
25:包覆層
25a:第一表面
25b:第二表面
25c:側面
26:電子元件
27:導電元件
28:封裝層
29:強固件

Claims (20)

  1. 一種電子封裝件，係包括：
    一包覆層，係具有相對之第一表面與第二表面；
    電子結構，係嵌埋於該包覆層中；
    複數導電柱，係嵌埋於該包覆層中；
    強固件，係結合該包覆層；
    線路結構，係形成於該包覆層之第一表面上且電性連接該複數導電柱與該電子結構而未電性連接該強固件；以及
    複數電子元件，係設於該線路結構上且電性連接該線路結構，以令該電子結構作為橋接元件藉由該線路結構而電性橋接該複數電子元件之至少二者。
  2. 如請求項1所述之電子封裝件，其中，該強固件係為金屬框架。
  3. 如請求項1所述之電子封裝件，其中，該強固件係為非金屬材質之框架。
  4. 如請求項1所述之電子封裝件，其中，該強固件之寬度係至少35微米。
  5. 如請求項1所述之電子封裝件，其中，該強固件之寬度係大於或等於各該導電柱之寬度。
  6. 如請求項1所述之電子封裝件，其中，該強固件係呈環形。
  7. 如請求項1所述之電子封裝件，其中，該強固件係環繞該電子結構。
  8. 如請求項1所述之電子封裝件，其中，該強固件係具有至少一導引孔。
  9. 如請求項1所述之電子封裝件，其中，該電子結構係定義有水平中線，以將該包覆層區分成相對之第一區域與第二區域，以令位於該第一區域中之導電柱的數量多於位於該第二區域中之導電柱的數量，使該強固件對應該第二區域處的寬度大於該強固件對應該第一區域處之寬度。
  10. 如請求項1所述之電子封裝件，復包括複數設於該包覆層第二表面上之導電元件，其電性連接該複數導電柱而未電性連接該強固件。
  11. 一種電子封裝件之製法，係包括：
    於一承載件上形成複數導電柱，並設置強固件及電子結構；
    形成包覆層於該承載件上，以令該包覆層包覆該複數導電柱、強固件及電子結構；
    形成線路結構於該包覆層上，且令該線路結構電性連接該複數導電柱與該電子結構而未電性連接該強固件；
    設置複數電子元件於該線路結構上，且該複數電子元件電性連接該線路結構，以令該電子結構作為橋接元件藉由該線路結構而電性橋接該複數電子元件之至少二者；以及
    移除該承載件。
  12. 如請求項11所述之電子封裝件之製法，其中，該強固件係為金屬框架。
  13. 如請求項11所述之電子封裝件之製法，其中，該強固件係為非金屬材質之框架。
  14. 如請求項11所述之電子封裝件之製法，其中，該強固件之寬度係至少35微米。
  15. 如請求項11所述之電子封裝件之製法，其中，該強固件之寬度係大於或等於各該導電柱之寬度。
  16. 如請求項11所述之電子封裝件之製法，其中，該強固件係呈環形。
  17. 如請求項11所述之電子封裝件之製法，其中，該強固件係環繞該電子結構。
  18. 如請求項11所述之電子封裝件之製法，其中，該強固件係具有至少一導引孔。
  19. 如請求項11所述之電子封裝件之製法，其中，該電子結構係定義有水平中線，以將該包覆層區分成相對之第一區域與第二區域，以令位於該第一區域中之導電柱的數量多於位於該第二區域中之導電柱的數量，使該強固件對應該第二區域處的寬度大於該強固件對應該第一區域處之寬度。
  20. 如請求項11所述之電子封裝件之製法，復包括於該包覆層上形成複數導電元件，以令該複數導電元件電性連接該複數導電柱而未電性連接該強固件。
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