TWI822226B - 電子封裝件及其製法 - Google Patents
電子封裝件及其製法 Download PDFInfo
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Abstract
一種電子封裝件,係於具有線路層之承載結構之其中一側配置電子元件、第一導電結構與第二導電結構、及包覆該電子元件、第一導電結構與第二導電結構之包覆層,並使該第一導電結構外露於該包覆層,以依功能需求而外接所需元件。
Description
本發明係有關一種半導體裝置,尤指一種雙側封裝之電子封裝件及其製法。
隨著電子產業的蓬勃發展,電子產品也逐漸邁向多功能、高性能的趨勢。目前第四代(4G)的無線傳輸通訊技術已廣泛應用於各式各樣的消費性電子產品以利接收或發送各種無線訊號。
然而,隨著無線通信發展迅速,以及網路資源流量日趨龐大,所需的無線傳輸頻寬也越來越大,故第五代(5G)無線傳輸技術刻正積極研發中。
圖1係習知半導體封裝件1之立體示意圖。該半導體封裝件1係包括:一配置有半導體元件16與被動元件11之封裝基板10、一如天線之射頻元件12以及封裝膠體13。該半導體元件16係藉由一傳輸線17外接該射頻元件12。該封裝膠體13覆蓋該半導體元件16與該部分傳輸線17。
惟,習知半導體封裝件1中,其依功能需求(如天線)而需配置大量半導體元件16與被動元件11,致使該封裝基板10之佈設面積需隨之增加,
因而增大該半導體封裝件1之體積,導致該半導體封裝件1難以符合輕薄短小之需求。
因此,如何克服上述習知技術的問題,實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失,本發明係提供一種電子封裝件,係包括:具有線路層之承載結構,係定義有相對之第一側與第二側;第二電子元件,係設於該承載結構之第二側上並電性連接該線路層;第一導電結構,係設於該承載結構之第二側上且電性連接該線路層;包覆層,係設於該承載結構之第二側上以包覆該第二電子元件及第一導電結構,該包覆層係定義有一體成形之第一包覆部及第二包覆部,以令該第二電子元件位於該第一包覆部中,且該第一導電結構位於該第二包覆部中,其中,該第一包覆部之高度係高於該第二包覆部之高度,且該第一導電結構係外露於該第二包覆部;以及第二導電結構,係設於該承載結構之第二側上且電性連接該線路層,其中,該第二導電結構之組成係不同於該第一導電結構之組成。
本發明復提供一種電子封裝件之製法,係包括:提供一具有線路層之承載結構,其定義有相對之第一側與第二側;將第二電子元件與第一導電結構設於該承載結構之第二側上,並使該第二電子元件與第一導電結構電性連接該線路層;形成包覆層於該承載結構之第二側上以包覆該第二電子元件及第一導電結構,該包覆層係定義有一體成形之第一包覆部及第二包覆部,且該第一包覆部之高度係高於該第二包覆部之高度,其中,該第二電子元件位於該第一包覆
部中,且該第一導電結構位於該第二包覆部中並外露於該第二包覆部;以及形成第二導電結構於該承載結構之第二側上,以令該第二導電結構電性連接該線路層,其中,該第二導電結構之組成係不同於該第一導電結構之組成。
前述之電子封裝件及其製法中,該第一導電結構係為銲錫球或金屬柱。
前述之電子封裝件及其製法中,該第二導電結構係為導電膠。
前述之電子封裝件及其製法中,該包覆層外露出該承載結構之第二側之局部表面,以接置電子連接器。
前述之電子封裝件及其製法中,該第一包覆部之外觀呈凹凸狀。
前述之電子封裝件及其製法中,復包括將一承載該第一導電結構之線路結構設於該承載結構之第二側上。
前述之電子封裝件及其製法中,復包括將第一電子元件與線路板設於該承載結構之第一側上,並使該第一電子元件與線路板電性連接該線路層。例如,該線路板係為環形框架形式。或者,該線路板上配置複數導電元件,以接置電子裝置。
前述之電子封裝件及其製法中,復包括形成屏蔽結構於該包覆層上,且該屏蔽結構電性連接該第二導電結構。
由上可知,本發明之電子封裝件及其製法中,主要藉由該承載結構之第二側上配置外露於該包覆層之第一導電結構,以依功能需求而外接所需元件,使該承載結構之佈設面積依據包覆層之模具設計即可,而無需增加該承載結構之佈設面積,故相較於習知技術,本發明能減少該電子封裝件之體積,使該電子封裝件符合輕薄短小之需求。
再者,藉由該第二導電結構之設計,以遮擋該第二電子元件周圍,使該第二電子元件與該第一導電結構之間不會相互電磁干擾,進而使終端產品之可靠性更佳。
1:半導體封裝件
10:封裝基板
11:被動元件
12:射頻元件
13:封裝膠體
16:半導體元件
17:傳輸線
2,3a,3b,3c,4:電子封裝件
20:承載結構
20a:第一側
20b:第二側
20c:側面
200:線路層
21:第一電子元件
210:電極墊
211,221,460:導電凸塊
22:第二電子元件
23:線路板
23a:第一表面
23b:第二表面
230:導電體
24,34:包覆層
24a:表面
240:開孔
241,341:第一包覆部
242:第二包覆部
25:導電元件
26,36,461:第一導電結構
27:封裝層
28:第二導電結構
280:凹槽
29:屏蔽結構
30:電子連接器
300:銲錫凸塊
36a:端面
46:線路結構
H1,H2:高度
圖1係為習知半導體封裝件之剖面示意圖。
圖2A至圖2F係為本發明之電子封裝件之製法之剖視示意圖。
圖2A-1係為圖2A之線路板之上視平面示意圖。
圖2E-1係為圖2E之上視平面示意圖。
圖3A、圖3B及圖3C係為圖2F之其它態樣之剖視示意圖。
圖4係為本發明之電子封裝件之另一實施例之剖視示意圖。
以下藉由特定的具體實施例說明本發明之實施方式,熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知,本說明書所附圖式所繪示之結構、比例、大小等,均僅用以配合說明書所揭示之內容,以供熟悉此技藝之人士之瞭解與閱讀,並非用以限定本發明可實施之限定條件,故不具技術上之實質意義,任何結構之修飾、比例關係之改變或大小之調整,在不影響本發明所能產生之功效及所能達成之目的下,均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時,本說明書中所引用之如「上」、「第一」、「第二」及「一」等之用語,亦僅為便於敘述
之明瞭,而非用以限定本發明可實施之範圍,其相對關係之改變或調整,在無實質變更技術內容下,當亦視為本發明可實施之範疇。
圖2A至圖2E係為本發明之電子封裝件2之製法之剖視示意圖。
如圖2A所示,將一線路板23設置於一承載結構20上,且設置至少一第一電子元件21於該承載結構20上。
於本實施例中,該承載結構20係具有相對之第一側20a與第二側20b,且該承載結構20係例如具有核心層之封裝基板(substrate)或無核心層(coreless)式封裝基板,其具有一絕緣基體與結合該絕緣基體之線路層200,該線路層200例如為扇出(fan out)型重佈線路層(redistribution layer,簡稱RDL),其中,該承載結構20內部係佈設有線路(圖略)以導通該第一側20a與第二側20b上之線路層200。例如,形成該線路層200之材質係例如為銅,而形成該絕緣基體之材質係例如為聚對二唑苯(Polybenzoxazole,簡稱PBO)、聚醯亞胺(Polyimide,簡稱PI)、預浸材(Prepreg,簡稱PP)等之介電材。
再者,該第一電子元件21係設於該承載結構20之第一側20a上(本實施例係以複數電子元件21進行說明),且該第一電子元件21係為主動元件、被動元件或其二者組合等,其中,該主動元件係例如半導體晶片,且該被動元件係例如電阻、電容及電感。例如,若該第一電子元件21為半導體晶片時,其電極墊210可藉由複數如銲錫材料之導電凸塊211以覆晶方式設於該線路層200上並電性連接該線路層200;或者,該第一電子元件21之電極墊210可藉由複數銲線(圖略)以打線方式電性連接該線路層200;亦或,該第一電子元件21之電極墊210可直接電性連接該線路層200。然而,有關該第一電子元件21電性連接該承載結構20之方式不限於上述。
又,該線路板23係具有相對之第一表面23a與第二表面23b,且以其第一表面23a藉由藉由如銲錫材之導電體230結合至該承載結構20之第一側20a之線路層200上。例如,該線路板23係為環狀框架形式,如圖2A-1所示,以圍繞該複數第一電子元件21。
另外,該線路板23之第二表面23b上可形成複數如銲錫凸塊之導電元件25。
如圖2B所示,形成一封裝層27於該承載結構20之第一側20a上,以包覆該些第一電子元件21、該線路板23及該些導電元件25。
於本實施例中,形成於該封裝層27之材質係例如為聚醯亞胺(polyimide,簡稱PI)、乾膜(dry film)、環氧樹脂(epoxy)或封裝材(molding compound)等絕緣材,但並不限於上述。例如,可採用壓合(lamination)或模壓(molding)等方式將該封裝層27形成於該承載結構20之第一側20a上。
再者,該封裝層27係填入該第一電子元件21與該承載結構20之第一側20a之間以包覆該些導電凸塊211,且填入該線路板23與該承載結構20之第一側20a之間以包覆該些導電體230;或者,可先填充底膠(圖略)於該第一電子元件21與該承載結構20之第一側20a之間以包覆該些導電凸塊211,且該底膠亦填入該線路板23與該承載結構20之第一側20a之間以包覆該些導電體230,再使該封裝層27包覆該底膠。
如圖2C所示,配置至少一第二電子元件22與至少一第一導電結構26於該承載結構20之第二側20b上(本實施例係以複數第二電子元件22與複數第一導電結構26進行說明)。
於本實施例中,該第二電子元件22係為主動元件、被動元件或其二者組合等,其中,該主動元件係例如半導體晶片,且該被動元件係例如電阻、電容及電感。例如,當該第二電子元件22係為半導體晶片時,其可藉由複數如銲錫材料之導電凸塊221採用覆晶方式設於該承載結構20之第二側20b之線路層200上並電性連接該線路層200;或者,該第二電子元件22可藉由複數銲線(圖略)以打線方式電性連接該線路層200。亦或,該第二電子元件22可直接接觸該線路層200。然而,有關該第二電子元件22電性連接該承載結構20之方式不限於上述。
再者,該第一導電結構26係為球體、柱體或其它立體之凸塊狀,其電性連接該承載結構20之第二側20b上之線路層200。例如,於本實施例中係以銲錫球作為該第一導電結構26;或者,於另一實施例中,如圖3A所示之電子封裝件3a,可採用如銅柱之金屬柱作為第一導電結構36。
如圖2D所示,形成一包覆層24於該承載結構20之第二側20b上,以包覆該些第二電子元件22與該些第一導電結構26。
於本實施例中,該包覆層24係為絕緣材,如聚醯亞胺(polyimide,簡稱PI)、乾膜(dry film)、如環氧樹脂(epoxy)之封裝膠體或封裝材(molding compound)。例如,該包覆層24之製程可選擇液態封膠(liquid compound)、噴塗(injection)、壓合(lamination)或模壓(compression molding)等方式形成於該承載結構20上。
再者,該包覆層24係定義有一包覆該些第二電子元件22之第一包覆部241及一包覆該些第一導電結構26之第二包覆部242,其中,該第一包覆部241之高度H1係高於該第二包覆部242之高度H2。例如,使用研磨方式
移除該包覆層24於該些第一導電結構26處之部分材質(如圖2D所示之虛線區域),以形成該第二包覆部242,使該包覆層24之外觀具有缺口或呈凹凸狀,其中,有關移除該包覆層24之部分材質之方式繁多,如蝕刻、雷射、銑具等,並不限於上述。或者,亦可採用模壓方式,以模具直接形成外觀具有缺口或呈凹凸狀之包覆層24,而無需移除該包覆層24之部分材質。因此,有關該包覆層24之製作方式繁多,並無特別限制。
又,該包覆層24可覆蓋該承載結構20之第二側20b之全部表面;於其它實施例中,該包覆層24之範圍可依需求調整,如圖3B所示之電子封裝件3b,該包覆層24僅形成於該承載結構20之第二側20b之局部表面上,以將至少一電子連接器30接置於該承載結構20之第二側20b之外露區域上,供接合電子產品之主機板之連接埠上。例如,該電子連接器30可透過銲接(如圖所示之銲錫凸塊300)或其它方式設於該承載結構20之第二側20b之線路層200上。
另外,可依電子產品之空間需求,調整該包覆層24之外觀。例如,當該些第二電子元件22相對於該承載結構20第二側20b之高度不一致時,可依據該些第二電子元件22相對於該承載結構20第二側20b之高度形成凹凸狀之第一包覆部341,如圖3C所示之電子封裝件3c之階梯狀包覆層34。有關該包覆層24之外觀樣式可依需求變化,並無特別限制。
如圖2E所示,於該包覆層24之第二包覆部242上形成複數開孔240及至少一凹槽280,以令該些第一導電結構26外露於該些開孔240,使該些第一導電結構26作為接點(I/O),且該凹槽280係外露出該承載結構20之第二
側20b之表面。之後,移除該封裝層27之部分材質,使該導電元件25外露於該封裝層27。
於本實施例中,該第一導電結構26之接點功能可為訊號接點(signal pin)、組裝(SMT)用接點或其他用途等。因此,於另一實施例中,可於該承載結構20之第二側20b上配置一線路結構46,如圖4所示之電子封裝件4,使該線路結構46之其中一側藉由複數導電凸塊460電性連接該承載結構20之第二側20b上之線路層200,而另一側佈設第一導電結構461,供外接其它封裝模組。例如,該線路結構46係具有重佈線路層(redistribution layer,簡稱RDL)之線路塊,如基板形式或該線路板23之環狀框架形式,以作為中介板(interposer)。
再者,該開孔240及凹槽280係以雷射燒灼方式形成,使該第一導電結構26之端部與該開孔240之間係具有間隔,且該第一導電結構26之端部可高於、低於或齊平該包覆層24之第二包覆部242之表面24a。於其它實施例中,如圖3A所示,可藉由進行整平製程,如研磨方式,以移除該第一導電結構36及該第二包覆部242之部分材質,使該第一導電結構36之端面36a與該包覆層24之第二包覆部242之表面24a共平面(即兩者齊平),以令該第一導電結構36外露於該第二包覆部242。因此,有關該第一導電結構外露於該第二包覆部之方式繁多,並無特別限制。
又,該凹槽280係形成於該第一包覆部241與第二包覆部242之間,且可沿該第二包覆部242之邊緣配置,如圖2E-1所示,並外露出該承載結構20之第二側20b之線路層200。
另外,可採用研磨、蝕刻、燒灼、切除或其它適合方式移除該封裝層27之部分材質,使該導電元件25外露於該封裝層27。
如圖2F所示,形成第二導電結構28於該凹槽280中,以令該第二導電結構28電性連接該承載結構20之第二側20b之線路層200,進而製得本發明之電子封裝件2。
於本實施例中,該第二導電結構28係為導電膠,如銀膠、銅膏或其它適當膠材。
再者,該第二導電結構28可作為接地。例如,將屏蔽結構29形成於該包覆層24上並接觸該第二導電結構28,以令該屏蔽結構29遮蓋該第二電子元件22,使該第二電子元件22不會受外界之電磁干擾。進一步,該屏蔽結構29之佈設區域可依需求選擇延伸至該承載結構20之側面20c,以接觸該承載結構20之側面20c之線路層,使該屏蔽結構29接地而達到屏蔽的效果。甚至於該屏蔽結構29可延伸至該封裝層27,以保護該第一電子元件21不會受外界之電磁干擾。
再者,可藉由塗佈金屬層(如銅材)之加工方式形成該屏蔽結構29於該包覆層24上,例如,濺鍍(sputtering)、蒸鍍(vaporing)、電鍍、無電電鍍或化鍍等方式;或者,利用蓋設金屬架或金屬罩、或貼膜(foiling)等設置方式形成該屏蔽結構29於該包覆層24上。應可理解地,有關屏蔽方式繁多,並無特別限制。
因此,藉由該第二導電結構28電性連接該屏蔽結構29,使該屏蔽結構29可透過該第二導電結構28連接該承載結構20的線路層200之接地線路而達到屏蔽的效果。
另外,於後續製程中,該電子封裝件2可藉由該些導電元件25接置於一如電路板之電子裝置(圖未示)上。
因此,本發明之製法主要藉由該承載結構20之第二側20b上配置外露於該包覆層24之第一導電結構26,36,461,以依功能需求(如天線)而外接所需元件,使該承載結構20之佈設面積依據包覆層24之模具設計即可,而無需增加該承載結構20之佈設面積,故相較於習知技術,本發明之製法能減少該電子封裝件2,3a,3b,3c,4之體積,使該電子封裝件2,3a,3b,3c,4符合輕薄短小之需求。
再者,藉由該承載結構20之第二側20b上配置外露於該包覆層24之第二導電結構28,使該屏蔽結構29無需覆蓋該第一導電結構26,36,461,因而減少該屏蔽結構29之佈設面積,以節省該屏蔽結構29之材料,故本發明之製法能減少該電子封裝件2,3a,3b,3c,4之製作成本。
又,藉由該第二導電結構28之設計,以遮擋該第二電子元件22周圍,使該第二電子元件22與該第一導電結構26,36,461之間不會相互電磁干擾,進而使終端產品之可靠性更佳。
本發明復提供一種電子封裝件2,3a,3b,3c,4,係包括:一具有線路層200之承載結構20、第一電子元件21、線路板23、第二電子元件22、第一導電結構26,36,461、一包覆層24,34、以及第二導電結構28。
所述之承載結構20係具有相對之第一側20a與第二側20b。
所述之第一電子元件21係設於該承載結構20之第一側20a上並電性連接該線路層200。
所述之線路板23係設於該承載結構20之第一側20a上並電性連接該線路層200。
所述之第二電子元件22係設於該承載結構20之第二側20b上並電性連接該線路層200。
所述之第一導電結構26,36,461係設於該承載結構20之第二側20b上且電性連接該線路層200。
所述之包覆層24,34係設於該承載結構20之第二側20b上以包覆該第二電子元件22及第一導電結構26,36,461,該包覆層24,34係定義有一體成形之第一包覆部241,341及第二包覆部242,以令該第二電子元件22位於該第一包覆部241,341中,且該第一導電結構26,36,461位於該第二包覆部242中,其中,該第一包覆部241,341之高度H1係高於該第二包覆部242之高度H2,且該第一導電結構26,36,461係外露於該第二包覆部242。
所述之第二導電結構28係設於該承載結構20之第二側20b上且電性連接該線路層200,其中,該第二導電結構28之組成係不同於該第一導電結構26,36,461之組成。
於一實施例中,該線路板23係為環形框架形式。
於一實施例中,該第一導電結構26,36,461係為銲錫球或金屬柱。
於一實施例中,該第二導電結構28係為導電膠。
於一實施例中,該包覆層24,34外露出該承載結構20之第二側20b之局部表面,以接置電子連接器30。
於一實施例中,該第一包覆部341之外觀呈凹凸狀。
於一實施例中,所述之電子封裝件4復包括一承載該第一導電結構461之線路結構46,其設於該承載結構20之第二側20b上。
於一實施例中,所述之電子封裝件4復包括一包覆該第一電子元件21與線路板23之封裝層27。例如,該線路板23上配置複數導電元件25,以令該複數導電元件25外露於該封裝層27。
於一實施例中,所述之電子封裝件2,3a,3b,3c,4復包括形成於該包覆層24,34上之屏蔽結構29,其電性連接該第二導電結構28。
綜上所述,本發明之電子封裝件及其製法,係藉由該承載結構之第二側上配置外露於該包覆層之第一導電結構,以依功能需求而外接所需元件,使該承載結構之佈設面積依據包覆層之模具設計即可,而無需增加該承載結構之佈設面積,故本發明能減少該電子封裝件之體積,使該電子封裝件符合輕薄短小之需求。
再者,藉由該第二導電結構之設計,以遮擋該第二電子元件周圍,使該第二電子元件與該第一導電結構之間不會相互電磁干擾,進而使終端產品之可靠性更佳。
上述實施例係用以例示性說明本發明之原理及其功效,而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對上述實施例進行修改。因此本發明之權利保護範圍,應如後述之申請專利範圍所列。
2:電子封裝件
20:承載結構
20a:第一側
20b:第二側
20c:側面
21:第一電子元件
22:第二電子元件
23:線路板
230:導電體
24:包覆層
241:第一包覆部
242:第二包覆部
25:導電元件
26:第一導電結構
27:封裝層
28:第二導電結構
280:凹槽
29:屏蔽結構
Claims (20)
- 一種電子封裝件,係包括:具有線路層之承載結構,係定義有相對之第一側與第二側;第二電子元件,係設於該承載結構之第二側上並電性連接該線路層;第一導電結構,係設於該承載結構之第二側上且電性連接該線路層;包覆層,係設於該承載結構之第二側上以包覆該第二電子元件及第一導電結構,該包覆層係定義有一體成形之第一包覆部及第二包覆部,以令該第二電子元件位於該第一包覆部中,且該第一導電結構位於該第二包覆部中,其中,該第一包覆部之高度係高於該第二包覆部之高度,且該第一導電結構係外露於該第二包覆部;以及第二導電結構,係設於該承載結構之第二側上且電性連接該線路層,其中,該第二導電結構之組成係不同於該第一導電結構之組成。
- 如請求項1所述之電子封裝件,其中,該第一導電結構係為銲錫球或金屬柱。
- 如請求項1所述之電子封裝件,其中,該第二導電結構係為導電膠。
- 如請求項1所述之電子封裝件,其中,該包覆層外露出該承載結構之第二側之局部表面,以接置電子連接器。
- 如請求項1所述之電子封裝件,其中,該第一包覆部之外觀呈凹凸狀。
- 如請求項1所述之電子封裝件,復包括一承載該第一導電結構之線路結構,其設於該承載結構之第二側上。
- 如請求項1所述之電子封裝件,復包括:第一電子元件,係設於該承載結構之第一側上並電性連接該線路層;以及線路板,係設於該承載結構之第一側上並電性連接該線路層。
- 如請求項7所述之電子封裝件,其中,該線路板係為環形框架形式。
- 如請求項7所述之電子封裝件,其中,該線路板上配置複數導電元件,以接置電子裝置。
- 如請求項1所述之電子封裝件,復包括形成於該包覆層上之屏蔽結構,其電性連接該第二導電結構。
- 一種電子封裝件之製法,係包括:提供一具有線路層之承載結構,其定義有相對之第一側與第二側;將第二電子元件與第一導電結構設於該承載結構之第二側上,並使該第二電子元件與第一導電結構電性連接該線路層;形成包覆層於該承載結構之第二側上以包覆該第二電子元件及第一導電結構,該包覆層係定義有一體成形之第一包覆部及第二包覆部,且該第一包覆部之高度係高於該第二包覆部之高度,其中,該第二電子元件位於該第一包覆部中,且該第一導電結構位於該第二包覆部中並外露於該第二包覆部;以及形成第二導電結構於該承載結構之第二側上,以令該第二導電結構電性連接該線路層,其中,該第二導電結構之組成係不同於該第一導電結構之組成。
- 如請求項11所述之電子封裝件之製法,其中,該第一導電結構係為銲錫球或金屬柱。
- 如請求項11所述之電子封裝件之製法,其中,該第二導電結構係為導電膠。
- 如請求項11所述之電子封裝件之製法,其中,該包覆層外露出該承載結構之第二側之局部表面,以接置電子連接器。
- 如請求項11所述之電子封裝件之製法,其中,該第一包覆部之外觀呈凹凸狀。
- 如請求項11所述之電子封裝件之製法,復包括將一承載該第一導電結構之線路結構設於該承載結構之第二側上。
- 如請求項11所述之電子封裝件之製法,復包括將第一電子元件與線路板設於該承載結構之第一側上,並使該第一電子元件與線路板電性連接該線路層。
- 如請求項17所述之電子封裝件之製法,其中,該線路板係為環形框架形式。
- 如請求項17所述之電子封裝件之製法,其中,該線路板上配置複數導電元件,以接置電子裝置。
- 如請求項11所述之電子封裝件之製法,復包括形成屏蔽結構於該包覆層上,且令該屏蔽結構電性連接該第二導電結構。
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