TWI819582B - 電子封裝件及其基板結構 - Google Patents

電子封裝件及其基板結構 Download PDF

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TWI819582B
TWI819582B TW111115837A TW111115837A TWI819582B TW I819582 B TWI819582 B TW I819582B TW 111115837 A TW111115837 A TW 111115837A TW 111115837 A TW111115837 A TW 111115837A TW I819582 B TWI819582 B TW I819582B
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substrate structure
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謝雯貞
紀雅婷
曹佳雯
張馨尹
蔡苡琳
簡秀芳
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矽品精密工業股份有限公司
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Priority to CN202210498403.8A priority patent/CN116995036A/zh
Priority to US17/859,291 priority patent/US20230343692A1/en
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Abstract

一種電子封裝件，其包括基板結構、設於該基板結構上之電子元件以及包覆該電子元件之封裝層，其中，於該基板結構之基板本體之表面上形成至少一功能線路，其於封裝區與外圍區之間的交界處的界線上配置寬度較小之導線，以於形成該封裝層用之模具遮蓋於該基板結構上時，該模具於該導線周圍處會產生縫隙，供作為排氣通道，故當形成該封裝層時，可藉由該排氣通道進行排氣，以避免該封裝層發生氣泡或溢膠等問題。

Description

電子封裝件及其基板結構
本發明係有關一種半導體裝置，尤指一種可提升良率之電子封裝件及其基板結構。
隨著電子產業的發達，現今的電子產品已趨向輕薄短小與功能多樣化的方向設計，半導體封裝技術亦隨之開發出不同的封裝型態。為滿足半導體裝置之高積集度(Integration)以及微型化(Miniaturization)需求，除傳統打線式(Wire bonding)之半導體封裝技術外，業界主要藉由覆晶(Flip chip)方式，以提升半導體裝置之佈線密度。
圖1A係為習知覆晶式半導體封裝件1之剖視示意圖。如圖1A所示，先將一半導體晶片11藉由複數銲錫凸塊110結合至一封裝基板10之電性接觸墊100上，再回銲該銲錫凸塊110。接著，藉由模具9將封裝膠體12形成於該封裝基板10上，以包覆該半導體晶片11與該些銲錫凸塊110。
如圖1A及圖1B所示，該封裝基板10通常定義有一用以形成該封裝膠體12之封裝區A及一環繞該封裝區A之外圍區B，且於該封 裝基板10上通常會配置至少一電性連接該半導體晶片11之片形接地線路14，且令該片形接地線路14自該封裝區A延伸至外圍區B。
惟，習知半導體封裝件1中，該片形接地線路14係為大面積金屬結構，使其於該封裝區A與該外圍區B之間的交界處的界線L上係大面積佔據該界線L之區段，故當該模具9遮蓋於該封裝基板10上時，該模具9與該片形接地線路14之間並無縫隙，以致於當形成該封裝膠體12時，容易於該片形接地線路14處及其周圍因排氣不良而造成該封裝膠體12發生氣泡(void)或溢膠，導致該半導體封裝件1發生氣爆(popcorn)或分層(delamination)問題，致使生產良率不佳。
因此，如何克服上述習知技術的問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失，本發明係提供一種基板結構，係包括：基板本體，其表面定義有相互鄰接之封裝區與外圍區；以及至少一功能線路，係形成於該基板本體上且自該封裝區延伸至該外圍區，其中，該功能線路係定義有一位於該封裝區上之第一區塊、一位於該外圍區上之第二區塊、及至少一連接該第一區塊與第二區塊之導線，且該導線之寬度係小於該第一區塊之寬度。
本發明亦提供一種電子封裝件，係包括：前述之基板結構；電子元件，係設於該封裝區上並電性連接該功能線路；以及封裝層，係設於該封裝區上而未設於該外圍區上。
前述之電子封裝件及其基板結構中，該導線之寬度係為100至150微米。例如，該導線之寬度係為130微米。
前述之電子封裝件及其基板結構中，該導線之寬度係小於或等於該第二區塊之寬度。
前述之電子封裝件及其基板結構中，該導線係橫跨該封裝區與該外圍區之間的交界處的界線，以令該導線基於該界線定義出一配置於該封裝區之第一線段與一配置於該外圍區之第二線段。例如，該第一線段係連接該第一區塊，而該第二線段係連接該第二區塊。或者，該第一線段之長度係為130至160微米，且該第二線段之長度亦可為130至160微米。
前述之電子封裝件及其基板結構中，該功能線路係為接地線路。
前述之電子封裝件及其基板結構中，該基板本體於該外圍區上係配置有金屬層，其與該導線保持間距而未電性連接該導線。
由上可知，本發明之電子封裝件及其基板結構中，主要藉由該功能線路之設計，將該功能線路於該封裝區與該外圍區之間的交界處的界線上配置寬度較小之導線，以於形成該封裝層用之模具遮蓋於該基板結構上時，該模具於該導線周圍處會產生縫隙，供作為排氣通道，故相較於習知技術，當形成該封裝層時，可藉由該排氣通道進行排氣，以增加排氣量，避免該封裝層發生氣泡或溢膠，進而避免該電子封裝件發生氣爆或分層等問題。
1:半導體封裝件
10:封裝基板
100:電性接觸墊
11:半導體晶片
110:銲錫凸塊
12:封裝膠體
14:片形接地線路
2:電子封裝件
2a,4a:基板結構
20:基板本體
200:線路層
200a:導電跡線
201:介電層
21:電子元件
210:導電凸塊
22:封裝層
24:功能線路
240,340:導線
240a:第一線段
240b:第二線段
241:第一區塊
242,342:第二區塊
35:金屬層
9:模具
H:開孔
A:封裝區
B:外圍區
C,C1,C2,C3,C4:功能區
F:排氣通道
L:界線
d1,d2:長度
t,t1,t2:寬度
圖1A係為習知半導體封裝件於製程中之剖視示意圖。
圖1B係為習知半導體封裝件之上視示意圖。
圖2A係為本發明之電子封裝件於製程中之剖視示意圖。
圖2B係為本發明之電子封裝件之上視示意圖。
圖2C係為圖2B之局部放大示意圖。
圖3A係為圖2B之另一實施例之局部上視示意圖。
圖3B及圖3C係為圖3A之其它實施例之局部上視示意圖。
圖4係為本發明之基板結構之另一實施例之上視示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「上」、「第一」、「第二」、及「一」等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
圖2A及圖2B係為本發明之電子封裝件2的示意圖。如圖2A所示，所述之電子封裝件2係包括一基板結構2a、至少一電子元件21 以及一包覆該電子元件21之封裝層22，其中，該基板結構2a係包括一基板本體20。
所述之基板本體20係於其外表面上定義有相互鄰接之一封裝區A與一環繞該封裝區A之外圍區B。
於本實施例中，該基板本體20係如具有核心層與線路層之封裝基板(substrate)或無核心層(coreless)之線路結構，其包含至少一介電層201及結合該介電層201之線路層200。例如，以線路重佈層(redistribution layer，簡稱RDL)之製作方式形成該線路層200，其中，形成該線路層200之材質係為銅，且形成該介電層201之材質係為如聚對二唑苯(Polybenzoxazole，簡稱PBO)、聚醯亞胺(Polyimide，簡稱PI)、預浸材(Prepreg，簡稱PP)等之介電材。
再者，該封裝區A之輪廓與該外圍區B之輪廓係大致呈矩形，且該封裝區A之角落處可依需求設計成倒角。
所述之線路層200於該基板本體20之最外表面上係具有複數佈設於該封裝區A內之導電跡線200a，另外於該基板本體20之最外表面上形成有至少一自該封裝區A延伸至該外圍區B之功能線路24，其中，該功能線路24係定義有一位於該封裝區A上之第一區塊241、一位於該外圍區B上之第二區塊242、及至少一連接該第一區塊241與第二區塊242之導線240，且該導線240之寬度t係小於該第一區塊241之寬度t1。
於本實施例中，該功能線路24係為接地線路或電源線路，且該導線240之寬度t係為100至150微米(um)(最佳為130um)。例如，該基板本體20係於其外表面上定義有一橫跨該封裝區A與該外圍區B之功能區C，以佈設該功能線路24，供接地或電源之用。
再者，該導線240係橫跨該封裝區A與該外圍區B之間的交界處的界線L(即模壓線)，以令該導線240基於該界線L定義出一配置於該封裝區A之第一線段240a與一配置於該外圍區B之第二線段240b，如圖2C所示。例如，該第一線段240a係連接該第一區塊241且其長度d1(即該第一區塊241與該界線L之間的距離)係為130至160微米(um)(最佳為140um)，而該第二線段240b係連接該第二區塊242且其長度d2(即該第二區塊242與該界線L之間的距離)係為130至160微米(um)(最佳為140um)。應可理解地，該第一線段240a之長度d1可同於或異於該第二線段240b之長度d2，長度d1與長度d2用於避免因基板與模具位移而造成無法排氣。
又，該第一區塊241與第二區塊242之形狀可相同(如圖2B所示之矩形片體狀或如圖3A所示之網格狀)或相異(如圖3B所示之網格狀第一區塊241與線條狀第二區塊342)，且該第一區塊241與第二區塊242之間係透過導線240,340相連接。例如，該網格狀係於片體上形成複數開孔H，且較佳者，該些開孔H係陣列排設。
另外，該導線340之數量可依需求而定，如圖3A及圖3B所示之多條導線340，並無特別限制，且該導線240之寬度t可小於第二區塊242(片體狀)之寬度t2(如圖2B所示)，或者各該導線340之寬度t等於該第二區塊342(線條狀)之寬度t2(如圖3B所示)。應可理解地，當該功能區C配置多條導線340時，各該導線340之寬度可相同或相異，且各該導線340之間的距離可依需求設定，並無特別限制。
所述之電子元件21係為主動元件、被動元件或其二者組合，且該主動元件係例如半導體晶片，而該被動元件係例如電阻、電容及電感。
於本實施例中，該電子元件21係例如為圖形處理器(graphics processing unit，簡稱GPU)、高頻寬記憶體(High Bandwidth Memory，簡稱HBM)或其它類型半導體晶片之主動元件，其係藉由複數如銲錫凸塊、銅凸塊或其它等之導電凸塊210以覆晶方式電性連接該導電跡線200a與該功能線路24。
再者，可藉由該封裝層22同時包覆該電子元件21與該些導電凸塊210。或者，亦可先形成底膠(圖略)於該電子元件21與該基板結構2a之間以包覆該些導電凸塊210，再形成該封裝層22以包覆該底膠與該電子元件21。
應可理解地，有關電子元件21電性連接該導電跡線200a與該功能線路24之方式繁多，如打線方式、直接接觸方式或其它等，並不限於上述。
所述之封裝層22係設於該封裝區A之全區上而未設於該外圍區B上，如圖2B所示，且該封裝層22係為絕緣材，如聚醯亞胺(polyimide，簡稱PI)、乾膜(dry film)、如環氧樹脂(epoxy)之封裝膠體或封裝材(molding compound)，其可用壓合(lamination)或模壓(molding)之方式形成於該基板結構2a上。
於本實施例中，封裝製程係先設置至少一電子元件21於該基板結構2a(基板本體20)之封裝區A上，以令該電子元件21電性連接該導電跡線200a與該功能線路24，再藉由模具9設於該基板結構2a上，以將該封裝層22形成於該封裝區A上而包覆該電子元件21。之後，移除該模具9，以獲取該電子封裝件2。
因此，本發明之電子封裝件2藉由該基板結構2a之設計，將該功能線路24於該封裝區A與該外圍區B之間的交界處的界線L上配置 寬度t較小之導線240,340，以於該模具9遮蓋於該基板結構2a上時，該模具9與該功能區C之間(即該導線240,340周圍處)會產生縫隙，供作為排氣通道F，如圖2A所示，故相較於習知技術，當形成該封裝層22時，於該導線240,340處及其周圍能藉由該排氣通道F進行排氣，以增加排氣量，減少該封裝層22發生氣泡(void)或溢膠，進而避免該電子封裝件2發生氣爆(popcorn)或分層(delamination)等問題。
再者，該基板本體20於該外圍區B上可依需求配置金屬層35，如圖3C所示，其未電性連接該電子元件21，以平衡應力分佈而防止該基板本體20翹曲，供作為強化結構之用。例如，該金屬層35可為線條狀，其對應位於該功能區C上並與該導線340(第二線段)保持間距而未電性連接該導線340(第二線段)。
另外，如圖4所示，本發明之基板結構4a係可在基板本體20上依需求設計多個功能區C1,C2,C3,C4(或功能線路)，如該界線L之邊線及角落處，以形成更多排氣通道F，使製程良率更好。應可理解地，亦可額外配置習知片形接地線路，並不會影響排氣功能。
綜上所述，本發明之電子封裝件及其基板結構，係藉由將該功能區內之功能線路對應模具邊界之位置設計成線寬較小之導線，以形成該封裝層時，於該導線處及其周圍能形成排氣通道而增加排氣量，故該封裝層不會發生氣泡或溢膠，避免該電子封裝件發生氣爆或分層等問題，進而能提高生產良率。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2:電子封裝件
2a:基板結構
20:基板本體
200:線路層
200a:導電跡線
201:介電層
21:電子元件
210:導電凸塊
22:封裝層
24:功能線路
9:模具
F:排氣通道
L:界線

Claims (20)

  1. 一種基板結構，係包括：基板本體，其表面定義有相互鄰接之封裝區與外圍區；以及至少一功能線路，係形成於該基板本體上且自該封裝區延伸至該外圍區，其中，該功能線路係定義有一位於該封裝區上之第一區塊、一位於該外圍區上之第二區塊、及至少一連接該第一區塊與第二區塊之導線，且該導線之寬度係小於該第一區塊之寬度，其中，該導線供一模具遮蓋於該基板本體上時，於該導線周圍形成排氣通道。
  2. 如請求項1所述之基板結構，其中，該導線之寬度係為100至150微米。
  3. 如請求項2所述之基板結構，其中，該導線之寬度係為130微米。
  4. 如請求項1所述之基板結構，其中，該導線之寬度係小於或等於該第二區塊之寬度。
  5. 如請求項1所述之基板結構，其中，該導線係橫跨該封裝區與該外圍區之間的交界處的界線，以令該導線基於該界線定義出一配置於該封裝區之第一線段與一配置於該外圍區之第二線段。
  6. 如請求項5所述之基板結構，其中，該第一線段係連接該第一區塊，而該第二線段係連接該第二區塊。
  7. 如請求項5所述之基板結構，其中，該第一線段之長度係為130至160微米。
  8. 如請求項5所述之基板結構，其中，該第二線段之長度係為130至160微米。
  9. 如請求項1所述之基板結構，其中，該功能線路係為接地線路。
  10. 如請求項1所述之基板結構，其中，該基板本體於該外圍區上係配置有金屬層，其與該導線保持間距而未電性連接該導線。
  11. 一種電子封裝件，係包括：如請求項1所述之基板結構；電子元件，係設於該封裝區上並電性連接該功能線路；以及封裝層，係設於該封裝區上而未設於該外圍區上。
  12. 如請求項11所述之電子封裝件，其中，該導線之寬度係為100至150微米。
  13. 如請求項12所述之電子封裝件，其中，該導線之寬度係為130微米。
  14. 如請求項11所述之電子封裝件，其中，該導線之寬度係小於或等於該第二區塊之寬度。
  15. 如請求項11所述之電子封裝件，其中，該導線係橫跨該封裝區與該外圍區之間的交界處的界線，以令該導線基於該界線定義出一配置於該封裝區之第一線段與一配置於該外圍區之第二線段。
  16. 如請求項15所述之電子封裝件，其中，該第一線段係連接該第一區塊，而該第二線段係連接該第二區塊。
  17. 如請求項15所述之電子封裝件，其中，該第一線段之長度係為140至160微米。
  18. 如請求項15所述之電子封裝件，其中，該第二線段之長度係為140至160微米。
  19. 如請求項11所述之電子封裝件，其中，該功能線路係為接地線路。
  20. 如請求項11所述之電子封裝件，其中，該基板本體於該外圍區上係配置有金屬層，其與該導線保持間距而未電性連接該導線。
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