TWI594390B - 半導體封裝件及其製法 - Google Patents

半導體封裝件及其製法 Download PDF

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TWI594390B
TWI594390B TW103117272A TW103117272A TWI594390B TW I594390 B TWI594390 B TW I594390B TW 103117272 A TW103117272 A TW 103117272A TW 103117272 A TW103117272 A TW 103117272A TW I594390 B TWI594390 B TW I594390B
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semiconductor package
semiconductor
encapsulant
substrate
shield
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TW103117272A
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TW201545304A (zh
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張卓興
許聰賢
鍾興隆
朱德芳
陳嘉揚
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矽品精密工業股份有限公司
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Priority to TW103117272A priority Critical patent/TWI594390B/zh
Priority to CN201410230567.8A priority patent/CN105097784A/zh
Priority to US14/459,678 priority patent/US9490219B2/en
Publication of TW201545304A publication Critical patent/TW201545304A/zh
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Description

半導體封裝件及其製法
本發明係有關一種半導體封裝件，尤指一種具防內部電子元件相互電磁波干擾之半導體封裝件及其製法。
隨著半導體技術的演進，半導體產品已開發出不同封裝產品型態，而為提升電性品質，多種半導體產品具有屏蔽之功能，以防止電磁干擾(Electromagnetic Interference，EMI)產生。
習知避免EMI之射頻(Radio frequency,RF)模組，如第1A至1C圖所示，該射頻模組1係將複數射頻晶片11a,11b與非射頻式電子元件11電性連接在一基板10上，再以係如環氧樹脂之封裝膠體13包覆各該射頻晶片11a,11b與該非射頻式電子元件11，並於該封裝膠體13上形成一金屬薄膜14。該射頻模組1藉由該封裝膠體13保護該射頻晶片11a,11b、非射頻式電子元件11及基板10，並避免外界水氣或污染物之侵害，且藉由該金屬薄膜14保護該些射頻晶片11a,11b免受外界EMI影響。
惟，習知射頻模組1之外圍雖可藉由包覆該金屬薄膜 14以達到避免EMI之目的，但卻無法避免其內部各該射頻晶片11a,11b之間的電磁波干擾(EMI)，導致訊號容易發生錯誤。
因此，如何提供一種能避免射頻模組內部之電子元件相互電磁波干擾之半導體封裝件，實為一重要課題。
為克服習知技術之種種缺失，本發明係提供一種一種半導體封裝件，係包括：基板；複數半導體元件，係設於該基板上；至少一屏蔽件，係立設於該基板上並位於各該半導體元件之間；以及封裝膠體，係設於該基板上，以包覆各該半導體元件與該屏蔽件。
本發明復提供一種半導體封裝件之製法，係包括：設置複數半導體元件與至少一屏蔽件於一基板上，且該屏蔽件位於各該半導體元件之間；以及形成封裝膠體於該基板上，以包覆各該半導體元件與該屏蔽件。
前述之半導體封裝件及其製法中，該些半導體元件之至少一者係為射頻晶片。例如，該射頻晶片係為藍芽晶片或Wi-Fi晶片。
前述之半導體封裝件及其製法中，該屏蔽件係外露於該封裝膠體。例如，該屏蔽件之外露表面係齊平該封裝膠體之表面。
前述之半導體封裝件及其製法中，該屏蔽件係為板體。
前述之半導體封裝件及其製法中，復包括金屬層，係 形成於該封裝膠體上。例如，該金屬層電性連接該屏蔽件，且該金屬層係由銅、鎳、鐵、鋁及不銹鋼所組成之群組之材質所製成。又該基板具有用以電性連接該金屬層之線路。
由上可知，本發明之半導體封裝件及其製法，係藉由該屏蔽件位於各該半導體元件之間，以避免各該半導體元件之間發生電磁波相互干擾之問題。
1‧‧‧射頻模組
10,20‧‧‧基板
11‧‧‧非射頻式電子元件
11a,11b‧‧‧射頻晶片
13,23‧‧‧封裝膠體
14‧‧‧金屬薄膜
2,2’‧‧‧半導體封裝件
20a‧‧‧上表面
20b‧‧‧下表面
20c‧‧‧側表面
200‧‧‧電性接觸墊
201‧‧‧接地部
202‧‧‧內部線路
21‧‧‧半導體元件
21’‧‧‧電子元件
210‧‧‧銲線
210’‧‧‧銲球
22‧‧‧屏蔽件
22a‧‧‧外露表面
23a‧‧‧頂面
23b‧‧‧底面
23c‧‧‧側面
24‧‧‧金屬層
第1A至1C圖係為習知射頻模組之製法之剖面示意圖；以及第2A至2C圖係為本發明半導體封裝件之製法之剖面示意圖；其中，第2A’圖係為第2A圖之立體圖，第2C’圖係為第2C圖之另一實施例。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“一”及“下”等之用語，亦僅為便於敘述之明瞭，而 非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
請參閱第2A至2C圖，係為本發明半導體封裝件之製法之示意圖。於本實施例中，所述之半導體封裝件2係可發出電磁波者，例如為射頻(Radio frequency,RF)模組。
如第2A及2A’圖所示，提供一具有上表面20a及下表面20b之基板20；接著，接置複數半導體元件21與至少一屏蔽件22於該基板20之上表面20a上，且該屏蔽件22位於各該半導體元件21之間。
所述之基板20之上表面20a上具有線路層，該線路層包含複數電性接觸墊200與至少一接地部201。於本實施例中，該基板20之種類繁多，例如，該基板20之線路層具有至少一內部線路202(如第2C’圖所示)，且該內部線路202可選擇性地電性連接該電性接觸墊200與該接地部201，因而該基板20之構造並無特別限制。
所述之半導體元件21係為射頻晶片，例如：藍芽晶片或Wi-Fi(Wireless Fidelity)晶片。於本實施例中，該些半導體元件21之其中一者為藍芽晶片，而另一者為Wi-Fi晶片，且亦可於該基板20之上表面20a上設置其它無影響電磁波干擾之電子元件21’。
再者，該半導體元件21係為打線式晶片，即藉由複數銲線210對應電性連接該基板20上表面20a上之電性接觸墊200；或者，該半導體元件21為覆晶式晶片，即藉由複 數銲球210’對應電性連接至該基板20上表面20a上之電性接觸墊200。
所述之屏蔽件22係為導電材板體，其立設於該接地部201上並電性連接該接地部201，以將該基板20之上表面20a隔成複數置放室。
於本實施例中，該屏蔽件22之形狀並無限制，如不規則狀或幾何形狀，而該些半導體元件21係分別置放於各該置放室內，且藉由該屏蔽件22作為電磁波屏障(EMI Shielding)，以防止各該半導體元件21之間相互電磁波干擾，例如，防止藍芽晶片與Wi-Fi晶片之間的訊號相互干擾。
如第2B圖所示，形成封裝膠體23覆蓋於該基板20之上表面20a上，以包覆各該半導體元件21、電子元件21’與該屏蔽件22。
於本實施例中，該封裝膠體23具有頂面23a及相對該頂面23a且結合至該基板20之上表面20a的底面23b，且該屏蔽件22係外露於該封裝膠體23之頂面23a。具體地，該屏蔽件22之外露表面22a係齊平該封裝膠體23之頂面23a。
再者，各該半導體元件21與電子元件21’並未外露於該封裝膠體23之頂面23a。
如第2C圖所示，以例如化學鍍膜的方式，如濺鍍(sputtering)，形成金屬層24於該基板20之側表面20c、該屏蔽件22之外露表面22a、該封裝膠體23之頂面23a 與側面23c上，俾形成該半導體封裝件2。
於本實施例中，該金屬層24係電性連接該屏蔽件22，且亦藉由該金屬層24作為電磁波屏障，以防止各該半導體元件21之間相互電磁波干擾，例如，防止藍芽晶片與Wi-Fi晶片之間的訊號相互干擾。
再者，亦可藉由塗佈(coating)與回銲(reflow)方式形成該金屬層24。
又，形成該金屬層24之材質如銅(Cu)、鎳(Ni)、鐵(Fe)、鋁(Al)、不銹鋼(Sus)等。
另外，於其它實施例中，如第2C’圖所示，該金屬層24係電性連接該屏蔽件22與該基板20之內部線路202(因該內部線路202外露於該側面20c)。
因此，本發明之製法中，係藉由該屏蔽件22分隔各該半導體元件21，以避免各該半導體元件21之間發生電磁波相互干擾之問題。
本發明復提供一種半導體封裝件2,2’，係包括：一基板20、複數半導體元件21、至少一屏蔽件22以及封裝膠體23。
所述之半導體封裝件2係為射頻模組。
所述之基板20係具有內部線路202、複數電性接觸墊200與至少一接地部201。
所述之半導體元件21係設於該基板20上且電性連接該些電性接觸墊200。於一實施例中，該半導體元件21係為射頻晶片，例如，藍芽晶片或Wi-Fi晶片。
所述之屏蔽件22係立設於該基板20上並位於各該半導體元件21之間，且該屏蔽件22係電性連接該接地部201。
所述之封裝膠體23係設於該基板20上，以包覆各該半導體元件21與該屏蔽件22。於一實施例中，該屏蔽件22係外露於該封裝膠體23。
於一實施例中，所述之半導體封裝件2復包括金屬層24，係形成於該封裝膠體23上並電性連接該屏蔽件22，且該金屬層24係選自銅、鎳、鐵、鋁或不銹鋼之材質。又，該金屬層24可選擇性電性連接該內部線路202。
綜上所述，本發明之半導體封裝件及其製法，主要藉由該屏蔽件之設計，以避免各該半導體元件之間發生電磁波相互干擾之問題。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2‧‧‧半導體封裝件
20‧‧‧基板
20a‧‧‧上表面
20c‧‧‧側表面
200‧‧‧電性接觸墊
201‧‧‧接地部
21‧‧‧半導體元件
21’‧‧‧電子元件
22‧‧‧屏蔽件
22a‧‧‧外露表面
23‧‧‧封裝膠體
23a‧‧‧頂面
23c‧‧‧側面
24‧‧‧金屬層

Claims (20)

  1. 一種半導體封裝件，係包括：基板；複數半導體元件，係設於該基板上；至少一屏蔽件，係立設於該基板上並位於各該半導體元件之間；以及封裝膠體，係形成於該基板上，以包覆各該半導體元件與該屏蔽件，其中，該屏蔽件連通該封裝膠體之底表面與頂表面。
  2. 如申請專利範圍第1項所述之半導體封裝件，其中，該些半導體元件之至少一者係為射頻晶片。
  3. 如申請專利範圍第2項所述之半導體封裝件，其中，該射頻晶片係為藍芽晶片或Wi-Fi晶片。
  4. 如申請專利範圍第1項所述之半導體封裝件，其中，該屏蔽件係外露於該封裝膠體。
  5. 如申請專利範圍第4項所述之半導體封裝件，其中，該屏蔽件之外露表面係齊平該封裝膠體之該頂表面。
  6. 如申請專利範圍第1項所述之半導體封裝件，其中，該屏蔽件係為板體。
  7. 如申請專利範圍第1項所述之半導體封裝件，復包括形成於該封裝膠體上之金屬層。
  8. 如申請專利範圍第7項所述之半導體封裝件，其中，該金屬層係電性連接該屏蔽件。
  9. 如申請專利範圍第7項所述之半導體封裝件，其中， 該基板具有用以電性連接該金屬層之線路。
  10. 如申請專利範圍第7項所述之半導體封裝件，其中，該金屬層係選自由銅、鎳、鐵、鋁及不銹鋼所組成之群組之材質所製成。
  11. 一種半導體封裝件之製法，係包括：設置複數半導體元件與至少一屏蔽件於一基板上，且該屏蔽件位於各該半導體元件之間；以及形成封裝膠體於該基板上，以包覆各該半導體元件與該屏蔽件，其中，該屏蔽件連通該封裝膠體之底表面與頂表面。
  12. 如申請專利範圍第11項所述之半導體封裝件之製法，其中，該些半導體元件之至少一者係為射頻晶片。
  13. 如申請專利範圍第12項所述之半導體封裝件之製法，其中，該射頻晶片係為藍芽晶片或Wi-Fi晶片。
  14. 如申請專利範圍第11項所述之半導體封裝件之製法，其中，該屏蔽件係外露於該封裝膠體。
  15. 如申請專利範圍第14項所述之半導體封裝件之製法，其中，該屏蔽件之外露表面係齊平該封裝膠體之該頂表面。
  16. 如申請專利範圍第11項所述之半導體封裝件之製法，其中，該屏蔽件係為板體。
  17. 如申請專利範圍第11項所述之半導體封裝件之製法，復包括形成金屬層於該封裝膠體上。
  18. 如申請專利範圍第17項所述之半導體封裝件之製法， 其中，該金屬層電性連接該屏蔽件。
  19. 如申請專利範圍第17項所述之半導體封裝件之製法，其中，該基板具有用以電性連接該金屬層之線路。
  20. 如申請專利範圍第17項所述之半導體封裝件之製法，其中，該金屬層係選自由銅、鎳、鐵、鋁及不銹鋼所組成之群組之材質所製成。
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