TWI438885B - 半導體封裝件及其製法 - Google Patents

半導體封裝件及其製法 Download PDF

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TWI438885B
TWI438885B TW100109271A TW100109271A TWI438885B TW I438885 B TWI438885 B TW I438885B TW 100109271 A TW100109271 A TW 100109271A TW 100109271 A TW100109271 A TW 100109271A TW I438885 B TWI438885 B TW I438885B
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substrate
package
semiconductor
encapsulant
semiconductor package
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TW100109271A
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TW201240056A (en
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方顥儒
鍾興隆
張卓興
蔡宗賢
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矽品精密工業股份有限公司
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Priority to TW100109271A priority Critical patent/TWI438885B/zh
Priority to CN201110084587.5A priority patent/CN102683329B/zh
Priority to US13/242,182 priority patent/US20120235259A1/en
Publication of TW201240056A publication Critical patent/TW201240056A/zh
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Description

半導體封裝件及其製法
本發明係有關一種半導體封裝件，尤指一種具防內部電子元件相互電磁波干擾之半導體封裝件及其製法。
隨著半導體技術的演進，半導體產品已開發出不同封裝產品型態，而為提升電性品質，多種半導體產品具有屏蔽之功能，以防止電磁干擾(Electromagnetic Interference，EMI)產生，如第5557142號美國專利。
第7125744B2號美國專利係提供一種避免EMI之射頻(Radio frequency,RF)模組之方式。如第1A及1B圖所示，該第7125744B2號美國專利所揭示之射頻模組1係將複數半導體元件11a,11b電性連接在一基板10上，再以係如環氧樹脂之封裝膠體12包覆各該半導體元件11a,11b及基板10，並於該封裝膠體12上罩設一金屬薄膜13。該射頻模組1藉由該封裝膠體12保護該半導體元件11a,11b及基板10，並避免外界水氣或污染物之侵害，且藉由該金屬薄膜13保護該些半導體元件11a,11b免受外界EMI影響。
第7701040B2號美國專利係揭示一種複數模組相互堆疊之封裝件。如第2圖所示，該第7701040B2號美國專利所揭示之射頻模組2係於外圍包覆有屏障(shielding)層23，以避免該射頻模組2與其他模組產生相互電磁干擾。
惟，習知射頻模組1,2之外圍雖可藉由包覆金屬材以達到避免EMI之目的，但卻無法避免其內部各該半導體元件11a,11b之間的電磁波干擾(EMI)，導致訊號容易發生錯誤。
因此，如何提供一種能避免射頻模組內部之電子元件相互電磁波干擾之半導體封裝件，實為一重要課題。
為克服習知技術之種種缺失，本發明係提供一種半導體封裝件，其主要包括一具有相對之第一表面及第二表面之基板、接置且電性連接於該基板之第一表面上之複數半導體元件、覆蓋於該基板之第一表面與各該半導體元件上之封裝膠體、以及形成於該基板與封裝膠體上之金屬層；其中，該封裝膠體具有溝槽，以於該基板上劃分複數封裝單元，令每一個該封裝單元具有至少一個該半導體元件，且該金屬層復形成於該溝槽中，以包覆各該封裝單元之周圍，且令該基板之第二表面外露該金屬層。
由上可知，本發明之半導體封裝件，係藉由溝槽之設計，使基板上劃分出複數封裝單元，令每一封裝單元之間藉由金屬層作包覆，使各該半導體元件之間不會相互受電磁波干擾。
另外，本發明復提供一種據上述結構之半導體封裝件之製法。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“一”、“二”及“下”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
請參閱第3A至3E圖，係為本發明半導體封裝件之製法之示意圖。於本實施例中，所述之半導體封裝件3係可發出電磁波者，例如為射頻(Radio frequency,RF)模組。
如第3A及3A’圖所示，提供一承載件3a，係具有複數基板30(如圖中之虛線作區分)，且各該基板30具有上表面(定義為第一表面)30a及下表面(定義為第二表面)30b；接著，接置複數半導體元件31於承載件3a上，亦即各該基板30之上表面30a上。
所述之基板30之上表面30a及下表面30b上均具有複數電性接觸墊300。
所述之半導體元件31係為射頻晶片，例如：藍芽晶片或Wi-Fi(Wireless Fidelity)晶片。
再者，如第3A圖所示，該半導體元件31以打線方式，即藉由銲線310，對應電性連接該基板30上表面30a上之電性接觸墊300；或如第3A’圖所示，該半導體元件31’以覆晶方式，即藉由銲球310’，對應電性連接至該基板30上表面30a上之電性接觸墊300。
如第3B圖所示，接續第3A圖之製程，將封裝膠體32覆蓋於該承載件3a(或基板30)之上表面30a及各該半導體元件31(含該銲線310)上。
所述之封裝膠體32具有外露之頂面32a及結合至該基板30上表面30a的底面32b。
如第3C圖所示，沿著各該基板30邊緣之預定切割線L(如第3B圖所示)，切割該封裝膠體32及該承載件3a，以形成複數分離之封裝件預製品3b。該封裝件預製品3b係包括具有側表面30c、上表面30a及下表面30b之基板30、接置於該基板30上表面30a上之複數半導體元件31、及覆蓋於該基板30上表面30a與各該半導體元件31上之封裝膠體32，且該封裝膠體32經切割而具有側面32c。
如第3D及3D’圖所示，以雷射燒灼或機械切割，例如刀具切割方式，形成溝槽320於該封裝件預製品3b之封裝膠體32上，以於該基板30之上表面30a上劃分複數封裝單元3’，令每一個封裝單元3’僅具有一個半導體元件31，但非指不可包括其他無影響電磁波干擾之電子元件。
所述之溝槽320係貫穿該封裝膠體32以連通該封裝膠體32之頂面32a與該基板30之部分上表面30a。
再者，於本實施例中，其中一個半導體元件31為藍芽晶片，而另一個半導體元件31為Wi-Fi晶片。
如第3E圖所示，以例如化學鍍膜的方式，如濺鍍(sputtering)，形成金屬層33於該溝槽320中、該封裝膠體32之頂面32a與側面32c上、該基板30之側表面30c及其外露之上表面30a上，以包覆各該封裝單元3’之周圍，且令該基板之第二表面外露該金屬層，俾形成該半導體封裝件3，並藉由該金屬層33作為電磁波屏障(EMI Shielding)，以防止各該半導體元件31之間相互電磁波干擾。亦可藉由塗佈(coating)與回銲(reflow)方式形成該金屬層33。
於本實施例中，係藉由該金屬層33，以防止藍芽晶片與Wi-Fi晶片之間的訊號相互干擾。
再者，形成該金屬層33之材質如銅(Cu)、鎳(Ni)、鐵(Fe)、鋁(Al)、不銹鋼(Sus)等。
因此，本發明之半導體封裝件3及其製法，係藉由該溝槽320之設計，使該半導體封裝件3上劃分出複數封裝單元3’，令每一封裝單元3’之間藉由金屬層33之包覆，以避免該半導體封裝件3上之各該半導體元件31之間發生電磁波相互干擾之問題。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
1、2．．．射頻模組
10．．．基板
11a,11b,31,31’．．．半導體元件
12,32．．．封裝膠體
13．．．金屬薄膜
23．．．屏障層
3．．．半導體封裝件
3’．．．封裝單元
3a．．．承載件
3b．．．封裝件預製品
30．．．基板
30a．．．上表面
30b．．．下表面
30c．．．側表面
300．．．電性接觸墊
310‧‧‧銲線
310’‧‧‧銲球
32a‧‧‧頂面
32b‧‧‧底面
32c‧‧‧側面
320‧‧‧溝槽
33‧‧‧金屬層
L‧‧‧預定切割線
第1A及1B圖係為習知射頻模組之示意圖，其中，第1A圖係為立體圖，第1B圖係為剖面圖；
第2圖係為習知堆疊複數模組之封裝件之剖面圖；以及
第3A至3E圖係為本發明半導體封裝件之製法之剖面示意圖；其中，第3A’係為第3A圖之另一實施例，第3D’圖係為第3D圖之立體圖。
3．．．半導體封裝件
3’．．．封裝單元
30．．．基板
30a．．．上表面
30c．．．側表面
31．．．半導體元件
32．．．封裝膠體
32a．．．頂面
32c．．．側面
320．．．溝槽
33．．．金屬層

Claims (15)

  1. 一種半導體封裝件，係包括：基板，係具有相對之第一表面及第二表面；複數半導體元件，係接置且電性連接於該基板之第一表面上；封裝膠體，係覆蓋於該基板之第一表面與各該半導體元件上，且該封裝膠體具有溝槽，以於該基板上劃分複數封裝單元，令每一個該封裝單元具有至少一個該半導體元件；以及金屬層，係形成於該基板與封裝膠體上、及該溝槽中，以包覆各該封裝單元之周圍，且令該基板之第二表面外露該金屬層。
  2. 如申請專利範圍第1項所述之半導體封裝件，其中，該半導體封裝件係為射頻模組。
  3. 如申請專利範圍第1項所述之半導體封裝件，其中，該半導體元件係為射頻晶片。
  4. 如申請專利範圍第3項所述之半導體封裝件，其中，該射頻晶片係為藍芽晶片或Wi-Fi晶片。
  5. 如申請專利範圍第1項所述之半導體封裝件，其中，該封裝膠體具有外露之頂面與側面、及結合至該基板之第一表面的底面，且該溝槽係貫穿該封裝膠體以連通該頂面與該基板之第一表面。
  6. 如申請專利範圍第5項所述之半導體封裝件，其中，該金屬層係形成於該封裝膠體之頂面與側面上。
  7. 如申請專利範圍第1項所述之半導體封裝件，其中，該金屬層係選自銅、鎳、鐵、鋁或不銹鋼之材質。
  8. 一種半導體封裝件之製法，係包括：提供一承載件；接置複數半導體元件於該承載件上；將該封裝膠體覆蓋於該承載件上，以包覆各該半導體元件；切割該封裝膠體及承載件，以形成複數分離之該封裝件預製品，該封裝件預製品係包含：基板，係具有相對之第一表面及第二表面，其中，該基板係經切割之該承載件；複數該半導體元件，係接置且電性連接於該基板之第一表面上；及該封裝膠體，係覆蓋於該基板之第一表面與各該半導體元件上；形成溝槽於該封裝件預製品之封裝膠體上，以於該基板上劃分複數封裝單元，令每一個該封裝單元具有至少一個該半導體元件；以及形成金屬層於該基板與封裝膠體上、及該溝槽中，以包覆各該封裝單元之周圍，且令該基板之第二表面外露該金屬層。
  9. 如申請專利範圍第8項所述之半導體封裝件之製法，其中，該半導體封裝件係為射頻模組。
  10. 如申請專利範圍第8項所述之半導體封裝件之製法，其 中，該半導體元件係為射頻晶片。
  11. 如申請專利範圍第10項所述之半導體封裝件之製法，其中，該射頻晶片係為藍芽晶片或Wi-Fi晶片。
  12. 如申請專利範圍第8項所述之半導體封裝件之製法，其中，該封裝膠體具有外露之頂面與側面、及結合至該基板之第一表面的底面，且該溝槽係貫穿該封裝膠體以連通該頂面與該基板之第一表面。
  13. 如申請專利範圍第12項所述之半導體封裝件之製法，其中，該金屬層係形成於該封裝膠體之頂面與側面上。
  14. 如申請專利範圍第8項所述之半導體封裝件之製法，其中，形成該溝槽之方式係為雷射或機械切割。
  15. 如申請專利範圍第8項所述之半導體封裝件之製法，其中，該金屬層係選自銅、鎳、鐵、鋁或不銹鋼之材質。
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