TW201434129A - 多晶片封裝件及其製法 - Google Patents

多晶片封裝件及其製法 Download PDF

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TW201434129A
TW201434129A TW102105957A TW102105957A TW201434129A TW 201434129 A TW201434129 A TW 201434129A TW 102105957 A TW102105957 A TW 102105957A TW 102105957 A TW102105957 A TW 102105957A TW 201434129 A TW201434129 A TW 201434129A
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encapsulant
substrate
chip package
semiconductor elements
electromagnetic shielding
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TW102105957A
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徐泰錝
江政育
陳苗汶
江文榮
李信宏
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矽品精密工業股份有限公司
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Priority to TW102105957A priority Critical patent/TW201434129A/zh
Priority to US13/960,064 priority patent/US9305885B2/en
Publication of TW201434129A publication Critical patent/TW201434129A/zh
Priority to US15/054,845 priority patent/US9887102B2/en

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Abstract

一種多晶片封裝件，係包括：具有接地結構之基板；設置並電性連接該基板之兩半導體元件；形成於該基板上並包覆該等半導體元件之封裝膠體，且該封裝膠體上形成有複數圓孔，該等圓孔係位於該等半導體元件之間；以及形成於各該圓孔中之電磁屏蔽體，藉由電磁屏蔽體連接該基板之接地結構以達到電磁屏蔽之效果。

Description

多晶片封裝件及其製法
本發明係有關一種半導體封裝結構，尤指一種多晶片封裝件及其製法。
隨著電子產業的蓬勃發展，市面上的電子產品以輕量、小型、高速及多功能為訴求，使產品內部的多晶片封裝件，朝高運算速度、高元件密度、高複雜度發展，更將其他生物、光學、機械、電機、磁性等多功能之電子元件整合於同一封裝件中。
為符合多晶片封裝件體積輕薄短小的趨勢，系統級封裝(System in Package，SiP)遂發展出多晶片模組(Multi-chip Module；MCM)的封裝結構。然而，此種結構使元件密度增加，導致設置於同一基板之晶片間產生電磁干擾(electromagnetic interference，EMI)之現象。
為改善晶片間產生電磁干擾之現象，目前業界開發一種具電磁屏蔽功能之多晶片封裝件。如第1A及1B圖所示，習知具電磁屏蔽功能之多晶片封裝件1包括：於一基板10上設置並電性連接二半導體元件11a,11b；於該基板 10上形成封裝膠體12；於該封裝膠體12中形成有一長條形溝槽120，且該長條形溝槽120係形成於該兩半導體元件11a,11b之間；以及電磁屏蔽體13，係形成於該長條形溝槽120中，並電性連接基板10之接地結構100。此外，亦可於該封裝膠體12中形成複數條狀電磁屏蔽體13’，如第1B’圖所示。
然而，習知長條形溝槽120係以雷射方式形成，該封裝膠體12於長時間燃燒下會過熱，致使該等半導體元件11a,11b損毀或該封裝膠體12發生翹曲。
再者，形成該長條形溝槽120亦需較長時間，致使生產成本上升。
因此，如何克服習知技術中之種種問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之缺失，本發明提供一種多晶片封裝件，係包括：基板，係具有接地結構；二半導體元件，係設置並電性連接於該基板上；封裝膠體，係形成於該基板上，以包覆該等半導體元件，該封裝膠體於該等半導體元件間並形成有複數圓孔；以及電磁屏蔽體，係形成於各該圓孔中，以令該電磁屏蔽體接地連接該接地結構。
本發明復提供一種多晶片封裝件之製法，係包括：於一表面上設有二半導體元件之基板上形成封裝膠體，使該等半導體元件嵌埋於該封裝膠體中，其中，該基板具有接地結構；於該等半導體元件間形成複數貫穿該封裝膠體之 圓孔；以及於各該圓孔中形成電磁屏蔽體，以令該電磁屏蔽體接地連接該接地結構。
本發明又提供一種多晶片封裝件，係包括：具有接地層之基板；二半導體元件，係設置並電性連接於該基板上；封裝膠體，係形成於該基板上，以包覆該等半導體元件，該封裝膠體中並形成有複數貫穿該封裝膠體及基板之圓孔，且該等圓孔係位於該等半導體元件間；以及電磁屏蔽體，係形成於各該圓孔中，以令該電磁屏蔽體接地連接該接地層。
本發明另提供一種多晶片封裝件之製法，係包括：於一表面上設有二半導體元件之基板上形成封裝膠體，使該等半導體元件嵌埋於該封裝膠體中，其中，該基板具有接地層；於該等半導體元件間形成複數貫穿該封裝膠體及基板之圓孔；以及於各該圓孔中形成電磁屏蔽體，以令該電磁屏蔽體接地連接該接地層。
前述兩種多晶片封裝件之製法中，係以雷射鑽孔之方式形成該等圓孔。
前述兩種多晶片封裝件及其製法中，復包括形成條形孔於該封裝膠體中，且該條形孔與該圓孔呈間隔排列。另外，該電磁屏蔽體復形成於各該條形孔中。
前述兩種多晶片封裝件及其製法中，復包括形成散熱件於該封裝膠體上，俾使該多晶片封裝件具有較佳之散熱效果。
由上可知，本發明之多晶片封裝件及其製法，係藉由 形成圓孔，以縮短雷射鑽孔之時間，而能避免長時間加工而導致封裝膠體過熱或翹曲及半導體元件損毀等缺失。
再者，相較於習知之長條形溝槽，本發明之圓孔之製程時間較短，因而能降低生產成本。
又，於本發明之多晶片封裝件中，於封裝膠體上設置散熱件，使本發明之電磁屏蔽體除了發揮其電磁屏蔽之效果外，亦可有效將半導體元件運作時所產生之熱傳導至散熱件，提供本發明之多晶片封裝件優異之散熱效果。
1、2、3‧‧‧多晶片封裝件
10、20‧‧‧基板
100、200‧‧‧接地結構
11a、11b、21a、21b‧‧‧半導體元件
12、22‧‧‧封裝膠體
120‧‧‧長條形溝槽
13、13’、23‧‧‧電磁屏蔽體
201‧‧‧接地層
220、220”‧‧‧圓孔
220’‧‧‧條形孔
24‧‧‧散熱件
A‧‧‧交界區域
第1A至1B’圖係為習知多晶片封裝件之示意圖，其中，第1B圖係為第1A圖之俯視圖，第1B’圖係為第1B圖之另一態樣之俯視圖；第2A至2C圖係為本發明之多晶片封裝件之製法的剖面示意圖，其中，第2B’圖為第2B圖之俯視圖，第2B”圖為第2B’圖之另一實施例；第3圖係為本發明多晶片封裝件之另一實施例之剖面示意圖；以及第4圖係為本發明多晶片封裝件之又一實施例之剖面示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小 等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「上」、「一」及「二」等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A至2C圖係為本發明之多晶片封裝件2之製法的剖面示意圖。
如第2A圖所示，提供一表面上設置並電性連接有二半導體元件21a,21b之基板20，且於該基板20上形成有覆蓋該等半導體元件21a,21b之封裝膠體22，使該等半導體元件21a,21b係嵌埋於該封裝膠體22中。
於本實施例中，該基板20具有相連接之一接地結構200與一接地層201，且該等半導體元件21a,21b係為晶片。
再者，有關基板20之種類繁多，且為習知者即能適用，故不再贅述。
又，有關封裝膠體22之形成方式及材料，為習知者即能適用，在此不再贅述。
另外，該等半導體元件21a,21b係藉由銲線(未圖示)或導電凸塊(未圖示)電性連接至該基板20，但不以此為限。
如第2B及2B’圖所示，於該等半導體元件21a,21b之間形成複數貫穿該封裝膠體22之圓孔220，至少一該圓孔220外露該接地結構200。
於本實施例中，係於該等半導體元件21a,21b間定義一交界區域A，於該交界區域A係利用雷射形成該等圓孔220，且各該圓孔220之間具有間距。
於另一實施例中，可形成複數條形孔220’於該封裝膠體22之交界區域A上，且該條形孔220’與該圓孔220呈間隔排列，如第2B”圖所示。
再者，形成該圓孔220及條形孔220’之先後順序並未有特殊限制，較佳者係於形成該條形孔220’後，再形成該圓孔220。
又，形成該圓孔220及條形孔220’之方法並未有特別限制，僅需使用一般雷射鑽孔即可。
本發明之方法因非使用連續切割，故可避免於雷射鑽孔時，該封裝膠體22過度受熱而發生翹曲之問題，且能避免發生晶片損毀而導致不良品增加進而提高生產成本之缺點。
如第2C圖所示，係接續第2B及2B’圖之製程，於各該圓孔220中形成電磁屏蔽體23，且該電磁屏蔽體23係與該基板20之接地結構200相連接，以製成一多晶片封裝件2。
於本實施例中，該電磁屏蔽體23之材質為含有金屬材質之導電膠、銅或銲料，該電磁屏蔽體23與該基板20之 接地結構200進行導通，具有屏障並阻絕電磁干擾之功能，藉以達到電磁屏蔽之效果。
若接續第2B”圖之製程，該電磁屏蔽體23復形成於該些條形孔220’中，俾連接該接地結構200或接地層201。
本發明之多晶片封裝件2係包括：一具有接地結構200之基板20、設於該基板20上並電性連接該基板20之二半導體元件21a,21b、形成於該基板20上以覆蓋該等半導體元件21a,21b之封裝膠體22；形成於該封裝膠體22中並外露該接地結構200且位於該等半導體元件21a,21b間之複數圓孔220；以及形成於各該圓孔220中之電磁屏蔽體23，使該電磁屏蔽體23接地連接該接地結構200。
第3圖係本發明之多晶片封裝件3之另一實施例，係利用鍍覆法形成金屬膜或貼合一金屬片的方式於該封裝膠體22上形成散熱件24，能有效使該等半導體元件21a,21b於運作時所產生之熱排出。
於本實施例中，各該圓孔220中所形成之電磁屏蔽體23係與該散熱件24接觸。
又，由於該電磁屏蔽體23之材質為含有金屬材質之導電膠、銅或銲料，因此，該電磁屏蔽體23具有良好之熱傳導性，能有效將熱能傳遞至散熱件24，使該多晶片封裝件3具有良好之散熱效果。
第4圖係本發明之多晶片封裝件之另一實施例，係將圓孔220”貫穿該封裝膠體22及基板20，使該圓孔220”直接與該基板20之接地層201接地連接。
綜上所述，本發明之多晶片封裝件及其製法，藉由形成電磁屏蔽體於圓孔中之設計，不僅使製程更為快速、生產成本更低，且能避免封裝膠體翹曲或晶片損壞等問題。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2‧‧‧多晶片封裝件
20‧‧‧基板
200‧‧‧接地結構
21a,21b‧‧‧半導體元件
22‧‧‧封裝膠體
220‧‧‧圓孔
23‧‧‧電磁屏蔽體

Claims (11)

  1. 一種多晶片封裝件，係包括：基板，係具有接地結構；二半導體元件，係設置並電性連接於該基板上；封裝膠體，係形成於該基板上，以包覆該等半導體元件，該封裝膠體於該等半導體元件間並形成有複數圓孔；以及電磁屏蔽體，係形成於各該圓孔中，以令該電磁屏蔽體接地連接該接地結構。
  2. 一種多晶片封裝件，係包括：基板，係具有接地層；二半導體元件，係設置並電性連接於該基板上；封裝膠體，係形成於該基板上，以包覆該等半導體元件，且該封裝膠體中並形成有複數貫穿該封裝膠體及基板之圓孔，且該等圓孔係位於該等半導體元件間；以及電磁屏蔽體，係形成於各該圓孔中，以令該電磁屏蔽體接地連接該接地層。
  3. 如申請專利範圍第1或2項所述之多晶片封裝件，其中，該封裝膠體復形成有至少一條形孔，且該條形孔與該圓孔呈間隔排列。
  4. 如申請專利範圍第3項所述之多晶片封裝件，其中，該電磁屏蔽體復形成於各該條形孔中。
  5. 如申請專利範圍第1或2項所述之多晶片封裝件，復 包括散熱件，係形成於該封裝膠體上。
  6. 一種多晶片封裝件之製法，係包括：於一表面上設有二半導體元件之基板上形成封裝膠體，使該等半導體元件嵌埋於該封裝膠體中，其中，該基板具有接地結構；於該等半導體元件間形成複數貫穿該封裝膠體之圓孔；以及於各該圓孔中形成電磁屏蔽體，以令該電磁屏蔽體接地連接該接地結構。
  7. 一種多晶片封裝件之製法，係包括：於一表面上設有二半導體元件之基板上形成封裝膠體，使該等半導體元件嵌埋於該封裝膠體中，其中，該基板具有接地層；於該等半導體元件間形成複數貫穿該封裝膠體及基板之圓孔；以及於各該圓孔中形成電磁屏蔽體，以令該電磁屏蔽體接地連接該接地層。
  8. 如申請專利範圍第6或7項所述之多晶片封裝件之製法，復包括形成至少一條形孔於該封裝膠體中，且該條形孔與該圓孔呈間隔排列。
  9. 如申請專利範圍第8項所述之多晶片封裝件之製法，其中，該電磁屏蔽體復形成於各該條形孔中。
  10. 如申請專利範圍第6或7項所述之多晶片封裝件之製法，復包括形成散熱件於該封裝膠體上。
  11. 如申請專利範圍第6或7項所述之多晶片封裝件之製法，其中，係以雷射鑽孔之方式形成該等圓孔。
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