WO2016173507A1 - 一种集成电路管芯及制造方法 - Google Patents
一种集成电路管芯及制造方法 Download PDFInfo
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- WO2016173507A1 WO2016173507A1 PCT/CN2016/080514 CN2016080514W WO2016173507A1 WO 2016173507 A1 WO2016173507 A1 WO 2016173507A1 CN 2016080514 W CN2016080514 W CN 2016080514W WO 2016173507 A1 WO2016173507 A1 WO 2016173507A1
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Definitions
- the present invention relates to the field of integrated circuits, and more particularly to an integrated circuit die and a method of fabricating the same.
- the power density of the chips is also higher.
- the distribution of power density is non-uniform throughout the IC chip. In areas with high power density, a large amount of heat is generated in a small area, so that hot spots with high temperatures are formed on the surface of the chip, and the temperature of these "hot spots" is higher than the average temperature of the entire IC chip. a lot of. If the effective IC chip thermal management and heat dissipation design cannot be performed, the heat of the hot spot area can be quickly and effectively diffused, which may easily lead to the temperature of the hot spot of the chip being too high and the chip not working properly.
- FIG. 1 shows the die-up plastic ball grid array package 10, on which the heat sink 12 is integrated.
- the IC die 11 is mounted on the substrate 15 by a die attach material 13 and is connected to the leads 17.
- the package 10 can be connected to a printed wiring board (not shown in FIG. 1) by solder balls 14.
- the heat sink 12 is disposed on the substrate 15 for discharging heat of the die 11.
- the molding material 16 seals the package 10.
- the material of the heat sink 12 is a conductive material, and therefore, the heat sink 12 and the die 11 are insulated by an insulating molding material 16.
- most of the heat sink 12 is located on the molding material 16, that is, most of it is located on the sealing layer composed of the molding material 16.
- the heat dissipation method adopted in the package shown in FIG. 1 is to design a heat on the IC chip package structure.
- the channel diffuses the heat of the hot spot through the heat sink.
- This method of heat dissipation is to indiscriminately cool the entire chip, removing heat from the entire package, thereby maintaining the temperature of the chip below the upper operating limit.
- the added heat sink cannot be infinitely close to the IC die. Since the IC die is a heat source, the heat sink is added to the IC chip package. The method is insufficient to reduce the temperature of the hot spot on the surface of the IC chip, or has a limited effect in lowering the temperature of the hot spot, which causes the operation of the IC chip to be still limited by the temperature of the hot spot on the surface of the IC chip.
- the current heat dissipation method of the IC chip is mainly because the heat sink is added to the IC chip package structure, and the heat sink method can reduce the hot spot on the surface of the IC chip because the heat sink cannot be infinitely close to the IC die.
- the role of temperature is limited.
- Embodiments of the present invention provide an integrated circuit die and a manufacturing method for solving the problem that the heat dissipation method using the current IC chip has a limited effect in reducing the temperature of the hot spot on the surface of the IC chip.
- an integrated circuit die comprising:
- interconnect layer overlying the active device, the interconnect layer comprising a plurality of metal layers and a plurality of dielectric layers, the plurality of metal layers and the plurality of dielectric layers being alternately disposed;
- the multilayer metal a metal layer in the layer farthest from the active device includes a metal trace and a metal pad;
- the heat dissipation layer covering an area of the interconnection layer except a position corresponding to the metal pad, the heat dissipation layer is located under the package layer, and the package layer includes a molding material, the heat dissipation layer Includes materials that have a thermal conductivity greater than the preset value and are electrically insulating.
- the heat dissipation layer covers the distance On the metal layer farthest from the active device.
- the interconnect layer further includes a passivation layer covering the metal layer farthest from the active device An area other than the corresponding position of the metal pad, the heat dissipation layer covering the passivation layer.
- the integrated circuit chip including the integrated circuit die is a wire bonding chip, and the heat dissipation layer is formed after performing a wire bonding process, and the heat dissipation layer is further Covering the corresponding position of the metal pad.
- the integrated circuit chip including the integrated circuit die Wire the chip or flip chip for the wire.
- a method of fabricating an integrated circuit die comprising:
- the metal layer farthest from the active device includes metal traces and metal pads;
- a heat dissipation layer including a material having a thermal conductivity greater than a predetermined value and electrically insulating; the heat dissipation layer being located in an encapsulation layer including a molding material under.
- forming the heat dissipation layer on a region other than the corresponding position of the metal pad on the interconnect layer includes:
- a window is opened in a position corresponding to the metal pad in the heat dissipation layer.
- the integrated circuit die further includes a passivation layer, and a region other than the corresponding position of the metal pad is formed on the interconnect layer
- the heat dissipation layer includes:
- a window is opened in a position corresponding to the metal pad in the heat dissipation layer.
- the integrated circuit die further includes a passivation layer, if the integrated circuit chip including the integrated circuit die is a wire bonding chip, and the heat dissipation layer After the wire bonding process is performed, the heat dissipation layer is formed on a region other than the corresponding position of the metal pad on the interconnect layer, including:
- the heat dissipation layer is formed on a surface of the passivation layer.
- the integrated circuit die and the manufacturing method provided by the embodiments of the present invention because the heat dissipation layer covers an area on the interconnect layer in the IC die except the corresponding position of the metal pad, and is located under the package layer,
- the heat dissipation layer can be closer to the IC die. Since the material of the heat dissipation layer is a material having a thermal conductivity greater than a preset value and electrically insulated, the heat dissipation layer can rapidly diffuse heat in a region of the IC die with a large power density. On the surface of the die, thereby increasing the heat dissipation area of the IC chip including the IC die, and improving the heat dissipation capability of the chip.
- FIG. 1 is a cross-sectional view of an IC chip in the prior art
- FIG. 2 is a cross-sectional view of a wire bonding chip according to an embodiment of the present invention.
- FIG. 3 is a cross-sectional view of a flip chip according to an embodiment of the present invention.
- 4a is a cross-sectional view of an IC die in a wire bonding chip according to an embodiment of the present invention
- 4b is a cross-sectional view of an IC die in a flip chip according to an embodiment of the present invention.
- 5a is a cross-sectional view of an IC die in a wire bonding chip according to an embodiment of the present invention
- 5b is a third cross-sectional view of an IC die in a wire bonding chip according to an embodiment of the present invention.
- 6a is a cross-sectional view of an IC die in a flip chip according to an embodiment of the present invention.
- 6b is a third cross-sectional view of an IC die in a flip chip according to an embodiment of the present invention.
- FIG. 7 is a top plan view of an IC die according to an embodiment of the present invention.
- the IC die and the method for fabricating the same cover a position corresponding to a metal pad on an interconnect layer in an IC die by using a heat dissipation layer made of a material having a thermal conductivity greater than a preset value and electrically insulating. Outside the area, and the heat dissipation layer is located under the encapsulation layer, thereby rapidly dissipating heat of the area of the IC die with a large power density to the entire surface of the die, which increases the heat dissipation area of the IC chip and improves the chip Cooling capacity.
- the IC chip formed after the package includes two types, one is the wire bonding chip shown in FIG. 2, and the other is shown in FIG. Flip chip.
- the wire bonding chip shown in FIG. 2 includes an IC die 102, a die bond material 101, a lead 103, a molding material 104, a substrate 105, and a solder ball 106.
- the general process flow of the wire bond chip package is: first processing The IC die 102 is discharged, and the IC die 102 is fixed on the substrate 105 through the die bond material 101, and then the leads 103 are soldered to the IC die 102 and the substrate 105 by wire bonding, and then passed through the molding material 104.
- the IC die 102 is hermetically sealed, and finally the solder balls 106 are soldered to the substrate 105 to complete the package of the entire wire bond chip.
- the flip chip shown in FIG. 3 includes an IC die 202, a metal bump (BUMP) 201, an underfill 203, a molding material 204, a substrate 205, and solder balls 206.
- the general process flow for a flip chip package is to first process the IC die 202, which is grown on the IC die 202. The IC die 202 is then flipped over the substrate 205, and the physical and electrical connection of the IC die 202 to the substrate 205 is achieved by the BUMP 201.
- the bottom filling material 203 is injected to protect the BUMP 201, then the IC die 202 is solid-sealed by the molding material 204, and finally the solder ball 206 is soldered to the substrate 205 to complete the packaging of the entire flip chip.
- An active device overlying the substrate
- interconnect layer overlying the active device, the interconnect layer comprising a plurality of metal layers and a plurality of dielectric layers, the plurality of metal layers and the plurality of dielectric layers being alternately disposed;
- the multilayer metal a metal layer in the layer farthest from the active device includes a metal trace and a metal pad;
- the heat dissipation layer covering an area of the interconnection layer except a position corresponding to the metal pad, the heat dissipation layer is located under the package layer, and the package layer includes a molding material, the heat dissipation layer Includes materials that have a thermal conductivity greater than the preset value and are electrically insulating.
- the preset value may be 10 W/m-k.
- the alternating arrangement of the multi-layer metal layer and the multi-layer dielectric layer means that a first dielectric layer is formed on the active device, then a first metal layer is formed on the first dielectric layer, and then on the first metal layer. A second dielectric layer is formed, and then a second metal layer is formed on the second dielectric layer, until the number of metal layers and dielectric layers meets the requirements.
- the materials of the dielectric layers of each layer may be different materials, but all are electrically insulating materials.
- the metal traces in the metal layer in the interconnect layer are used to connect the electrodes in the active device at corresponding locations, and the metal pads in the metal layer in the interconnect layer are used to extract the electrodes in the active device It is convenient for practical application to the outside of the package that encapsulates the IC die.
- the heat dissipation layer may cover a portion of the interconnect layer in the IC die other than the metal pad, and may also cover all regions of the interconnect layer in the IC die except the metal pad.
- the heat dissipation layer covers the metal layer of the IC die that is farthest from the active device of the IC die in the interconnect layer of the IC die, except for the position corresponding to the metal pad.
- the material of the heat dissipation layer is an insulating material, the heat dissipation layer in FIGS. 4a and 4b replaces the passivation layer in the IC die of the prior art.
- FIG. 4a is a schematic structural view of an IC die after replacing the passivation layer with a heat dissipation layer when the IC chip is a wire bonding chip.
- Figure 4a is a cross-sectional view of the dashed box 100 of Figure 2.
- 4a includes a lead 103, a metal pad 107 in the metal layer of the interconnect layer 112 that is furthest from the active device 111, a heat sink layer 109, and a substrate 110.
- the heat dissipation layer 109 functions as a passivation layer.
- an active device 111 is first formed on the substrate 110, and then a plurality of metal layers and a plurality of dielectric layers, a plurality of metal layers and a plurality of layers are alternately formed on the active device 111.
- the dielectric layer constitutes an interconnect layer 112 in which a metal pad 107 is located in the metal layer farthest from the active device 111, and finally a heat dissipation layer is formed on the metal layer including the metal pad 107.
- the window in the heat dissipation layer is open to the area of the metal pad, the window can be smaller than the metal pad facing the window, as long as it can meet the IC die can pass through the metal pad in the area facing the window and strengthen the heat dissipation IC chip
- the substrates can be connected.
- FIG. 4b is a schematic view showing the structure of the IC die after replacing the passivation layer with a heat dissipation layer when the IC chip is a flip chip
- FIG. 4b is a cross-sectional view of the broken line frame 200 of FIG. 4b includes a metal bump 201, a heat dissipation layer 207, a bump metal (209), a metal pad 210 in a metal layer farthest from the active device 212 in the interconnect layer 213. And a substrate 211.
- the heat sink layer 207 functions as a passivation layer.
- an active device 212 is first formed on the substrate 211, and then a plurality of metal layers and a plurality of dielectric layers, a plurality of metal layers and a plurality of layers are alternately formed on the active device 212.
- the dielectric layer constitutes an interconnect layer 213 in which a metal pad 210 is located in the metal layer farthest from the active device 212, and finally a heat dissipation layer is formed on the metal layer including the metal pad 210.
- the window 207 in the heat dissipation layer 207 is open to the area of the metal pad 210, the window can be smaller
- the metal pad facing the window can be connected to the substrate in the IC chip of the heat-dissipating IC chip through the metal pad in the area facing the window, and then the UBM209 is sequentially formed on the metal pad 210 and Metal bump 201.
- the passivation layer covers the metal layer farthest from the active device except the metal pad The area other than the location, the heat dissipation layer overlying the passivation layer.
- the IC chip is a wire bonding chip
- the IC die provided by the embodiment of the present invention is as shown in FIG. 5a and FIG. 5b.
- the IC chip is a flip chip
- the IC die provided by the embodiment of the present invention is as shown in FIG. 6a and FIG. 6b.
- the IC die 102 shown in FIG. 5a includes a substrate 110, an active device 111, an interconnect layer 112, a passivation layer 108, and a metal in a metal layer of the interconnect layer 112 that is furthest from the active device 111.
- the pad 107; the heat dissipation layer 109 overlies the passivation layer 108, wherein the window of the passivation layer 108 facing a metal pad 107 is smaller than or equal to the window of the heat dissipation layer 109 of the metal pad 107.
- Figure 5a is a cross-sectional view of the dashed box 100 of Figure 2.
- an active device 111 is first formed on the substrate 110, and then a plurality of metal layers and a plurality of dielectric layers, a plurality of metal layers and a plurality of layers are alternately formed on the active device 111.
- the multilayer dielectric layer constitutes an interconnect layer 112 comprising a metal pad 107 in a metal layer furthest from the active device 111 in the interconnect layer 112 and then forming a passivation on the metal layer comprising the metal pad 107
- the layer 108 is opened in a region of the passivation layer 108 facing the metal pad, and then a heat dissipation layer 109 is formed on the passivation layer 108, and a window is opened in the region of the heat dissipation layer 109 facing the metal pad 107, and finally Wire bonding.
- the window in the heat dissipation layer 109 facing a metal pad 107 is not smaller than the window of the passivation layer 108 of the metal pad 107. That is, in the manufacturing process of the IC die shown in FIG. 5a, the heat dissipation layer 109 is first formed, and then wire bonding is performed.
- the IC die 102 shown in FIG. 5b includes a substrate 110, an active device 111, an interconnect layer 112, a passivation layer 108, and a metal in the metal layer of the interconnect layer 112 that is furthest from the active device 111.
- the pad 107; the heat dissipation layer 109 is overlaid on the passivation layer 108, and the lead 103 is further included in FIG. 5b.
- Figure 5b is a cross-sectional view of the dashed box 100 of Figure 2.
- the active device 111 is first formed on the substrate 110, and then the multilayer metal layer and the multilayer dielectric layer are alternately formed on the active device 111, and the multilayer metal layer and The multilayer dielectric layer constitutes an interconnect layer 112 comprising a metal pad 107 in a metal layer furthest from the active device 111 in the interconnect layer 112 and then forming a passivation on the metal layer comprising the metal pad 107
- the layer 108, and the window of the passivation layer 108 facing the metal pad 107 is opened, then wire bonding is performed, and finally a heat dissipation layer 109 is formed on the active surface of the IC die.
- the heat dissipation layer 109 on the metal pad 107 may be removed, that is, a window is opened in the heat dissipation layer 109 facing the metal pad 107 (ie, as shown in FIG. 5b), facing a metal pad 107.
- the window of the passivation layer 108 is not limited to the size relationship of the window of the heat dissipation layer 109 of the metal pad 107; of course, after the heat dissipation layer 109 is formed, the heat dissipation layer on the metal pad 107 may not be removed. Further, in Fig. 5b, the window of the passivation layer 108 facing the one metal pad 107 is larger than the window of the heat dissipation layer 109 of the metal pad 107.
- the IC die 202 shown in FIG. 6a includes a substrate 211.
- the active device 212, the interconnect layer 213, and the UBM 209 are grown on the metal pad 210.
- the BUMP 201 is grown on the UBM 209, and the heat dissipation layer 207 is over the passivation layer 208.
- the metal pad 210 is located in a layer of metal in the interconnect layer 213 that is furthest from the active device 212.
- Figure 6a is a cross-sectional view of the dashed box 200 of Figure 3.
- an active device 212 is first formed on the substrate 110, and then a plurality of metal layers and a plurality of dielectric layers, a plurality of metal layers and a plurality of layers are alternately formed on the active device 212.
- the multilayer dielectric layer constitutes an interconnect layer 213 including a metal pad 210 in a metal layer furthest from the active device 212 in the interconnect layer 213, and then forming a passivation on the metal layer including the metal pad 210 Layer 208, and opening a window in the region of the passivation layer 208 facing the metal pad 210, and growing the UBM 209 in the window region, then forming a heat dissipation layer 207 on the passivation layer 208, and facing the metal pad 210 in the heat dissipation layer 207
- the area opens the window and finally grows BUMP201 on the UBM209. Its
- the window in the heat dissipation layer 207 facing a metal pad 210 is not smaller than the window of the passivation layer 208 of the metal pad 210.
- the IC die 202 shown in FIG. 6b includes a substrate 211.
- the active device 212, the interconnect layer 213, and the UBM 209 are grown on the metal pad 210.
- the BUMP 201 is grown on the UBM 209, and the heat dissipation layer 207 is over the passivation layer 208.
- the metal pad 210 is located in a layer of metal in the interconnect layer 213 that is furthest from the active device 212.
- Figure 6b is a cross-sectional view of the dashed box 200 of Figure 3.
- an active device 212 is first formed on the substrate 110, and then a plurality of metal layers and a plurality of dielectric layers, a plurality of metal layers and a plurality of layers are alternately formed on the active device 212.
- the multilayer dielectric layer constitutes an interconnect layer 213 including a metal pad 210 in a metal layer furthest from the active device 212 in the interconnect layer 213, and then forming a passivation on the metal layer including the metal pad 210 Layer 208, and opening a window in the region of the passivation layer 208 facing the metal pad 210, and growing the UBM 209 in the window region, then growing the BUMP 201 on the UBM 209, then forming a heat dissipation layer 207 on the passivation layer 208, and
- the IC die in the chip is connected to the substrate in the IC chip through the BUMP 201. Therefore, it is finally necessary to remove the heat dissipation layer 207 on the surface of the BUMP 201.
- the window in the heat dissipation layer 207 facing a metal pad 210 is not smaller than the window of the passivation layer 208 of the metal pad 210.
- FIG. 7 is a top plan view of any of the IC dies shown in FIGS. 5a, 5b, 6a, and 6b.
- Figure 7 is a top plan view of the IC die shown in Figure 4a or Figure 4b.
- the 7 includes a metal layer 31 and a heat dissipation layer 32 which are the farthest from the active device in the interconnection layer on the active device in the IC die, wherein the metal layer 31 can be further divided into a metal layer.
- the metal trace 311 and the metal pad 312 open a few windows in the heat dissipation layer 32 opposite to the metal pad 312 in the metal layer 31.
- the window may be smaller than the metal pad, that is, the metal pad 312 is to be used.
- the passivation layer covered by the upper window position is removed, so that the IC die can be passivated by uncovered
- the metal pad 312 of the layer is connected to the substrate in the IC chip.
- the pattern of a metal layer that is the farthest from the active device in the interconnect layer overlying the active device in the IC die is not limited to the pattern shown in FIG.
- the metal layer farthest from the active device includes metal traces and metal pads;
- a heat dissipation layer including a material having a thermal conductivity greater than a predetermined value and electrically insulating; the heat dissipation layer being located in an encapsulation layer including a molding material under.
- the corresponding position of the metal pad may be the area facing the metal pad.
- a heat dissipation layer may be formed on a portion of the interconnect layer in the IC die other than the metal pad, or all but the metal pad on the interconnect layer in the IC die.
- a heat dissipation layer is formed in the area.
- the heat dissipation layer can directly contact the IC die, and the heat on the IC die can be quickly diffused to the entire chip, thereby increasing the heat dissipation area of the IC chip and improving the heat dissipation capability of the chip.
- forming the heat dissipation layer on a region other than a position corresponding to the metal pad on the interconnect layer including:
- a window is opened in a position corresponding to the metal pad in the heat dissipation layer.
- the IC die can be wire bonded, BUMP or otherwise connected to the substrate in the IC chip through a region of the metal pad that is not covered by the heat sink layer.
- the structure of the IC die is as shown in FIG. 4a; when the IC die passes through the metal pad
- the structure diagram of the IC die is as shown in FIG. 4b. Show.
- the heat dissipation layer is formed on a region other than the corresponding position of the metal pad on the interconnect layer, including:
- Opening a window corresponding to the metal pad in the passivation layer that is, removing a passivation layer at a position corresponding to the metal pad;
- a window is opened in a position corresponding to the metal pad in the heat dissipation layer, that is, a heat dissipation layer at a position corresponding to the metal pad is removed.
- the IC die can be wire bonded, BUMP or otherwise connected to the substrate in the IC chip through a region of the metal pad that is not covered by the heat sink layer and the passivation layer.
- the structure of the IC die is as shown in FIG. 5a or FIG. 5b;
- the structure of the IC die is as shown in FIG. 6a or 6b.
- the region on the interconnection layer except the corresponding position of the metal pad forms the The heat dissipation layer includes:
- the heat dissipation layer is formed on a surface of the passivation layer. In this process, it is not necessary to open a window in a position corresponding to the metal pad in the heat dissipation layer.
- the IC die and the manufacturing method thereof provided by the embodiments of the present invention are applicable not only to the wire bonding chip and the flip chip, but also to the chip in other package forms.
- the material of the heat dissipation layer in the heat-dissipating IC chip and the manufacturing method thereof provided by the embodiment of the present invention is a material having high thermal conductivity and electrical insulation, and the thickness of the heat dissipation layer may be any thickness required for the process, and Further, the method of forming the heat dissipation layer is not limited to methods such as physical sputtering, chemical deposition, plating, and coating.
- modules in the apparatus in the embodiments may be distributed in the apparatus of the embodiment according to the description of the embodiments, or the corresponding changes may be located in one or more apparatuses different from the embodiment.
- the modules of the above embodiments may be combined into one module, or may be further split into multiple sub-modules.
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Abstract
Description
Claims (9)
- 一种集成电路管芯,其特征在于,包括:衬底;有源器件;互连层,覆盖在所述有源器件上,所述互连层包括多层金属层和多层介质层,所述多层金属层和所述多层介质层交替设置;所述多层金属层中距离所述有源器件最远的一层金属层包括金属走线和金属焊垫;及散热层,所述散热层覆盖在所述互连层上除所述金属焊垫对应的位置以外的区域,所述散热层位于封装层之下,所述封装层包括塑封材料,所述散热层包括导热率大于预设值且电绝缘的材料。
- 如权利要求1所述的集成电路管芯,其特征在于,所述散热层覆盖在所述距离所述有源器件最远的一层金属层上。
- 如权利要求1所述的集成电路管芯,其特征在于,所述互连层还包括钝化层,所述钝化层覆盖在所述距离所述有源器件最远的一层金属层上除所述金属焊垫对应的位置以外的区域,所述散热层覆盖在所述钝化层上。
- 如权利要求1所述的集成电路管芯,其特征在于,包含所述集成电路管芯的集成电路芯片为引线键合芯片,所述散热层形成于施行引线键合工艺之后,所述散热层还覆盖在所述金属焊垫对应的位置。
- 如权利要求1~3任一所述的集成电路管芯,其特征在于,包含所述集成电路管芯的集成电路芯片为引线键合芯片或倒装芯片。
- 一种集成电路管芯的制造方法,其特征在于,包括:在衬底上形成有源器件;在所述有源器件的表面上以交替设置的方式形成多层金属层和多层介质层;所述多层金属层和多层介质层构成互连层;所述多层金属层中距离所述有源器件最远的一层金属层包括金属走线和金属焊垫;在所述互连层之上、除所述金属焊垫对应的位置以外的区域形成包括导 热率大于预设值且电绝缘的材料的散热层;所述散热层位于包括塑封材料的封装层之下。
- 如权利要求6所述的方法,其特征在于,在所述互连层之上、除所述金属焊垫对应的位置以外的区域形成所述散热层,包括:在所述互连层中距离有源器件最远的一层金属层上形成所述散热层;在所述散热层中与所述金属焊垫对应的位置开窗口。
- 如权利要求6所述的方法,其特征在于,所述集成电路管芯还包括钝化层,在所述互连层之上、除所述金属焊垫对应的位置以外的区域形成所述散热层,包括:在所述互连层中距离所述有源器件最远的一层金属层上形成钝化层;在所述钝化层中与所述金属焊垫对应的位置开窗口;在所述钝化层的表面上形成所述散热层;在所述散热层中与所述金属焊垫对应的位置开窗口。
- 如权利要求6所述的方法,其特征在于,所述集成电路管芯还包括钝化层,若包含所述集成电路管芯的集成电路芯片为引线键合芯片、且所述散热层形成于施行引线键合工艺之后,在所述互连层之上、除所述金属焊垫对应的位置以外的区域形成所述散热层,包括:在所述互连层中距离所述有源器件最远的一层金属层上形成钝化层;在所述钝化层中与所述金属焊垫对应的位置开窗口;在所述钝化层的表面上形成所述散热层。
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EP16785938.8A EP3282478A4 (en) | 2015-04-30 | 2016-04-28 | Integrated circuit die and manufacturing method therefor |
BR112017023286-3A BR112017023286A2 (zh) | 2015-04-30 | 2016-04-28 | An integrated circuit die and method of manufacture |
US15/797,549 US10607913B2 (en) | 2015-04-30 | 2017-10-30 | Integrated circuit die and manufacture method thereof |
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CN201510221081.2A CN104851860B (zh) | 2015-04-30 | 2015-04-30 | 一种集成电路管芯及制造方法 |
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EP (1) | EP3282478A4 (zh) |
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CN108281404A (zh) * | 2015-04-30 | 2018-07-13 | 华为技术有限公司 | 一种集成电路管芯及制造方法 |
CN107579050B (zh) * | 2016-07-05 | 2019-11-15 | 慧隆科技股份有限公司 | 晶片封装体的制造方法 |
CN112652573A (zh) * | 2020-12-07 | 2021-04-13 | 海光信息技术股份有限公司 | 一种封装方法及芯片 |
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EP3282478A4 (en) | 2018-05-02 |
CN104851860B (zh) | 2018-03-13 |
US10607913B2 (en) | 2020-03-31 |
EP3282478A1 (en) | 2018-02-14 |
BR112017023286A2 (zh) | 2018-09-04 |
US20180068922A1 (en) | 2018-03-08 |
CN108281404A (zh) | 2018-07-13 |
CN104851860A (zh) | 2015-08-19 |
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