TW201501249A - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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Publication number
TW201501249A
TW201501249A TW103107251A TW103107251A TW201501249A TW 201501249 A TW201501249 A TW 201501249A TW 103107251 A TW103107251 A TW 103107251A TW 103107251 A TW103107251 A TW 103107251A TW 201501249 A TW201501249 A TW 201501249A
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Taiwan
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conductive pattern
wiring
semiconductor device
substrate
semiconductor wafer
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TW103107251A
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TWI615925B (zh
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Atsushi Tomohiro
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Ps4 Luxco Sarl
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    • H—ELECTRICITY
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Manufacturing & Machinery (AREA)

Abstract

本發明係一種半導體裝置(1)，其中，具有配線基板(2)，和半導體晶片(3)，和封閉體(4)。配線基板(2)係具有絕緣基材(2a)，和加以形成於絕緣基材(2a)之一方的面之第1導通圖案(12)，和加以形成於絕緣基材(2a)之一方的面，而加以連接於第1導通圖案(12)，端面則露出於側方之第2導通圖案(13)。半導體晶片(3)係呈重疊於第1導通圖案(12)地加以搭載於配線基板(2a)上。封閉體(4)係呈被覆半導體晶片(3)地加以形成於配線基板(2a)。

Description

半導體裝置
本發明係有關具有半導體晶片的半導體裝置。
近年，具有記憶體晶片或邏輯晶片等之半導體晶片的半導體裝置之高速化進展，根據半導體晶片之稼動率變高等而半導體晶片則成為容易產生發熱。因此，有必要將熱釋放至半導體裝置之外部。但對於BGA(Ball Grid Array)型式之半導體裝置係多使用傳熱性缺乏之有機構件之故，而不易自半導體裝置之半導體晶片加以釋放熱至空氣中。
在記載於專利文獻1(日本特開2000-68403號公報)之半導體裝置中，由配線基板與封閉體所成而內藏半導體晶片之封裝則加以安裝於安裝基板。對於此半導體裝置之構成保持半導體晶片(半導體元件)之封裝的配線基板之與安裝基板的連接面(基板連接面)之中央範圍，係加以設置有複數之散熱用焊錫球(焊錫凸塊)。於專利文獻1所揭示之半導體裝置係具有從半導體晶片熱傳達至複數之 散熱用焊錫球之構成之故，而從半導體晶片產生的熱則傳達至藉由散熱用焊錫球而加以連接之安裝基板，從安裝基板加以釋放至半導體裝置之外部。
〔先前技術文獻〕 〔專利文獻〕
[專利文獻1]日本特開2000-68403號公報
但在揭示於專利文獻1之發明中，因必須另外設置散熱用焊錫球之故，而半導體裝置全體之製造成本則增加。
對於使用揭示於專利文獻1之封裝，構成重疊具有不同種類之半導體晶片之複數的封裝之PoP(Package on Package)情況加以說明。在PoP型半導體裝置中，對於層積於上方之封裝的中央範圍的正下方，係設置有位置於下方之封裝的半導體晶片之故，未存在有配置複數之散熱用焊錫球於層積於上方之封裝的連接面之中央範圍的空間。假設，對於設置間隙於上方之封裝與下方之封裝之間而配置散熱用焊錫球情況，係下方的封裝之半導體晶片與散熱用焊錫球則接觸，而散熱用焊錫球與安裝基板則未接觸。作為其結果，無法從半導體晶片產生的熱，藉由散熱用焊錫球而傳達至安裝基板而加以釋放至外部者，而有半導體裝置帶有熱的問題。
本發明之半導體裝置係具有配線基板，和半導體晶片，和封閉體。配線基板係具有絕緣基材，和加以形成於絕緣基材之一方的面之第1導通圖案，和加以形成於絕緣基材之一方的面，而加以連接於第1導通圖案，端面則露出於側方之第2導通圖案。半導體晶片係呈重疊於第1導通圖案地加以搭載於配線基板上。封閉體係呈被覆半導體晶片地加以形成於配線基板。
如根據本發明，於絕緣基材之一方的面，加以形成有第1導通圖案，和加以連接於第1導通圖案之第2導通圖案。呈從重疊於第1導通圖案而加以搭載之半導體晶片產生的熱係傳導至第1導通圖案。傳導至第1導通圖案的熱係傳導至第2導通圖案，而從露出於側方之第2導通圖案的端面加以釋放至半導體裝置之外部。因此，無須形成複數之散熱用焊錫球於半導體晶片之配線基板的中央範圍，而抑制了半導體裝置全體之製造成本。另外，因未形成有散熱用焊錫球故，對於PoP型半導體裝置，亦可適用本發明之半導體晶片。
另外，從半導體晶片產生的熱則由藉由第1導通圖案，從露出於側方之第2導通圖案的端面加以釋放至外部者，經由半導體晶片本身產生的熱而半導體裝置則變為不易帶熱，半導體裝置之信賴性則提升。
1‧‧‧半導體裝置
2‧‧‧配線基板
2a‧‧‧絕緣基材
3‧‧‧半導體晶片
4‧‧‧封閉體
5‧‧‧焊錫球
6‧‧‧連接墊片
7‧‧‧金屬銲點
9‧‧‧電極墊片
10‧‧‧導線
11‧‧‧開口部
12‧‧‧第1導通圖案
13‧‧‧第2導通圖案
16‧‧‧上段封裝
17‧‧‧下段封裝
19‧‧‧連接用金屬銲點
21‧‧‧配線
23‧‧‧母基板
24‧‧‧製品形成部
圖1係顯示本發明之第1實施形態之半導體裝置之平面圖。
圖2a係顯示第1實施形態之半導體裝置之底面圖。
圖2b係顯示第1實施形態之半導體裝置之側面圖。
圖3a係在圖1之A-A’剖面圖。
圖3b係在圖1之B-B’剖面圖。
圖4係顯示第1實施形態之PoP型之半導體裝置之剖面圖。
圖5a係顯示第1實施形態之半導體裝置之組裝工程之剖面圖。
圖5b係顯示第1實施形態之半導體裝置之組裝工程之剖面圖。
圖5c係顯示第1實施形態之半導體裝置之組裝工程之剖面圖。
圖5d係顯示第1實施形態之半導體裝置之組裝工程之剖面圖。
圖5e係顯示第1實施形態之半導體裝置之組裝工程之剖面圖。
圖5f係顯示第1實施形態之半導體裝置之組裝工程之剖面圖。
圖6係顯示本發明之第2實施形態之半導體裝置之平面圖。
圖7係在圖6之C-C’剖面圖。
圖8係顯示第2實施形態之半導體裝置之變形例的平面圖。
圖9係顯示本發明之第3實施形態之半導體裝置之平面圖。
圖10係顯示本發明之第4實施形態之半導體裝置之平面圖。
圖11係在圖10之D-D’剖面圖。
以下，對於本發明之實施形態，參照圖面加以說明。
(第1實施形態)
圖1係顯示本發明之第1實施形態之半導體裝置之平面圖，圖2a係顯示第1實施形態之半導體裝置之底面圖，圖2b係顯示第1實施形態之半導體裝置之側面圖。
如圖1與圖2b所示，半導體裝置1係具有：於一方的面加以形成有特定配線圖案(未圖示)與第1導通圖案12與第2導通圖案13之絕緣基材2a所成之配線基板2，和搭載於配線基板2之一方的面之中央範圍之半導體晶片3。更且，此半導體裝置1係具有呈被覆半導體晶片3地，加以形成於配線基板2之一方的面之封閉體4。在圖1中，部分除去封閉體4，而顯示內部構造。
配線基板2係由玻璃聚酯基板等之絕緣基材2a所 成，而於絕緣基材2a之一方的面與另一方的面加以形成特定之配線圖案(未圖示)，此等配線圖案係加以被覆於抗焊劑膜等之絕緣膜2b。一方的面之配線圖案係加以形成於未與第1導通圖案12及第2導通圖案13平面上重疊之位置，未與此等加以連接。如圖1與圖3a所示，絕緣膜2b係於與後述之連接墊片6及第2導通圖案13對向之位置具有開口部11。沿著加以搭載之半導體晶片3之對向的一對的邊，加以連接於形成在配線基板2之一方的面之配線圖案的複數之連接墊片6則從開口部11露出。從形成於配線基板2之另一方的面之絕緣膜2b的開口部11係露出有複數之金屬銲點7。此連接墊片6與金屬銲點7係由Cu等加以形成，藉由形成在配線基板2內部之配線加以電性連接。對於配線基板2之另一方的面上係如圖2a所示，與金屬銲點7各加以連接之複數之焊錫球5(金屬球)則於除了配線基板2之另一方的面之中央範圍的範圍，沿著配線基板2之各邊加以設置成二列。
半導體晶片3係例如，DRAM(Dynamic Random Access Memory)之記憶體晶片，如圖1所示，加以形成為長方形之板狀。對於半導體晶片3之一方的面上係沿著對向之一對的邊而加以設置有複數之電極墊片9。與半導體晶片3之前述一方的面相反側的面(連接面)係如圖3a所示，藉由接著構件8而加以連接於配線基板2之中央範圍。作為接著構件8，例如使用絕緣電糊或DAF(Die Attached Film)等。如圖1與圖3a所示，連接墊片 6與電極墊片9係作為鄰接，經由導電性之導線10而加以電性連接。
另外，如圖1與圖3b所示，平面上而視，具有較半導體晶片3尺寸大的形狀之第1導通圖案12則加以形成於配線基板2之絕緣基材2a之一方的面上。對於第1導通圖案12之正上方係加以形成有半導體晶片3。更且，第2導通圖案13則沿著平行於未形成有半導體晶片3之電極墊片9之一對的邊之配線基板2之對向的一對的邊，於側方呈至少露出有端面地加以形成於絕緣基材2a之一方的面。第2導通圖案13係從絕緣膜2b之開口部11露出，於第2導通圖案13之表面上加以形成有電鍍層15。第1導通圖案12與第2導通圖案13係經由複數之連接用配線14而加以連接。第1導通圖案12與第2導通圖案13與連接用配線14係由熱傳導率高的Cu等加以形成。第2導通圖案13係較配線圖案的寬度為大，例如，如圖2b所示，沿著配線基板2之側面略遍佈全長而延伸存在呈露出地加以構成。從第2導通圖案13之側面的露出面係加以分割成複數亦可，但呈加大自第2導通圖案13之側面的露出面積地，沿著側面連續使其延伸存在者為佳。
如此，經由加以連接有加以設置於半導體晶片3之正下方的第1導通圖案12與第2導通圖案13之時，半導體晶片3所產生的熱則成為容易藉由第1導通圖案12而傳導至第2導通圖案13。並且，由第2導通圖案13之端面則露出於側方者，成為容易從露出之第2導通圖案13之 端面，將熱釋放於半導體裝置1之外部。因此，半導體晶片3本身則不易帶熱，而半導體裝置1之信賴性則提升。更且，使第2導通圖案13，從絕緣膜2b之開口部11露出，亦對於第2導通圖案13上呈形成有電鍍層15地加以構成有半導體裝置1者，可將露出於側方之金屬的面積，作為僅電鍍層15的部分加以大者。
更且，因無須以追加而形成散熱用焊錫球等之故，可抑制半導體裝置1之製造成本者。
以下，使用圖5a~圖5f，說明本發明之第1實施形態之半導體裝置1之製造工程。
首先，如圖5a所示，準備具有排列成矩陣狀之複數的製品形成部24(切斷後成為配線基板2的部分)之母基板23。對於母基板23之製品形成部24之一方的面係加以形成有複數之連接墊片6與第1導通圖案12與第2導通圖案13(參照圖1)，而對於製品形成部24之另一方的面係加以形成有複數之金屬銲點7。對於母基板23的兩面係加以設置有絕緣膜2b，從絕緣膜2b之開口部11露出有連接墊片6與第1導通圖案12與第2導通圖案13與金屬銲點7。
接著，如圖5b所示，在製品形成部24之一方的面之中央範圍，絕緣電糊或DAF等之接著構件8則加以塗佈於絕緣膜2b上。接著，於加以塗佈之接著構件8上，半導體晶片3之連接面與配線基板2之一方的面則呈對向地，加以搭載有半導體晶片3。此半導體晶片3係具有形 成有DRAM之記憶體電路等於一方的面之Si基板，對於此Si基板係加以設置有複數之電極墊片9。對於半導體晶片3之一方的面之除了電極墊片9的部分係加以形成有為了保護電路之保護膜(未圖示)。
在於各製品形成部24各加以搭載半導體晶片3之後，加以進行打線接合。如圖5c所示，所搭載之半導體晶片3的電極墊片9與母基板23之連接墊片6則經由導電性之導線10而加以連接。此導線10係例如，由Au或Cu等所成。另外，對於打線接合係使用不圖示之打線接合裝置。具體而言，加以熔融而形成為球狀之導線10之一端則加以超音波熱壓著於半導體晶片3之電極墊片9之後，導線10之另一端則加以超音波熱壓著於母基板23之連接墊片6。導線10係為了迴避與半導體晶片3之端部的邊緣之接觸而呈描繪特定之環形狀地加以形成。
接著，如圖5d所示地，呈一次地被覆複數之製品形成部24地，於母基板23之一方的面上加以形成有封閉體4。具體而言，使用具有由上模具與下模具所成之成行金屬模具(未圖示)之傳遞成形裝置等之成形裝置，加以形成封閉體4。對於上模具係形成有一次被覆複數之製品形成部24尺寸之模孔，而對於下模具係形成有為了配置母基板23之凹部。形成有導線10之母基板23則加以設置於下模具之凹部，由上模具與下模具而夾鉗母基板23之周緣部，於母基板23之上方加以配置前述之模孔。之後，使環氧樹脂等之熱硬化性的封閉樹脂充填於模孔內， 以特定溫度(例如，180℃)使其熱硬化。經由此，封閉樹脂則硬化，封閉體4則加以形成於母基板23之一方的面上。
在加以形成封閉體4於母基板23之一方的面上之後，進行形成焊錫球5於母基板23之另一方的面之球架工程。具體而言，如圖5e所示，於加以配置於母基板23之另一方的面之各製品形成部24之複數的金屬銲點7上，加以接合導電性之焊錫球5。複數之焊錫球5係經由配合金屬銲點7之配置而加以形成有複數之吸附孔的未圖示之球架而加以吸附保持，再藉由助熔劑而一次接合於金屬銲點7。
最後，經由未圖示之切割裝置，由切斷、分離製品形成部24彼此之間者，如圖5f所示，形成半導體裝置1。
圖4係顯示具有將在上所說明之構成的半導體裝置作為上段封裝16，而上段封裝16則加以層積於具有半導體晶片3之下段封裝17之構成的PoP型之半導體裝置之剖面圖。
下段封裝17係具有加以形成有特定之配線圖案(未圖示)於一方的面之配線基板2，和藉由下填充材20而加以搭載於配線基板2之一方的面之中央範圍之半導體晶片3。下段封裝17之半導體晶片3的形成範圍25係模式性地顯示於圖2a。對於配線基板2之兩面係加以被覆有絕緣膜2b，而對於絕緣膜2b係加以設置有開口部。對於配線基板2之一方的面係與上段封裝16之焊錫球5連接 之連接用金屬銲點19，和與半導體晶片3連接之連接墊片6則從開口部露出。對於配線基板2之另一方的面係與焊錫球5連接之複數的金屬銲點7則從開口部露出。
加以連接有上段封裝16之配線基板2的另一方的面之焊錫球5，和下段封裝17之配線基板2的另一方的面之連接用金屬銲點19，加以形成有具有不同之二個半導體晶片3之PoP型之半導體裝置1。此時，因於上段封裝16之配線基板2的另一方的面之中央範圍未加以設置有焊錫球5之故，搭載於下段封裝17之半導體晶片3與上段封裝16之配線基板2的另一方的面之焊錫球5則未接觸。即，上段封裝16之配線基板2的另一面之焊錫球5係未接觸於下段封裝17之半導體晶片3，而與下段封裝17之配線基板2接觸。
如以上，將半導體晶片3的熱，藉由第1導通圖案12及第2導通圖案13而從側方釋放於半導體裝置1之外部之故，無須於配線基板2之另一面之中央範圍設置散熱用之焊錫球，而將熱釋放至安裝基板。經由於層積上段封裝16與下段封裝17而加以形成之PoP型之半導體裝置1之上段封裝16，適用具有第1導通圖案12與加以連接於此之同時，露出於側方之第2導通圖案13之構成之時，上段封裝16之半導體晶片3的熱則容易從露出於側方之第2導通圖案13的端面加以釋放至半導體裝置1之外部，PoP型之半導體裝置1之信賴性則提升。
在本實施形態中，第1導通圖案12與第2導通圖案 13與連接墊片6則加以形成於夾持於絕緣基材2a與絕緣膜2b之相同的層。但連接墊片6與各導通圖案則加以形成於另外的層亦可。另外，各導通圖案與連接墊片6則自不同之材料加以形成亦可。
(第2實施形態)
圖6係顯示本發明之第2實施形態之半導體裝置之平面圖，圖7係在圖6之C-C’剖面圖。
在本實施形態之半導體裝置1係加以於第1實施形態之構成，第1導通圖案12，和與電源或GND連接之連接墊片6則藉由配線21而加以電性連接之構成。
圖8係顯示本發明之第2實施形態之半導體裝置之變形例的平面圖。
在本變形例之半導體裝置1中，第1導通圖案12則加以分為加以連接於連接於電源之連接墊片6之第1導通圖案(電源)12a，和加以連接於連接於GND之連接墊片6的第1導通圖案(GND)12b。同樣地，第2導通圖案13則加以分為加以連接於第1導通圖案(電源)12a之第2導通圖案(電源)13a，和加以連接於第1導通圖案(GND)12b之第2導通圖案(GND)13b。第1導通圖案(電源)12a第2導通圖案(電源)13a係經由連接用配線(電源)14a而加以連接。第1導通圖案(GND)12b和第2導通圖案(GND)13b係經由連接用配線(GND)14b而加以連接。
本實施形態及變形例之半導體裝置1之其他的構成或 製造工程係與第1實施形態同樣之故而省略之。
如此，第1導通圖案12則經由藉由連接於電源或GND之連接墊片6與配線21加以電性連接之時，第1導通圖案12及第2導通圖案13則作為配線基板2之配線圖案的一部分而加以利用。因此，與配線基板2之配線圖案同時，由形成第1導通圖案12及第2導通圖案13者，簡略化製造工程。作為其結果，可抑制半導體裝置1之製造成本。加上可得到與第1實施形態同樣的效果。
(第3實施形態)
圖9係顯示本發明之第3實施形態之半導體裝置之平面圖。
本實施形態之半導體裝置1係具有以平面而視表面積大之連接用導通圖案22而形成連結第1導通圖案12與第2導通圖案13之連接用的配線之構成。此連接用導通圖案22係與第1導通圖案12及第2導通圖案13同樣地，由Cu等加以形成。
本實施形態之半導體裝置1之其他的構成或製造工程係與第1實施形態同樣之故而省略之。
如此，由設置有連接用導通圖案22之時，連結第1導通圖案12與第2導通圖案13之間的範圍則增加，而從第1導通圖案12傳導至第2導通圖案13的熱則增加。因此，半導體晶片3所產生的熱則容易藉由第1導通圖案12與連接用導通圖案22與第2導通圖案13，從露出於側 方之第2導通圖案13的端面加以釋放熱至半導體裝置1之外部。作為其結果，半導體晶片3本身則不易帶熱，而半導體裝置1之信賴性則提升。加上可得到與第1實施形態同樣的效果。
(第4實施形態)
圖10係顯示本發明之第4實施形態之半導體裝置之平面圖，圖11係在圖10之D-D’剖面圖。
本實施形態之半導體裝置1係具有配線基板2，和搭載於配線基板2之一方的面之中央範圍之半導體晶片3，和加以形成於配線基板2之一方的面上之封閉體4。在圖10中，部分除去封閉體4，而顯示內部構造。
配線基板2之兩面係除了開口部11而加以被覆於絕緣膜2b。對於配線基板2之一方的面之開口部11內係沿著所搭載之半導體晶片3之各邊而露出有複數之連接墊片6。對於配線基板2之另一方的面之開口部11內係露出有複數之金屬銲點7。對於配線基板2之另一方的面上係與金屬銲點7各加以連接之複數之焊錫球5則於除了配線基板2之另一方的面之中央範圍的範圍，沿著配線基板2之各邊加以設置成二列。
半導體晶片3係加以形成為長方形之板狀，對於半導體晶片3之一方的面上係沿著半導體晶片3之各邊而加以設置有複數之電極墊片9。配線基板2之連接墊片6與半導體晶片3之電極墊片9係經由導電性之導線10而加以 電性連接。
另外，第1導通圖案12則加以形成於配線基板2之絕緣基材2a之一方的面與絕緣膜2b之間。對於第1導通圖案12之正上方係加以形成有半導體晶片3。第2導通圖案13之端面則在配線基板2之四個角部，呈於側方至少露出有一部分地，加以形成於絕緣基材2a之一方的面。第2導通圖案13係露出於絕緣膜2b之開口部11內，於第2導通圖案13之表面上加以形成有電鍍層15。第1導通圖案12與第2導通圖案13係經由複數之連接用配線14而加以連接。
本實施形態之半導體裝置1之製造工程係與第1實施形態同樣之故而省略之。
如此，經由第2導通圖案13加以設置於配線基板2之四個角部之時，可沿著半導體晶片3之各邊而形成連接墊片6與電極墊片9者，於半導體晶片3加以設置有多數電極墊片9。加上可得到與第1實施形態同樣的效果。
以上，對於本發明之半導體裝置之具體的構成，依據各實施形態而說明過，但本發明係不限定於前述之實施形態者，在不脫離本發明之內容的範圍，當然可對於前述實施形態而言做種種變更。例如，在前述之各實施形態中，對於於一個配線基板2上搭載一個半導體晶片3之半導體裝置1加以說明過，但亦可適用本發明於搭載有平面性排列加以配置之複數之半導體晶片3於一個配線基板2上的半導體裝置1。或者，亦可適用本發明於搭載有所層積之 複數之半導體晶片3(MCP：Multi Chip Package)於一個配線基板2上的半導體裝置1。
另外，在本實施形態中，對於適用於搭載DRAM之半導體晶片之半導體裝置的情況加以說明過，但亦可適用本發明於搭載邏輯晶片或快閃記憶體等，DRAM以外之半導體晶片之半導體裝置。
1‧‧‧半導體裝置
2‧‧‧配線基板
3‧‧‧半導體晶片
4‧‧‧封閉體
6‧‧‧連接墊片
9‧‧‧電極墊片
10‧‧‧導線
11‧‧‧開口部
12‧‧‧第1導通圖案
13‧‧‧第2導通圖案
14‧‧‧連接用配線

Claims (8)

  1. 一種半導體裝置，其特徵為具有：具有絕緣基材，和加以形成於前述絕緣基材之一方的面之第1導通圖案，及加以形成於前述絕緣基材之前述一方的面，而加以連接於前述第1導通圖案，端面則露出於側方之第2導通圖案之配線基板，和呈重疊於前述第1導通圖案地加以搭載於前述配線基板上之半導體晶片，和呈被覆前述半導體晶片地加以形成於前述配線基板之封閉體者。
  2. 如申請專利範圍第1項記載之半導體裝置，其中，前述配線基板係具有呈被覆前述第1導通圖案，而使前述第2導通圖案露出地，形成於前述絕緣基材之前述一方的面之絕緣膜者。
  3. 如申請專利範圍第1項或第2項記載之半導體裝置，其中，對於前述第2導通圖案的表面係設置有電鍍層者。
  4. 如申請專利範圍第1項至第3項記載之任一項記載之半導體裝置，其中，前述第1導通圖案與前述第2導通圖案則經由連接用配線加以連接者。
  5. 如申請專利範圍第1項至第4項記載之任一項記載之半導體裝置，其中，前述配線基板係具有連接墊片，前述絕緣膜係於與前述連接墊片對向之位置具有開口部，前述第1導通圖案係加以連接於前述連接墊片者。
  6. 一種半導體裝置，其特徵為具有：具有絕緣基材，和加以形成於前述絕緣基材之一方的面之配線圖案及連接墊片之配線基板，和呈重疊於前述配線圖案地加以搭載於前述配線基板上之半導體晶片，和呈被覆前述半導體晶片地加以形成於前述配線基板之前述一方的面之封閉體，前述配線圖案之一部分則構成加以連接於前述連接墊片之第1導通圖案，和加以連接於前述第1導通圖案之端面則露出於側方之第2導通圖案者。
  7. 一種半導體裝置，其特徵為具有：具有絕緣基材，加以形成於前述絕緣基材之一方的面之第1導通圖案，及加以連接於前述第1導通圖案，加以形成於前述絕緣基材之前述一方的面，而端面則露出於側方之第2導通圖案之配線基板，和呈重疊於前述第1導通圖案地加以搭載於前述配線基板上之半導體晶片，和呈被覆前述半導體晶片地加以形成前述配線基板之封閉體，和對於前述配線基板之另一方的面，於除了前述配線基板之中央範圍的範圍，沿著前述配線基板之各邊加以設置之金屬球的上段封裝，和具有由絕緣基材所成之配線基板，加以搭載於前述配線基板之一方的面之半導體晶片，及加以搭載於前述配線基板之另一方的面之金屬球的下段封裝，前述上段封裝之前述金屬球則未與前述下段封裝之前 述半導體晶片接觸，而呈與前述下段封裝之前述配線基板接觸地，層積有前述上段封裝與前述下段封裝者。
  8. 如申請專利範圍第7項記載之半導體裝置，其中，於前述下段封裝之前述配線基板之前述一方的面加以設置有連接用金屬銲點，加以連接有前述上段封裝之前述金屬球與前述下段封裝之前述連接用金屬銲點者。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107683018A (zh) * 2016-08-02 2018-02-09 矽品精密工业股份有限公司 电子装置

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6327114B2 (ja) * 2014-10-30 2018-05-23 三菱電機株式会社 電子部品搭載基板、電動機、空気調和機、及び電子部品搭載基板の製造方法
JP6560496B2 (ja) * 2015-01-26 2019-08-14 株式会社ジェイデバイス 半導体装置
JP6771308B2 (ja) * 2016-05-02 2020-10-21 三菱電機株式会社 回路基板および半導体集積回路の実装構造

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3052899B2 (ja) * 1997-07-04 2000-06-19 日本電気株式会社 半導体装置
JP2000031343A (ja) * 1998-07-09 2000-01-28 Texas Instr Japan Ltd 半導体装置
TW484344B (en) 1998-10-26 2002-04-21 Taiyo Yuden Kk Hybrid module
TW391566U (en) 1998-12-18 2000-05-21 Phoenix Prec Technology Corp Hear dissipation substrate structure of semiconductor component
JP2001345399A (ja) 2000-05-31 2001-12-14 Fujitsu Ltd 半導体装置及びその製造方法
JP4662324B2 (ja) 2002-11-18 2011-03-30 太陽誘電株式会社 回路モジュール
JP4020874B2 (ja) * 2003-03-13 2007-12-12 三洋電機株式会社 半導体装置およびその製造方法
US7187060B2 (en) 2003-03-13 2007-03-06 Sanyo Electric Co., Ltd. Semiconductor device with shield
JP4360858B2 (ja) * 2003-07-29 2009-11-11 シチズン電子株式会社 表面実装型ｌｅｄ及びそれを用いた発光装置
US7786591B2 (en) 2004-09-29 2010-08-31 Broadcom Corporation Die down ball grid array package
TWI281698B (en) * 2005-07-25 2007-05-21 Advanced Semiconductor Eng Chip package
JP4781097B2 (ja) * 2005-12-05 2011-09-28 ルネサスエレクトロニクス株式会社 テープキャリアパッケージ及びそれを搭載した表示装置
KR100653249B1 (ko) * 2005-12-07 2006-12-04 삼성전기주식회사 메탈코어, 패키지 기판 및 그 제작방법
JP2008010602A (ja) 2006-06-29 2008-01-17 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
JP5135828B2 (ja) * 2007-02-28 2013-02-06 ソニー株式会社 基板およびその製造方法、半導体パッケージおよびその製造方法、並びに半導体装置およびその製造方法
US7745910B1 (en) * 2007-07-10 2010-06-29 Amkor Technology, Inc. Semiconductor device having RF shielding and method therefor
JP4344766B2 (ja) * 2007-11-30 2009-10-14 シャープ株式会社 ソースドライバ、ソースドライバの製造方法、および液晶モジュール
TW200945527A (en) 2008-04-21 2009-11-01 Phoenix Prec Technology Corp Package structure
US7906371B2 (en) * 2008-05-28 2011-03-15 Stats Chippac, Ltd. Semiconductor device and method of forming holes in substrate to interconnect top shield and ground shield
CN101600292B (zh) * 2008-06-02 2012-06-20 鸿富锦精密工业（深圳）有限公司 电路板
TW201246490A (en) 2008-07-11 2012-11-16 Unimicron Technology Corp Package substrate
JP5359642B2 (ja) 2009-07-22 2013-12-04 東京エレクトロン株式会社 成膜方法
KR101601622B1 (ko) * 2009-10-13 2016-03-09 삼성전자주식회사 발광다이오드 소자, 발광 장치 및 발광다이오드 소자의 제조방법
JP2012182395A (ja) 2011-03-02 2012-09-20 Taiyo Yuden Co Ltd 電子デバイス
US8889995B2 (en) * 2011-03-03 2014-11-18 Skyworks Solutions, Inc. Wire bond pad system and method
US9412703B1 (en) * 2015-02-17 2016-08-09 Powertech Technology Inc. Chip package structure having a shielded molding compound

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107683018A (zh) * 2016-08-02 2018-02-09 矽品精密工业股份有限公司 电子装置

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US20160029491A1 (en) 2016-01-28
KR20150125988A (ko) 2015-11-10
TWI615925B (zh) 2018-02-21
US10517176B2 (en) 2019-12-24
TWI654722B (zh) 2019-03-21
TW201813013A (zh) 2018-04-01
WO2014136735A1 (ja) 2014-09-12
DE112014001116T5 (de) 2015-12-24
US20180139847A1 (en) 2018-05-17

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