201246490 六、發明說明： 【發明所屬之技術領域】 • 树明係有關於—種半導體封裝基板，尤指-種具有 - 開口之封裝基板。 【先前技術】 目刖業界為滿足半導體封裝件高積集度（Integrati〇n) 及Μ型化(Miniaturization)的封裝需求，且為求提昇單一半 導體封裝件之性能（ability)與容量（capacity)以符合電子產 品小型化、大容量與高速化之趨勢，係發展出半導體晶片 之堆疊技術。 請參閱第1A圖，一般具有堆疊技術之半導體封裝件 係將一第一半導體晶片11以覆晶式(Flip 電性連接於 一基板10之一表面10a，且於該基板10之另一表面1〇b 設置供外接其他電子裝置之焊料球12,並於該第一半導體 晶片11上接置至少一第二半導體晶片13，且該第二半導 體晶片13以打線式(Wire bonding)，即藉由導線14電性連 接至該基板10，並於該基板10上形成包覆該第一及第二 半導體晶片11，13之封裝材15。 然，因該第一及第二半導體晶片11，13均電性連接同 一基板10，若其中一半導體晶片故障，將導致半導體封裝 件整體失效，而浪費成本。 請參閱第1B圖，為解決上述之問題，遂發展堆疊封 裝（Package on Package，POP)技術，以提供另一種半導 體封裝件，係包括至少二封裝件16 ’各該封裝件16之間 110858D01 3 201246490 藉由導電元件丨7電性堆疊；其中，該封裝件16具有一基 板160、設於該基板160上並以打線式電性連接至該基板 160之半導體晶片161、以及覆設於部份之基板16〇上且覆 蓋該半導體晶片161之封裝材162,且該導電元件17設於 該基板160上，另外，於最下層之基板160之相對堆疊之 一側設有供外接其他電子裝置之焊料球163。 惟，各該封裝件16的高度係為該基板16〇及封裝材 162的愚度總和，俾使堆疊封裝（pop)之半導體封裝件高产 過高，不易製成輕薄短小之裝置，因而使電子產品的應用 受限。 因此，如何解決上述習知、半導體封裝件的問題，實為 目前亟欲解決的課題。 【發明内容】 鑑於上述習知技術之種種缺失，本發明之一目的在於 提供一種能降低封裝高度之封裝基板。 、 本發明之另一目的在於提供一種具散熱功能之封裝 基板。 、 為達上述及其它目的，本發明提供一種封農基板，係 包括.核心板，係具有相對之第-表面及第二表面，於該 第-表面及第二表面分別具有介電層，且該第—表面之介 有複數打線塾，於該第二表面之介電層上具有複 數植球墊，且具有貫穿該介電層、第一表面及第二表面之 開口，金屬板，係設於該核心板之第二表面之介電層上， 並對應該.，該金屬板之厚度係大於該植球塾之厚度， 110858D01 4 201246490 以供承載之用。 依上述之封裝基板，該核心板係為兩層或多層線路 板；該金屬板係為銅，且該開口中之金屬板係為該介電層 所覆蓋。 依上述之結構，復包括防焊層，係分別設於該核心板 之第一表面及第二表面的介電層上，該第一表面之防焊層 具有對應該開口之防焊層開口，且該些防焊層具有複數開 孔’以對應露出各該打線墊、金屬板及植球墊，於該防焊 層開口中之打線墊上設有表面處理層，該表面處理層係為 化鎳/金(Ni/Au)、電鍍鎳/金(Ni/Au)、化鎳鈀浸金(ENEPIG) 或化鎳自催化金(ENAG)。 本發明再提供一種封裝基板’係包括：核心板，係具 有相對之第一表面及第二表面，於該第一表面及第二表面 分別具有介電層，且該第一表面之介電層中具有複數打線 墊，該打線墊並與該介電層表面齊平，於該第二表面之介 電層上具有複數植㈣，該植球塾並與該介電層表面齊 平’且具有貫穿該介電層、第—表面及第二表面之開口； 金屬板，係設於該核心板之第二表而以人 φ^ ^ 衣面的介電層中並與該介 電層表面齊平，且對應該開口，拎 A '^金屬板之厚度係大於該 植球墊之厚度，以供承载之用。 依^上迷之封裝暴板’該核心柄、 板；該金屬板係為銅，該D中Μ兩層或多層線 所覆蓋。 之金屬板係為該介電 依上述之結構，復包括防焊層 ’係設於該核心板之第 U0858D01 ς 201246490 -表面及第二表面的介電層上，該防焊層具有對應該開口 之防焊層開口，且該些防焊層具有複數開孔，以對應露出 各該打線墊、金屬板及植球墊，於該防焊層開口中之打線 墊上设有表面處理層，該表面處理層係為化鎳/金 (Ni/Au)、電鍍鎳/金(Ni/Au)、化鎳鈀浸金(ENEpiG)或化鎳 自催化金(ENAG)。 本發明之封裝基板具有開口，並藉由半導體晶片置入 開口中，以降低整體之封裝高度；另外，該金屬板之厚度 係大於該植球墊之厚度，使該半導體晶片穩固設於金屬板 上，且利用金屬材質導熱性佳之特性，俾使半導體晶片藉 由金屬板散熱，以達到具散熱功能之目的。 【實施方式】 以下藉由特定的具體實施例說明本發明之實施方 式，熟悉此技藝之人士可由本說明書所揭示之内容輕易地 瞭解本發明之其他優點及功效。 請參閱第2A至2C圖，係為本發明之封農基板之剖面 示意圖。 如第2A圖所示，本發明之封裝基板係包括有核心板 20及金屬板21，該核心板20係為兩層或多層線路板並具 有相對之第一表面20a及第二表面20b’於該第一表面2〇a 上設有複數打線墊201，該打線墊201係設於該第一表面 20a中並與該第一表面20a齊平，又於該第二表面2〇b上 设有複數植球塾202’該植球墊202係設於該第二表面2〇b 中並與該第二表面20b齊平，且具有貫穿該第一表面2〇a 110858D01 6 201246490 及第二表面20b之開口 200;於該核心板20之第二表面20b 設有係為銅（Cu)之金屬板21，並與該第二表面20b齊平 以封住該開口 200之一端，使該金屬板21顯露在該開口 200中，且該金屬板21之厚度大於該植球墊202之厚度， 以供承載之用。 又於該第一及第二表面20a，20b上設有防烊層22，而 該防焊層22並具有對應該開口 200之防焊層開口 220,且 該防焊層22具有複數開孔221，以對應露出各該打線墊 201、金屬板21及植球墊202。 另於該打線墊201上設有表面處理層201a，該表面處 理層201a係為化鎳/金(Ni/Au，係先形成鎳，之後再形成 金）、電锻鎳/金（Ni/Au)、化鎳把浸金（Electroless Nickel/Electroless Palladium/Immersion Gold，ENEPIG)或化鎳 自催化金(Electroless Nickel Autocatlytic Gold, ΕΝ AG)。 如第2B圖所示’該核心板20係為兩層或多層線路 板，且於該核心板20之第一表面20a及第二表面20b分別 具有介電層204之實施結構，該打線墊201係設於該第一 表面20a之介電層204上，而該植球墊202及金屬板21 係設於該第二表面20b之介電層204上，又該金屬板21 係對應於封裝基板開口 200，並為該介電層204所覆蓋， 且於該第一表面20a及第二表面20b的介電層204上分別 設有防焊層22 ’而該第一表面2〇a之防焊層22並具有對 應該開口 200之防焊層開口 220,該防焊層22並具有複數 開孔221 ’以對應露出各該打線塾201、金屬板21及植球 110858D01 7 201246490 墊202，且該金屬板21之厚度大於該植球墊202之厚度， 以供承載之用。 如第2C圖所示，該核心板2〇係為兩層或多層線路 板’於該核心板20之第一表面20a及第二表面20b分別具 有介電層204之另一實施結構，該打線墊2〇1係設於該第 一表面20a之介電層204中，並與該第一表面20a之介電 層204表面齊平’而該植球墊202及金屬板21係設於該第 一表面20b之介電層204中，且與該第二表面20b之介電 層204表面齊平，又該金屬板21係對應於封裝基板開口 200 ’並為該介電層204所覆蓋，且該金屬板21之厚度大 於該植球塾202之厚度，以供承載之用。 請參閱第3圖，提供一係如第2A圖所示之封裝基板， 於該核心板20之開口 2〇〇中的金屬板21上接置一半導體 晶片23 ’該半導體晶片23具有相對之作用面23a及非作 用面23b ’於該作用面23a上具有複數電極墊231，且該半 導體晶片23以該非作用面23b藉由黏著層24固定於該開 口 200中之金屬板21上，並藉由導線25電性連接至該核 〜板20之打線墊201 ;因該金屬板21之厚度s大於該植 球塾202之厚度h，使該半導體晶片23得以穩固設置於該 金屬板21上’且藉由該金屬板21導熱性佳的特性，俾使 該半導體晶片23藉由該金屬板21以達散熱之作用；並於 該核心板20之第一表面20a上的部份防焊層22上形成有 封襄材26 ’且該封裝材26並填充於該開口 200中，以包 覆該半導體晶片23、導線25及打線墊201 ;又於該核心板 110858D01 201246490 20之第二表面2〇b側的防焊層22，於該防焊層22之開孔 221中的金屬板21及植球墊202上接置焊料球27,27,，以 - 構成一封裝件，其中接置於該金屬板21上的焊料球27，係 • 供散熱用，而接置於該植球墊202上之焊料球27係供外接 其他電子裝置，例如印刷電路板，該封裝件亦可外接另一 封裝件’以構成堆疊封裝（POP)結構。 本發明之封裝基板具有開口，並藉由將半導體晶片容 置於該開口中，以降低整體之封裝高度；另外，該金屬板 之厚度係大於該植球墊之厚度，使該半導體晶片穩固設於 金屬板上，且利用金屬材質導熱性佳之特性，俾使半導體 晶片藉由金屬板散熱’以達到具散熱功能之目的。 综上所述，本發明藉由半導體晶片置入核心板之開口 中，使主要結構高度僅為核心板的高度，而不 達到降低高度之目的;另外，藉由係: 穩，且達到具散熱功能之目的。 載 上述實施例係用以例示性說 效，而非用於限制本發日月 之原理及其功 在不違背本發明之精神及纟 " 二叮 故。田Η媒帕 ㈣下’對上述實施例進行修 發月之權利保護範圍 圍所列。 應如纽之申請專利範 【圖式簡單説明】 第1Α及1Β圖係為習知 ^ 2Α $ 2Γ m. ^ +導體封裝件之剖面示意圖；201246490 VI. Description of the Invention: [Technical Fields of the Invention] • Shuming is a type of semiconductor package substrate, in particular, a package substrate having an opening. [Prior Art] The industry has met the requirements for high-integration (Integrati) and Minaturization of semiconductor packages, and to improve the performance and capacity of a single semiconductor package. In order to meet the trend of miniaturization, large capacity and high speed of electronic products, the stacking technology of semiconductor wafers has been developed. Referring to FIG. 1A, a semiconductor package having a stacking technique generally has a first semiconductor wafer 11 in a flip chip form (Flip is electrically connected to one surface 10a of a substrate 10, and the other surface 1 of the substrate 10 is焊料b is provided with a solder ball 12 for externally connecting other electronic devices, and at least one second semiconductor wafer 13 is attached to the first semiconductor wafer 11, and the second semiconductor wafer 13 is wire-bonded, that is, by wire bonding The lead wire 14 is electrically connected to the substrate 10, and the package material 15 covering the first and second semiconductor wafers 11, 13 is formed on the substrate 10. However, since the first and second semiconductor wafers 11, 13 are Electrically connecting the same substrate 10, if one of the semiconductor wafers fails, the semiconductor package will be completely ineffective and costly. Please refer to Figure 1B to solve the above problems and develop a package on package (POP) technology. To provide another semiconductor package, comprising at least two packages 16' each of the packages 16 between 110858D01 3 201246490 electrically stacked by a conductive element ;7; wherein the package 16 has a base a semiconductor wafer 161 disposed on the substrate 160 and electrically connected to the substrate 160, and a package 162 overlying the portion of the substrate 16 and covering the semiconductor wafer 161, and the conductive member 17 is disposed on the substrate 160. Further, one side of the opposite stack of the lowermost substrate 160 is provided with solder balls 163 for externally connecting other electronic devices. However, the height of each of the packages 16 is the substrate 16 and The sum of the maturity of the package material 162 makes the semiconductor package of the stacked package high and the output is too high, and it is not easy to be made into a thin and light device, thereby limiting the application of the electronic product. Therefore, how to solve the above conventional semiconductor package SUMMARY OF THE INVENTION In view of the above-described deficiencies of the prior art, it is an object of the present invention to provide a package substrate capable of reducing the package height. Another object of the present invention is to provide a package substrate. Providing a package substrate having a heat dissipation function. In order to achieve the above and other objects, the present invention provides an agricultural substrate, which comprises a core plate, which has a relative The surface and the second surface respectively have a dielectric layer on the first surface and the second surface, and the first surface is provided with a plurality of wire bonds, and the plurality of ball pads are disposed on the dielectric layer of the second surface. And having an opening extending through the dielectric layer, the first surface and the second surface, the metal plate is disposed on the dielectric layer of the second surface of the core plate, and the thickness of the metal plate is greater than the The thickness of the bulb, 110858D01 4 201246490 for carrying. According to the above package substrate, the core plate is a two-layer or multi-layer circuit board; the metal plate is copper, and the metal plate in the opening is Covered by a dielectric layer. According to the above structure, the solder resist layer is respectively disposed on the dielectric layer of the first surface and the second surface of the core board, and the solder resist layer of the first surface has a solder mask opening corresponding to the opening. And the solder mask has a plurality of openings to correspondingly expose the wire pads, the metal plate and the ball pad, and a surface treatment layer is disposed on the wire pad in the opening of the solder resist layer, and the surface treatment layer is nickel / Gold (Ni / Au), electroplated nickel / gold (Ni / Au), nickel palladium immersion gold (ENEPIG) or nickel autocatalytic gold (ENAG). The present invention further provides a package substrate comprising: a core plate having opposite first and second surfaces, respectively having a dielectric layer on the first surface and the second surface, and a dielectric layer on the first surface Having a plurality of wire mats, the wire mats being flush with the surface of the dielectric layer, having a plurality of implants on the dielectric layer of the second surface, the ball bumps being flush with the surface of the dielectric layer and having An opening extending through the dielectric layer, the first surface, and the second surface; the metal plate is disposed in the second surface of the core plate and is in the dielectric layer of the human surface and is flush with the surface of the dielectric layer Flat, and corresponding to the opening, 拎A '^ metal plate thickness is greater than the thickness of the ball pad for bearing. According to the above-mentioned package, the core handle and the plate; the metal plate is made of copper, and the D is covered by two or more layers of wires. The metal plate is the dielectric according to the above structure, and the solder resist layer is disposed on the dielectric layer of the surface and the second surface of the U0858D01 ς 201246490 of the core plate, and the solder resist layer has an opening corresponding thereto. The solder resist layer has openings, and the solder resist layers have a plurality of openings to correspondingly expose the wire bonding pads, the metal plate and the ball pad, and a surface treatment layer is disposed on the wire bonding pad in the opening of the solder resist layer, the surface The treatment layer is nickel/gold (Ni/Au), electroplated nickel/gold (Ni/Au), nickel-palladium immersion gold (ENEpiG) or nickel self-catalyzing gold (ENAG). The package substrate of the present invention has an opening and is placed in the opening by the semiconductor wafer to reduce the overall package height; in addition, the thickness of the metal plate is greater than the thickness of the ball pad, so that the semiconductor wafer is stably disposed on the metal plate. On the other hand, and utilizing the characteristics of good thermal conductivity of the metal material, the semiconductor wafer is dissipated by the metal plate to achieve the purpose of heat dissipation. [Embodiment] The embodiments of the present invention are described below by way of specific embodiments, and those skilled in the art can readily understand the other advantages and functions of the present invention from the disclosure. Please refer to Figures 2A to 2C for a cross-sectional view of the agricultural substrate of the present invention. As shown in FIG. 2A, the package substrate of the present invention includes a core board 20 and a metal board 21, and the core board 20 is a two-layer or multi-layer circuit board and has a first surface 20a and a second surface 20b' opposite to each other. The first surface 2A is provided with a plurality of wire mats 201, and the wire mats 201 are disposed in the first surface 20a and are flush with the first surface 20a, and are further disposed on the second surface 2b a plurality of ball bumps 202' disposed in the second surface 2〇b and flush with the second surface 20b, and having a first surface 2〇a 110858D01 6 201246490 and a second surface 20b The opening 200; the second surface 20b of the core plate 20 is provided with a metal plate 21 of copper (Cu), and is flush with the second surface 20b to seal one end of the opening 200, so that the metal plate 21 It is exposed in the opening 200, and the thickness of the metal plate 21 is greater than the thickness of the ball pad 202 for carrying. Further, the first and second surfaces 20a, 20b are provided with a tamper-proof layer 22, and the solder resist layer 22 has a solder resist layer opening 220 corresponding to the opening 200, and the solder resist layer 22 has a plurality of openings 221 In order to expose each of the wire pad 201, the metal plate 21 and the ball pad 202. Further, the wire bonding pad 201 is provided with a surface treatment layer 201a which is made of nickel/gold (Ni/Au, which is formed by first forming nickel, then gold is formed), and electric forging nickel/gold (Ni/Au). ), Electroless Nickel/Electroless Palladium/Immersion Gold (ENEPIG) or Electroless Nickel Autocatlytic Gold (ΕΝ AG). As shown in FIG. 2B, the core board 20 is a two-layer or multi-layer circuit board, and the first surface 20a and the second surface 20b of the core board 20 have an implementation structure of a dielectric layer 204, respectively. The device is disposed on the dielectric layer 204 of the first surface 20a, and the ball pad 202 and the metal plate 21 are disposed on the dielectric layer 204 of the second surface 20b, and the metal plate 21 corresponds to the package substrate. The opening 200 is covered by the dielectric layer 204, and the solder resist layer 22' is respectively disposed on the dielectric layer 204 of the first surface 20a and the second surface 20b, and the first surface 2〇a is solderproofed. The layer 22 has a solder resist layer opening 220 corresponding to the opening 200, and the solder resist layer 22 has a plurality of openings 221' to correspondingly expose each of the wire bonds 201, the metal plate 21 and the ball 110858D01 7 201246490 pad 202, and The thickness of the metal plate 21 is greater than the thickness of the ball pad 202 for carrying. As shown in FIG. 2C, the core board 2 is a two-layer or multi-layer circuit board. The first surface 20a and the second surface 20b of the core board 20 respectively have another implementation structure of the dielectric layer 204. The pad 2〇1 is disposed in the dielectric layer 204 of the first surface 20a and is flush with the surface of the dielectric layer 204 of the first surface 20a. The ball pad 202 and the metal plate 21 are disposed on the first surface 20a. The dielectric layer 204 of a surface 20b is flush with the surface of the dielectric layer 204 of the second surface 20b, and the metal plate 21 corresponds to the package substrate opening 200' and is covered by the dielectric layer 204, and The thickness of the metal plate 21 is greater than the thickness of the ball carp 202 for carrying. Referring to FIG. 3, a package substrate as shown in FIG. 2A is provided. A semiconductor wafer 23 is attached to the metal plate 21 in the opening 2 of the core plate 20. The semiconductor wafer 23 has a relative function. The surface 23a and the non-active surface 23b' have a plurality of electrode pads 231 on the active surface 23a, and the semiconductor wafer 23 is fixed on the metal plate 21 in the opening 200 by the adhesive layer 24 by the non-active surface 23b. The wire 25 is electrically connected to the wire pad 201 of the core plate 20; since the thickness s of the metal plate 21 is greater than the thickness h of the ball bump 202, the semiconductor wafer 23 is stably disposed on the metal plate 21' The semiconductor wafer 23 is caused to dissipate heat by the metal plate 21 by the excellent thermal conductivity of the metal plate 21; and on the partial solder resist layer 22 on the first surface 20a of the core plate 20. A sealing material 26' is formed and filled in the opening 200 to cover the semiconductor wafer 23, the wire 25 and the wire pad 201; and the second surface 2b of the core plate 110858D01 201246490 20 a side solder resist layer 22 in the opening 221 of the solder resist layer 22 The metal plate 21 and the ball pad 202 are soldered to the solder balls 27, 27 to form a package in which the solder balls 27 attached to the metal plate 21 are provided for heat dissipation. The solder balls 27 on the ball pad 202 are for external connection to other electronic devices, such as a printed circuit board, which may also be externally connected to another package to form a stacked package (POP) structure. The package substrate of the present invention has an opening and reduces the overall package height by accommodating the semiconductor wafer in the opening; in addition, the thickness of the metal plate is greater than the thickness of the ball pad to stabilize the semiconductor wafer On the metal plate, and using the characteristics of the metal material with good thermal conductivity, the semiconductor wafer is cooled by the metal plate to achieve the purpose of heat dissipation. In summary, the present invention is placed in the opening of the core board by the semiconductor chip, so that the main structure height is only the height of the core board, and the height is not achieved; in addition, by means of: stable, and achieving heat dissipation The purpose of the function. The above embodiments are intended to be illustrative, and not to limit the principles of the present invention and its function without departing from the spirit and scope of the invention. Η Η 帕 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四The patent application model should be applied as follows: [1] The first and second diagrams are conventional ^ 2Α $ 2Γ m. ^ + schematic diagram of the conductor package;
第2A至2C圖係為本 M 象月之封裝基板之剖面示意圖； 110858D01 201246490 以及 第3圖係為本發明之封裝基板之堆疊應用之剖面示意 圖。 【主要元件符號說明】 10、160 基板 10a ' 10b 表面 11 第一半導體晶片 12、163、27、27’ 焊料球 13 第二半導體晶片 14、 25 導線 15、 162、26 封裝材 16 封裝件 161、23 半導體晶片 17 導電元件 20 核心板 200 開口 201 打線墊 201a 表面處理層 202 植球墊 204 介電層 20a 第一表面 20b 第二表面 21 金層板 22 防焊層 110858D01 10 201246490 220 防焊層開口 221 開孔 . 231 電極墊 23a 巍 作用面 23b 非作用面 24 黏著層 h、s 厚度 110858D012A to 2C are schematic cross-sectional views of a package substrate of the present invention; 110858D01 201246490 and Fig. 3 are schematic cross-sectional views showing a stacked application of the package substrate of the present invention. [Main component symbol description] 10, 160 substrate 10a ' 10b surface 11 first semiconductor wafer 12, 163, 27, 27' solder ball 13 second semiconductor wafer 14, 25 wire 15, 162, 26 package material 16 package 161, 23 semiconductor wafer 17 conductive element 20 core board 200 opening 201 wire pad 201a surface treatment layer 202 ball pad 204 dielectric layer 20a first surface 20b second surface 21 gold layer 22 solder mask 110858D01 10 201246490 220 solder mask opening 221 opening. 231 electrode pad 23a 巍 active surface 23b non-active surface 24 adhesive layer h, s thickness 110858D01