TWI418006B - Package substrate having single-layered circuits, package structure and method of forming the same - Google Patents

Description

Single-layer circuit package substrate and its manufacturing method and package structure

The invention relates to a package substrate and a preparation method thereof, in particular to a package substrate of a single-layer circuit and a method and a package structure thereof.

At present, ICs for low-foot counts are accustomed to using single-layer boards for packaging. However, with the booming electronics industry, in order to meet the packaging requirements for semiconductor package miniaturization, package substrates for semiconductor wafers are gradually being used. Reduce the thickness of the substrate to achieve the purpose of making the package light, thin and short.

Please refer to FIGS. 1A to 1E for a cross-sectional view of a package substrate of a conventional single-layer wiring.

As shown in FIG. 1A, a core board 10 having a first surface 10a and a second surface 10b is provided, and a copper metal layer 12 is respectively disposed on the first surface 10a and the second surface 10b of the core board 10.

As shown in FIG. 1B, a resist layer 11 is formed on the metal layer 12 on the first surface 10a, and a patterned opening region 110 is formed in the resist layer 11 to expose a metal layer on a portion of the first surface 10a. 12.

As shown in FIG. 1C, the metal layer 12 in the open region 110 is removed to form a wiring layer 15 having at least one pad 150 and a plurality of second electrical contact pads 152, and the second surface 10b is removed. The metal layer 12 is over to expose the second surface 10b of the core board 10; then, the resist layer 11 is removed to expose the wiring layer 15.

As shown in FIG. 1D, a plurality of openings 100 are formed in the second surface 10b of the core board 10, and the circuit layer 15 is partially exposed in the opening 100 to form a plurality of first electrical contact pads 151. A metal protective layer 14 is formed on the first electrical contact pad 151 to form a package substrate 1.

As shown in FIG. 1E, a semiconductor wafer 16 having a corresponding active surface 16a and an inactive surface 16b is provided, and the non-active surface 16b is attached to the crystal pad 150, and the active surface 16a has a plurality of electrodes. Pads 160, and each of the electrode pads 160 is electrically connected to each of the second electrical contact pads 152 by wires 17, and then coated on the first surface 10a of the core board 10, the semiconductor wafer 16, and the wires 17. The encapsulant 18 is further formed on each of the first electrical contact pads 151, and the crucible is formed into a package structure.

In the conventional package substrate 1, the thickness of the core plate 10 is usually about 60 μm or more, which cannot meet the requirements of a thin package. If the thickness of the core board 10 is reduced to 60 μm or less, the strength of the package substrate 1 is insufficient, and the circuit layer 15 is bent and deformed. Therefore, when the semiconductor wafer 16 is mounted on the crystal pad 150, it is easy. The offset error is generated, and when the wire bonding is performed, the wire 17 is more likely to be electrically connected to the electrode pad 160 and the second electrical contact pad 152 due to the positional error, so that the product is scrapped.

In addition, the package substrate 1 is mainly composed of the core plate 10, and only the metal layer 12 of the first surface 10a of the core plate 10 is patterned to form the circuit layer 15, so in a single patterning process, Only one package substrate 1 can be produced, resulting in an inability to increase productivity.

Therefore, how to avoid the problem that the package substrate of the single-layer circuit in the prior art cannot meet the requirements of thickness and strength, and the inability to increase the productivity has become a problem that is currently being solved.

In view of the above-mentioned various deficiencies of the prior art, it is an object of the present invention to provide a package substrate capable of reducing the thickness of a single-layer circuit and a method and a package structure thereof.

Another object of the present invention is to provide a package substrate of a single-layer circuit capable of improving productivity, a method for fabricating the same, and a package structure.

To achieve the above and other objects, the present invention discloses a package substrate for a single-layer circuit, comprising: a dielectric layer having a first surface and a second surface; and a circuit layer embedded in the dielectric layer and having a pad and a plurality of second electrical contact pads exposed on the first surface of the dielectric layer; and a plurality of openings formed on the second surface of the dielectric layer to expose the circuit layer portion In the opening, 俾 is provided as a plurality of first electrical contact pads.

The package substrate includes a metal protective layer and is disposed on the first electrical contact pad. The thickness of the wiring layer is less than 35 μm.

The invention provides a method for manufacturing a package substrate of a single-layer circuit, comprising: providing a carrier plate having opposite surfaces, and having a release film and an initial metal layer on at least one surface of the carrier plate; Forming a resist layer on the initial metal layer, and forming a patterned opening region in the resist layer to expose a portion of the initial metal layer; thinning the initial metal layer in the open region to form a line pattern and a bottom portion a metal layer, and a bottom of the metal layer is bonded to the release film to separate the wiring pattern from the release film; the resist layer is removed to expose the metal layer; and a dielectric layer is formed on the metal layer And the dielectric layer has first and second surfaces, the circuit pattern is embedded in the first surface of the dielectric layer; and a plurality of openings are formed in the second surface of the dielectric layer to make the circuit pattern Portion is exposed through the opening to form a plurality of first electrical contact pads; removing the carrier and the release film to expose the bottom of the metal layer; and removing the bottom of the metal layer to be embedded in The line pattern in the dielectric layer becomes the line , And the one surface of the wiring layer exposed from the first surface of the dielectric layer and flush with the first surface of the dielectric layer, the substrate to form a package of at least a single line.

The above method comprises forming a metal protective layer on the first electrical contact pad.

According to the above method, the thickness of the circuit layer is less than 35 μm, and the circuit layer has a crystal pad and a second electrical contact pad exposed on the first surface of the dielectric layer.

The present invention further provides a package structure comprising: a package substrate, comprising a dielectric layer having a first surface and a second surface, and a circuit layer embedded in the dielectric layer, the second layer of the dielectric layer The surface has a plurality of openings, such that the circuit layer portion is exposed through the opening to form a plurality of first electrical contact pads, and the circuit layer has a crystal pad exposed to the first surface of the dielectric layer and a plurality of a second electrical contact pad; the semiconductor wafer has a corresponding active surface and a non-active surface, and the non-active surface is placed on the crystal pad, and the active surface has a plurality of electrode pads, each of the electrode pads being composed of a plurality of wires Electrically connecting to each of the second electrical contact pads; and encapsulating the first surface of the package substrate, the semiconductor wafer, and the wires.

The package structure described above further comprises a metal protective layer disposed on the first electrical contact pad. The thickness of the wiring layer is less than 35 μm.

It can be seen that the package substrate of the single-layer circuit of the present invention and the manufacturing method and the package structure thereof are patterned on the initial metal layer on both surfaces of the carrier plate to form the metal layer having the circuit pattern, and then the metal layer Forming a dielectric layer having a better strength to avoid bending, and having the wiring pattern embedded in the dielectric layer, and then separating the carrier plate by the release film to separate into two parts And then removing the bottom of the metal layer to form a wiring layer embedded in the wiring pattern of the dielectric layer to form a package substrate of a single-layer wiring. The carrier board can be reused not only to improve the usability, but also to form a package substrate of two single-layer lines by the two surfaces of the carrier board, thereby improving the productivity. Moreover, the strength of the dielectric layer is increased, thereby reducing the thickness of the package substrate, thereby reducing the overall thickness of the package structure to achieve a thin package.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

Please refer to FIGS. 2A to 2J for a schematic cross-sectional view of the package structure of the present invention.

As shown in FIG. 2A, a carrier 20 having opposite surfaces 20a is provided. The release film 200 and the initial metal layer 201 are sequentially disposed on at least one surface 20a of the carrier 20, wherein the initial metal layer 201 is formed. The material is copper.

As shown in FIG. 2B, a resist layer 21 is formed on the initial metal layer 201, and a patterned opening region 210 is formed in the resist layer 21 to expose a portion of the initial metal layer 201.

As shown in FIG. 2C, the initial metal layer 201 in the open region 210 is thinned to form a metal layer 22 having a line pattern 22a, and the bottom portion 22b of the metal layer 22 (including the initial metal layer in the open region 210) 201) is bonded to the release film 200 to partition the wiring pattern 22a from the release film 200.

As shown in FIG. 2D, the resist layer 21 is removed to expose the metal layer 22.

As shown in FIG. 2E, a dielectric layer 23 is formed on the metal layer 22, and the dielectric layer 23 has a first surface 23a and a second surface 23b opposite to each other, so that the wiring pattern 22a is embedded in the dielectric layer. The dielectric layer 23 is a material having a better strength, such as the addition of glass fibers, to avoid bending and to reduce the overall thickness.

As shown in FIG. 2F, a plurality of openings 230 are formed on the second surface 23b of the dielectric layer 23, and the portion of the line pattern 22a is exposed through the opening 230 to form a plurality of first electrical contact pads 251. .

As shown in FIG. 2G, a metal protective layer 24 of nickel/gold or nickel/palladium/gold is formed on the first electrical contact pad 251.

As shown in FIG. 2H, the carrier sheet 20 is removed by the release film 200, and the removed carrier sheet 20 can be reused for making other substrates.

As shown in FIG. 2I, the bottom portion 22b of the metal layer 22 (ie, the metal layer 22 other than the wiring pattern 22a) is removed, so that the line pattern 22a embedded in the dielectric layer 23 becomes the desired wiring layer 25, And a surface of the circuit layer 25 is exposed on the first surface 23a of the dielectric layer 23 and flush with the first surface 23a of the dielectric layer 23 to form the package substrate 2 of the desired single-layer line. The thickness of the circuit layer 25 is less than 35 μm; and the portion of the circuit layer 25 exposed on the first surface 23a of the dielectric layer 23 is provided as a pad 250 and a plurality of second electrical contact pads 252, such as 2J. The figure shows.

The present invention provides a single-layer circuit package substrate 2, as shown in FIG. 2I, including a dielectric layer 23 having a first surface 23a and a second surface 23b opposite thereto, and is embedded in the dielectric layer 23. And a circuit layer 25 exposed on the first surface 23a of the dielectric layer 23 and an opening 230 formed in the second surface 23b of the dielectric layer 23.

The circuit layer 25 has a pad 250 and a plurality of second electrical contact pads 252 exposed on the first surface 23a of the dielectric layer 23 (please refer to FIG. 2J). Further, the material forming the wiring layer 25 is copper, and the thickness of the wiring layer 25 is less than 35 μm.

The opening 230 is such that the circuit layer 25 is partially exposed in the opening 230 for use as the plurality of first electrical contact pads 251.

The package substrate 2 further includes a metal protective layer 24 of nickel/gold or nickel/palladium/gold, which is disposed on the first electrical contact pad 251.

As shown in FIG. 2J, in the subsequent process, the semiconductor wafer 26 is disposed on the package substrate 2, and the semiconductor wafer 26 and the package substrate 2 are electrically connected by the wires 27, and then sealed by the encapsulant 28 to make the film. The aspect of a package structure of the invention.

In the package structure, the package substrate 2 is composed of a dielectric layer 23 having a first surface 23a and a second surface 23b, and is embedded in the dielectric layer 23 and a surface is exposed on the dielectric layer 23. The second surface 23b of the first surface 23a has a plurality of openings 230, and the circuit layer 25 is partially exposed in the opening 230 to form a plurality of first electrical contact pads. 251, and the circuit layer 25 has a pad 250 and a plurality of second electrical contact pads 252 exposed on the first surface 23a of the dielectric layer 23.

The semiconductor wafer 26 has a corresponding active surface 26a and an inactive surface 26b, and the semiconductor wafer 26 is placed on the crystal pad 250 with the non-active surface 26a, and the active surface 26a has a plurality of electrode pads 260. Each of the electrode pads 260 is electrically connected to each of the second electrical contact pads 252 by a plurality of wires 27 .

The encapsulant 28 covers the first surface 23a of the package substrate 2, the semiconductor wafer 26, and the wires 27.

The package structure further includes a plurality of solder balls 29 corresponding to the first electrical contact pads 251.

In addition, the package structure shown in FIG. 2J is a wire-wound package structure. In other embodiments, the package structure may be a flip-chip package structure, that is, the semiconductor wafer is electrically connected to the package substrate 2 in a flip chip manner.

In summary, the package substrate of the single-layer circuit of the present invention and the method and package structure thereof are formed by patterning a preliminary metal layer on both surfaces of the carrier to form the metal layer having the line pattern, and then Forming a dielectric layer having a preferred strength on the metal layer to avoid bending, and having the wiring pattern embedded in the dielectric layer, and then separating the carrier plate by the release film to separate Two-part substrate prototype (finally two package substrates can be formed), and then the bottom of the metal layer is removed to form a circuit layer embedded in the dielectric layer to form a circuit layer of the single-layer wiring . In this way, not only the carrier board can be reused, but also the utility model can be improved, and the two substrates of the single-layer circuit can be respectively formed by using the two surfaces of the carrier board, thereby effectively improving the productivity.

Moreover, the dielectric layer can not only improve the strength, but also reduce the thickness of the package substrate, thereby reducing the overall thickness of the package structure, and effectively achieving the purpose of thin packaging.

The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

1, 2‧‧‧ package substrate

10‧‧‧ core board

10a, 23a‧‧‧ first surface

10b, 23b‧‧‧ second surface

100, 230‧‧‧ openings

11, 21‧‧‧ resistance layer

110, 210‧‧‧Open area

12, 22‧‧‧ metal layer

14, 24‧‧‧ metal protective layer

15, 25‧‧‧ circuit layer

150, 250‧‧‧ crystal pad

151, 251‧‧‧ first electrical contact pads

152, 252‧‧‧second electrical contact pads

16, 26‧‧‧ semiconductor wafer

16a, 26a‧‧‧ action surface

16b, 26b‧‧‧ non-active surface

160, 260‧‧‧ electrode pads

17, 27‧‧‧ wires

18, 28‧‧‧Package colloid

19, 29‧‧‧ solder balls

20‧‧‧Loading board

20a‧‧‧ surface

200‧‧‧ release film

201‧‧‧Initial metal layer

22a‧‧‧ line pattern

22b‧‧‧ bottom

23‧‧‧Dielectric layer

1A to 1E are schematic cross-sectional views showing a conventional package substrate of a single-layer circuit;

2A to 2J are schematic cross-sectional views showing a package substrate of a single-layer circuit of the present invention, and a method and a package structure thereof.

2‧‧‧Package substrate

23‧‧‧Dielectric layer

23a‧‧‧ first surface

23b‧‧‧ second surface

230‧‧‧ openings

24‧‧‧ metal protective layer

25‧‧‧Line layer

251‧‧‧First electrical contact pad

Claims (10)

A package substrate for a single layer line, comprising:
a dielectric layer having a first surface and a second surface;
The circuit layer is embedded in the dielectric layer and has a crystal pad exposed on the first surface of the dielectric layer and a plurality of second electrical contact pads; and a plurality of openings formed in the dielectric layer The second surface is such that the circuit layer portion is exposed in the opening and is provided as a plurality of first electrical contact pads. The package substrate of the single-layer circuit of claim 1 is further provided with a metal protective layer disposed on the first electrical contact pad. The package substrate of the single-layer circuit of claim 1, wherein the circuit layer has a thickness of less than 35 μm. A method for manufacturing a package substrate of a single-layer circuit includes:
Providing a carrier plate having opposite surfaces, and having a release film and an initial metal layer on at least one surface of the carrier plate;
Forming a resist layer on the initial metal layer, and forming a patterned opening region in the resist layer to expose a portion of the initial metal layer;
Thinning the initial metal layer in the open area to form a metal layer having a line pattern and a bottom, and the bottom of the metal layer is bonded to the release film to separate the line pattern from the release film;
Removing the resist layer to expose the metal layer;
Forming a dielectric layer on the metal layer, and the dielectric layer has first and second surfaces, and the circuit pattern is embedded in the first surface of the dielectric layer;
Forming a plurality of openings in the second surface of the dielectric layer, wherein the circuit pattern portion is exposed through the opening to form a plurality of first electrical contact pads;
Removing the carrier plate and the release film to expose the bottom of the metal layer; and removing the bottom of the metal layer, so that the circuit pattern embedded in the dielectric layer becomes a circuit layer, and one surface of the circuit layer Exposed on the first surface of the dielectric layer and flush with the first surface of the dielectric layer to form a package substrate of at least one single layer of circuitry. The method for manufacturing a package substrate of a single-layer circuit of claim 4, further comprising forming a metal protection layer on the first electrical contact pad. The method for manufacturing a package substrate of a single-layer circuit according to claim 4, wherein the thickness of the circuit layer is less than 35 μm. The method for manufacturing a package substrate of a single-layer circuit according to claim 4, wherein the circuit layer has a crystal pad exposed on the first surface of the dielectric layer and a plurality of second electrical contact pads. A package structure includes:
The package substrate is composed of a dielectric layer having a first surface and a second surface and a circuit layer embedded in the dielectric layer, the second surface of the dielectric layer having a plurality of openings, and the circuit layer portion The portion is exposed to form a plurality of first electrical contact pads, and the circuit layer has a crystal pad exposed to the first surface of the dielectric layer and a plurality of second electrical contact pads;
The semiconductor wafer has a corresponding active surface and a non-active surface, and the non-active surface is placed on the crystal pad, and the active surface has a plurality of electrode pads, and each of the electrode pads is electrically connected to each of the electrodes by wires a second electrical contact pad; and an encapsulant that covers the first surface of the package substrate, the semiconductor wafer, and the wires. For example, the package structure of claim 8 includes a metal protective layer disposed on the first electrical contact pad. The package structure of claim 8 wherein the thickness of the circuit layer is less than 35 μm.