CN102655097B - Semiconductor package structure and manufacturing method thereof - Google Patents
Semiconductor package structure and manufacturing method thereof Download PDFInfo
- Publication number
- CN102655097B CN102655097B CN201110106224.7A CN201110106224A CN102655097B CN 102655097 B CN102655097 B CN 102655097B CN 201110106224 A CN201110106224 A CN 201110106224A CN 102655097 B CN102655097 B CN 102655097B
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- China
- Prior art keywords
- chip
- metal layer
- support plate
- active face
- semiconductor package
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 38
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 239000002184 metal Substances 0.000 claims abstract description 86
- 229910052751 metal Inorganic materials 0.000 claims abstract description 86
- 239000000758 substrate Substances 0.000 claims abstract description 40
- 238000000034 method Methods 0.000 claims abstract description 26
- 239000000853 adhesive Substances 0.000 claims description 14
- 230000001070 adhesive effect Effects 0.000 claims description 14
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 5
- 238000007747 plating Methods 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 4
- 238000009826 distribution Methods 0.000 claims description 2
- 238000003384 imaging method Methods 0.000 claims description 2
- 238000003825 pressing Methods 0.000 claims description 2
- 238000004544 sputter deposition Methods 0.000 claims description 2
- 238000004806 packaging method and process Methods 0.000 abstract description 11
- 239000000084 colloidal system Substances 0.000 abstract 2
- 238000007789 sealing Methods 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 39
- 230000000694 effects Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000012216 screening Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a semiconductor packaging structure and a manufacturing method thereof. The semiconductor packaging structure comprises a chip packaging body and a redistribution substrate, wherein the redistribution substrate is arranged below the chip packaging body and is electrically connected with the chip packaging body. Wherein the chip package includes: a metal layer having an opening; a chip disposed on the opening, wherein a back surface of the chip and an upper surface of the metal layer face in the same direction; and the sealing colloid covers the back surface of the chip and the upper surface of the metal layer, and an active surface and part of the metal layer of the chip are exposed outside the sealing colloid so as to electrically connect the heavy wiring substrate and the chip. The invention utilizes the chip to be packaged firstly and then combined with the redistribution wire substrate, and the metal layer is arranged in the chip packaging body and positioned on the joint surface of the chip packaging body and the substrate, so that the joint force between the chip packaging body and the substrate can be increased, and the process yield can be improved.
Description
Technical field
The present invention about a kind of semiconductor packaging, particularly a kind of semiconductor package and manufacture method thereof.
Background technology
In semiconductor packaging process, because the trend that electronic product is compact adds that function is on the increase, packaging density is improved constantly thereupon, also constantly reduce package dimension and improvement encapsulation technology.The encapsulation technology how developing to improve process yields and improve radiating efficiency is the important topic of technical field for this reason always.
Summary of the invention
In order to solve the problem, the object of the invention is to provide a kind of semiconductor package and manufacture method thereof, to improve process yields and to improve radiating efficiency.A kind of manufacture method of semiconductor package is provided according to an aspect of the present invention, is characterized in comprising the following steps: formation one chip packing-body and providing a heavy wiring substrate below chip packing-body, and is electrically connected with chip packing-body.The step wherein forming chip packing-body comprises: provide a support plate; Form the upper surface that a first metal layer is formed at support plate; Formed and be at least onely opened on the first metal layer, with exposed portion support plate; Arrange a chip on the part support plate exposed, an active face of its chips is towards support plate; Form an adhesive body and cover chip and the first metal layer; And remove support plate with the active face of exposed chip and the first metal layer.
A kind of manufacture method of semiconductor package is provided according to a further aspect of the invention, is characterized in comprising the following steps: formation one chip packing-body and providing a heavy wiring substrate below chip packing-body, and is electrically connected with chip packing-body.Wherein form a chip packing-body, its step comprises: provide a support plate; Arrange a chip on support plate, an active face of its chips is towards support plate; Form a first metal layer and cover chip and support plate; Form an adhesive body and cover chip and the first metal layer; And remove support plate with the active face of exposed chip and the first metal layer.
There is provided a kind of semiconductor package according to another aspect of the invention, be characterized in comprising: a chip packing-body, comprising: a first metal layer, there is an opening; One chip is positioned on opening, and a back side of its chips and a upper surface of the first metal layer are towards same direction; And an adhesive body, cover the back side of chip and the upper surface of the first metal layer, and a lower surface of an active face of chip and the first metal layer is exposed to adhesive body.And one heavy wiring substrate be arranged at below chip packing-body, and to be electrically connected with the active face of chip.
Advantageous Effects of the present invention is: utilize first to encapsulate chip and be combined with reprovision line substrate, and be provided with metal level in chip packing-body and be positioned at the composition surface with substrate, engaging force between chip packing-body and substrate can be increased like this to improve process yields and the radiating efficiency of chip can be increased, and EMI screening effect can be improved.
Below cooperation accompanying drawing is illustrated in detail to preferred embodiment of the present invention, when the effect that can be easier to understand object of the present invention, technology contents, feature and reach.
Accompanying drawing explanation
Fig. 1 is the structure cutaway view of the manufacture method of the semiconductor package of one embodiment of the invention.
Fig. 2 A, Fig. 2 B, Fig. 2 C, Fig. 2 D, Fig. 2 E, Fig. 2 F are the structure cutaway view of the semiconductor package of one embodiment of the invention.
Fig. 3 A, Fig. 3 B are the structure cutaway view of the semiconductor package of different embodiments of the invention.
Fig. 4 A, Fig. 4 B, Fig. 4 C, Fig. 4 D, Fig. 4 E, Fig. 4 F, Fig. 4 G are the structure cutaway view of the semiconductor package of one embodiment of the invention.
Embodiment
It is described in detail as follows, and described preferred embodiment is only done an explanation and is not used to limit the present invention.
Please refer to Fig. 1, Fig. 1 is the structure cutaway view of the manufacture method of the semiconductor package of one embodiment of the invention.As shown in the figure, the manufacture method of semiconductor package comprises the following steps: formation one chip packing-body 100 and provides a heavy wiring substrate 200 below chip packing-body 100, and heavy wiring substrate 200 is electrically connected with chip packing-body 100.
Continue above-mentioned, in an embodiment, form the step of chip packing-body 100 as shown in Fig. 2 A to Fig. 2 E.First, as Fig. 2 A, provide a support plate 110, and form the upper surface 112 that a first metal layer 120 is formed at support plate 110.In an embodiment, the first metal layer 120 includes but not limited to a conductive metal film, and the first metal layer 120 is arranged on support plate 110 with pressing mode, is separately understandable that, except single layer structure, the first metal layer 120 also can be composite film and forms by more metal layers is stacking.Then, please refer to Fig. 2 B, form at least one opening 122 on the first metal layer 120, with the upper surface 112 of exposed portion support plate 110.And the method forming opening 122 comprises the mode of dry film exposure imaging.Then, as shown in Figure 2 C, arrange a chip 130 on the part support plate 110 exposed, an active face 132 of its chips 130 is towards support plate 110, and the back side 134 of chip 130 is support plates 110 dorsad.Afterwards, please refer to Fig. 2 D, form an adhesive body 140 and cover chip 130 and the first metal layer 120.Again then, remove support plate 110 with exposed portion chip 130 and the first metal layer 120, the active face 132 of such as chip 130 and the lower surface 123 of the first metal layer 120, as shown in Figure 2 E.Finally, as shown in Figure 2 F, provided heavy wiring substrate 200 is arranged at below chip packing-body 100, and heavy wiring substrate 200 is electrically connected with the active face 132 of chip 130.
In an embodiment, the first metal layer 120 also can utilize deposition or plating mode to be formed on the upper surface 112 of support plate 110.In addition, please refer to Fig. 3 A, in another embodiment, before formation adhesive body 140 coating chip 130, also comprise forming the back side 134 that one second metal level 125 covers chip 130.Also or, as shown in Figure 3 B, the second metal level 125 also comprises and covers a side 135 of chip 130, and wherein the second metal level 125 can be identical material with the first metal layer 120.By the covering of metal level to chip, effect that EMI covers can be promoted.In addition, the setting of metal level also can increase the engaging force between unlike material, such as, increase the engaging force between packaging body 140 and heavy wiring substrate 200.
Utilize structure that the manufacture method of above-described embodiment is formed as shown in Figure 2 F.As shown in the figure, semiconductor package comprises: chip packing-body 100 and a heavy wiring substrate 200.Wherein chip packing-body 100 comprises: a first metal layer 120, and it has an opening 122, and wherein the material of the first metal layer 120 is including but not limited to copper.One chip 130 is arranged on opening 122, and a back side 134 of its chips 130 is towards same direction with a upper surface 121 of the first metal layer 120.And one adhesive body 140 cover the back side 134 of chip 130 and the upper surface 121 of the first metal layer 120, and an active face 132 of chip 130 is exposed to adhesive body 140 with a lower surface 123 of the first metal layer 120; And a heavy wiring substrate 200, be arranged at below chip packing-body 100, and be electrically connected with the active face 132 of chip 130.
Continue above-mentioned, in an embodiment, heavy wiring substrate 200 comprises multiple interior electric connection pad 210, multiple dispatch from foreign news agency connection pad 212 and multiple connection wire road 220, and wherein each one end, connection wire road 220 connects interior electric connection pad 210, another end and connects dispatch from foreign news agency connection pad 212.And as shown in the figure, interior electric connection pad 210 is electrically connected with the active face 132 of chip 130.And multiple soldered ball 230 is arranged on the dispatch from foreign news agency connection pad 212 of heavy wiring substrate 200, be electrically connected for external device.In an embodiment, heavy wiring substrate 200 is attached most importance to distribution film substrate.
In an embodiment, as shown in Figure 3A, chip packing-body 100 also comprises one second metal level 125, is arranged at the back side 134 of chip 130.In another embodiment, as shown in Figure 3 B, the second metal level 125 also comprises the side 135 covering chip 130, and the first metal layer 120 can be identical material with the second metal level 125, such as copper.Please continue to refer to Fig. 3 B, wherein heavy wiring substrate 200 also comprises at least one ground path 222, connects the first metal layer 120 and connection wire road 220.Cover chip by metal level, not only provide and cover and good engaging force, also can improve chip cooling problem.
In another embodiment, the step forming chip packing-body 100 also can as shown in Fig. 4 A to Fig. 4 D.Be first to arrange chip on support plate with above-described embodiment difference, then form the first metal layer covering chip, it states as follows in detail.First, as Fig. 4 A, provide a support plate 110.Then, arrange a chip 130 on support plate 110, an active face 132 of its chips 130 is towards support plate 110, and the back side 134 of chip 130 is support plates 110 dorsad.Then, please refer to Fig. 4 B, form a first metal layer 120 and cover chip 130, include but not limited to the back side 134 of covering chip 130, side 135 and support plate 110.Then, as shown in Figure 4 C, form an adhesive body 140 and cover chip 130 and the first metal layer 120.Again then, support plate 110 is removed with the lower surface 123 of the active face 132 of exposed chip 130 and the first metal layer 120, as shown in Figure 4 D.In an embodiment, the first metal layer 120 can utilize deposition or plating mode is formed, if formed with plating mode, then before formation the first metal layer 120, also comprise and form metallic bond layer 126, such as a nickel with sputtering way, cover chip 130 and support plate 110, then to remove after support plate 110 as shown in Figure 4 E, the active face 132 of metallic bond layer 126 and chip 130 can be exposed.Thereafter, shown in Fig. 4 F, provided heavy wiring substrate 200 is arranged at below chip packing-body 100, and heavy wiring substrate 200 is electrically connected with the active face 132 of chip 130.As shown in Figure 4 G, also can as described in above-described embodiment, heavy wiring substrate 200 can comprise at least one ground path 222 and connect the first metal layer 120 and connection wire road 220.
Comprehensively above-mentioned, a kind of semiconductor package of one embodiment of the invention and manufacture method thereof, utilize and the combination of reprovision line substrate is first encapsulated in chip again, and be provided with the first metal layer in chip packing-body and be positioned at the composition surface with substrate, engaging force between chip packing-body and substrate can be increased to improve process yields.In addition, metal level can increase the radiating efficiency of chip, and can improve EMI screening effect.
Above-described embodiment is only in order to technological thought of the present invention and feature are described, its object understands content of the present invention implementing according to this enabling person skilled in the art person, when can not with restriction the scope of the claims of the present invention, namely every equivalent change of doing according to disclosed spirit or replacement, must be encompassed in the scope of the claims of the present invention.
Claims (19)
1. a manufacture method for semiconductor package, is characterized in that comprising the following step:
Form a chip packing-body, its step comprises:
One support plate is provided;
Form a first metal layer in a upper surface of this support plate;
Formed and be at least onely opened on this first metal layer, with this upper surface of this support plate of exposed portion;
Arrange a chip on this support plate of the part exposed, wherein a part for a side of this first metal layer and a side of this chip contacts with each other, and wherein an active face of this chip is towards this support plate;
Form an adhesive body and cover this chip and this first metal layer; And
Remove this support plate to expose this active face and this first metal layer of this chip; And
There is provided a heavy wiring substrate below this chip packing-body, and this active face of this heavy wiring substrate and this chip is electrically connected.
2. the manufacture method of semiconductor package according to claim 1, is characterized in that, the mode forming this opening comprises the mode of dry film exposure imaging.
3. the manufacture method of semiconductor package according to claim 1, is characterized in that, this first metal layer is a conductive metal film, and this first metal layer is arranged on this support plate with pressing mode.
4. the manufacture method of semiconductor package according to claim 1, is characterized in that, this first metal layer is formed at this upper surface of this support plate with deposition or plating mode.
5. the manufacture method of semiconductor package according to claim 1, is characterized in that, before this adhesive body of formation, also comprises formation one second metal level and covers the back side of this chip relative to this active face.
6. the manufacture method of semiconductor package according to claim 5, is characterized in that, this second metal level also comprises the part covering and do not contact with this first metal layer in this side of this chip.
7. a manufacture method for semiconductor package, is characterized in that comprising the following step:
Form a chip packing-body, its step comprises:
One support plate is provided;
Arrange a chip on this support plate, wherein an active face of this chip is towards this support plate;
Form a first metal layer and cover this chip and this support plate;
Form an adhesive body and cover this chip and this first metal layer; And
Remove this support plate to expose this active face and this first metal layer of this chip; And
There is provided a heavy wiring substrate below this chip packing-body, and this active face of this heavy wiring substrate and this chip is electrically connected.
8. the manufacture method of semiconductor package according to claim 7, is characterized in that, this first metal layer is formed at a upper surface of this support plate with deposition or plating mode.
9. the manufacture method of semiconductor package according to claim 7, is characterized in that, before this first metal layer of formation, also comprises and forms a metallic bond layer with sputtering way and cover this chip and this support plate.
10. the manufacture method of semiconductor package according to claim 7, is characterized in that, this first metal layer covers a side of this chip and covers the back side of this chip relative to this active face.
11. 1 kinds of semiconductor packages, is characterized in that comprising:
One chip packing-body, comprises:
One the first metal layer, has an opening;
One chip, is positioned on this opening, and wherein a part for a side of this first metal layer and a side of this chip contacts with each other, and wherein the back side of this chip and the upper surface of this first metal layer are towards same direction; And
One adhesive body, cover this back side of this chip and this upper surface of this first metal layer, and a lower surface of an active face of this chip and this first metal layer is exposed to this adhesive body; And
One heavy wiring substrate, is arranged at below this chip packing-body, and is electrically connected with this active face of this chip.
12. semiconductor packages according to claim 11, is characterized in that, also comprise one second metal level, are arranged at least on one of them of the part do not contacted with this first metal layer in this back side of this chip and this side of this chip.
13. semiconductor packages according to claim 12, is characterized in that, this second metal level and this first metal layer are identical material.
14. semiconductor packages according to claim 11, it is characterized in that, this heavy wiring substrate comprises multiple interior electric connection pad, multiple dispatch from foreign news agency connection pad and multiple connection wire road, wherein each this one end, connection wire road connects this interior electric connection pad, the other end connects this dispatch from foreign news agency connection pad, and wherein in these, this active face of electric connection pad and this chip is electrically connected.
15. semiconductor packages according to claim 14, is characterized in that, also comprise multiple soldered ball and are arranged on these dispatch from foreign news agency connection pads of this heavy wiring substrate.
16. semiconductor packages according to claim 14, is characterized in that, this heavy wiring substrate also comprises at least one ground path, connect this first metal layer and this connection wire road.
17. semiconductor packages according to claim 11, is characterized in that, this first metal layer is a conductive metal film.
18. semiconductor packages according to claim 17, is characterized in that, this first metal layer forms by more metal layers is stacking.
19. semiconductor packages according to claim 11, is characterized in that, this heavy wiring substrate is attached most importance to distribution film substrate.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW100107294A TWI462201B (en) | 2011-03-04 | 2011-03-04 | Semiconductor package structure and method for fabricating the same |
| TW100107294 | 2011-03-04 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102655097A CN102655097A (en) | 2012-09-05 |
| CN102655097B true CN102655097B (en) | 2016-03-02 |
Family
ID=46730703
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110106224.7A Active CN102655097B (en) | 2011-03-04 | 2011-04-18 | Semiconductor package structure and manufacturing method thereof |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN102655097B (en) |
| TW (1) | TWI462201B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI549234B (en) * | 2014-01-17 | 2016-09-11 | 矽品精密工業股份有限公司 | Layer structure for contacting setting semiconductor device and manufacturing method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101179062A (en) * | 2002-05-27 | 2008-05-14 | 日本电气株式会社 | Semiconductor device mounting board and semiconductor package |
| CN101364579A (en) * | 2007-08-10 | 2009-02-11 | 三星电子株式会社 | Semiconductor package, method of manufacturing the same and system containing the package |
| CN101964339A (en) * | 2009-07-23 | 2011-02-02 | 日月光半导体制造股份有限公司 | Semiconductor packaging piece, manufacturing method thereof and manufacturing method of rerouted chip package |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI313037B (en) * | 2006-12-12 | 2009-08-01 | Siliconware Precision Industries Co Ltd | Chip scale package structure and method for fabricating the same |
| US7842542B2 (en) * | 2008-07-14 | 2010-11-30 | Stats Chippac, Ltd. | Embedded semiconductor die package and method of making the same using metal frame carrier |
| US7812449B2 (en) * | 2008-09-09 | 2010-10-12 | Stats Chippac Ltd. | Integrated circuit package system with redistribution layer |
| US8008125B2 (en) * | 2009-03-06 | 2011-08-30 | General Electric Company | System and method for stacked die embedded chip build-up |
-
2011
- 2011-03-04 TW TW100107294A patent/TWI462201B/en not_active IP Right Cessation
- 2011-04-18 CN CN201110106224.7A patent/CN102655097B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101179062A (en) * | 2002-05-27 | 2008-05-14 | 日本电气株式会社 | Semiconductor device mounting board and semiconductor package |
| CN101364579A (en) * | 2007-08-10 | 2009-02-11 | 三星电子株式会社 | Semiconductor package, method of manufacturing the same and system containing the package |
| CN101964339A (en) * | 2009-07-23 | 2011-02-02 | 日月光半导体制造股份有限公司 | Semiconductor packaging piece, manufacturing method thereof and manufacturing method of rerouted chip package |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201237974A (en) | 2012-09-16 |
| CN102655097A (en) | 2012-09-05 |
| TWI462201B (en) | 2014-11-21 |
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Address after: Room 1002, 10th Floor, Hall 2, No. 321, Section 2, Guangfu Road, East District, Hsinchu, Taiwan, China, China Patentee after: Quncheng Energy Co.,Ltd. Address before: Taiwan County, Hsinchu, China Hukou Zhongxing village, Guangfu Road, No. 5, building 65 Patentee before: ADL Engineering Inc. |
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Effective date of registration: 20240116 Address after: No. 8, Lixing 6th Road, Science Industrial Park, Hsinchu, Taiwan, China, China Patentee after: Taiwan Semiconductor Manufacturing Co.,Ltd. Address before: Room 1002, 10th Floor, Hall 2, No. 321, Section 2, Guangfu Road, East District, Hsinchu, Taiwan, China, China Patentee before: Quncheng Energy Co.,Ltd. |
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