201237974 法，係包括下列步驟：形成一晶片封裝體以及提供一重配線 .基板於晶片封裝體下方，並與晶片封裝體電性連接。其中形 成一晶片封裝體’其步驟包括：提供一載板；設置一晶片於 載板上，其中晶片之一主動面係朝向載板；形成一第一金屬 層覆蓋晶片與載板；形成一封膠體覆蓋晶片與第一金屬層； 以及移除载板以露出晶片的主動面及第一金屬層。 本發明目的之一係提供一種半導體封裝結構，係包括： 一晶片封裝體，包括：一第一金屬層，具有—開口.； 一晶片 位於開口上，其中晶片之一背面與第一金屬層之一上表面係 朝向同一方向；以及一封膠體覆蓋晶片之背面與第一金屬層 之上表面，且晶片之一主動面與第一金屬層之一下表面係露 出於封膠體。以及一重配線基板設置於晶片封裝體下方，並 與晶片之主動面電性連接。 以下藉由具體實施例配合所附的圖式詳加說明，當更容 易瞭解本發明之目的、技術内容、特點及其所達成之功效。 【實施方式】 其詳細說明如下，所述較佳實施例僅做一說明非用以限 定本發明。 園 马本發明 、 ▼，〜”貫施例之半導體封裝結構之 ,迨方法的 '纟。構剖視圖。如圖所示，半導體封裝結構之製造 方法包括下列步驟：形成-晶片封裝體100以及提供-重配 於晶片封裝體刚下方，並使重配線基板200盘 日日片封裝體1 〇〇電性連接。 、 接續上述，於—實施例中，形成晶片封裝體_ 如圖2A至圖2E所+、，4· 你 开所不。瓦先，如圖2A，提供一載板"〇,並 七成一第-金屬層120形成於載板110之一上表面112。於【 5 201237974 六、發明說明： 【發明所屬之技術領域】 種半導體 本發明係有關一種半導體封裝技術，特別是一 封裝結構及其製造方法。 【先前技術】 =半導體封裝製程甲，由於電子產品輕薄短小的趨勢加 j能不斷增多’使得封裝密度隨之不斷提高，亦不斷縮小 'f虞尺寸與改良封裝技術。如何開發以提高製程良率與改善 散熱效率之封裝技術一直為為此技術領域之重要課題。 【發明内容】 為了解決上述問題，本發明目的之一係提供一種半導體 封裝結構及其製造方法’利料以先封裝再與重配線基板 結合，且晶片封裝體内設有金屬層位於與基板的接合面，可 增加晶片料體與基板之間的接合力以提高製程良率及散埶 效率。 ‘' 、本發明目的之一係提供一種半導體封裝結構之製造方 法，係包括下列步驟：形成一晶片封裝體以及提供一重配線 基板於晶片封裝體下方，並與晶片封裝體電性連接。其中形 成晶片封裝體之步驟包括：提供一載板；形成一第一金屬層 形成於載板之一上表面；形成至少一開口於第一金屬層上， 以露出部分載板；設置一晶片於露出的部分載板上，&中晶 片之一主動面係朝向載板；形成一封膠體覆蓋晶片與第一金 屬層’以及移除載板以露出晶片之主動面及第一金屬層。 本發明目的之一係提供一種半導體封裝結構之製造方 201237974 一實施例中，第一金屬層120包括但不限於一導電金屬薄 膜，且第一金屬層120係以壓合方式設置於載板110上，另 可以理解的是，除單層結構之外，第一金屬層12〇亦可為複 合膜層由多層金屬層堆疊而成。接著，請參考圖2B，形成至 少一開口 122於第一金屬層120上，以露出部分載板11〇之 上表面112。而形成開口 122的方法包括乾膜曝光顯影的方 式。再來，如圖2C所示，設置一晶片130於露出的部分載 板110上，其中晶片130之一主動面丨32係朝向載板u〇， 晶片130之一背面丨34係背向載板ι10。接著，請參考圖2D’ 形成一封膠體140覆蓋晶片130與第一金屬層12〇。再來， 移除載板110以露出部分晶片130及第一金屬層丨2〇 ,例如 晶片130的主動面132及第一金屬層12〇之下表面123，如 圖2E所示。最後，如圖2F所示，將所提供的重配線基板2〇〇 設置於晶片封裝體1〇〇下方，並使重配線基板2〇〇與晶片13〇 的主動面132電性連接。 於貫施例中，第-金屬| i 2〇亦可利用沉積或電鑛方 式形成於載板110之上表面112。此外，請參考圖3A，於又 一實施例中，在形成封膠體14〇包覆晶片13〇之前，更包括 以形成一第二金屬層125覆蓋晶片130之一背面134。亦或 者如圖3B所不，第二金屬層125更包括覆蓋晶片⑽之 側面135 ’其中第—金屬層125與第—金屬層㈣可為相 同材貝。藉由金屬層對晶片的覆蓋’可提升腿遮蔽的功效。 此外’金屬層的設置亦可増加不同材質之_接合力，例如 增加封裝體140與重配線基板2〇〇之間的接合力。 矛！用上述貫她例之製作方法所形成之結構如圖a所示。 如圖所示，半導體封裝結構包括：—晶片封裝體·以及-重配線基板200。其中晶片封裝體1〇〇包括：一第一金屬層 20 /…、有開口 122 ’其中第一金屬層12〇的材質包含但 201237974 不限於銅。一晶片130設置於開口 122上，其中晶片13〇之 一背面134與第一金屬層12〇之一上表面121係朝向同一方 向。以及一封膠體14〇覆蓋晶片13〇之背面134與第一金屬 層〗20之上表面121，且晶片130之一主動面132與第一金 屬層120之一下表面123係露出於封膠體14〇 ;以及一重配 線基板200，設置於晶片封裝體1〇〇下方，並與晶片13〇之 主動面132電性連接。 接續上述，於一實施例中，重配線基板2〇〇包括複數個 内電接墊210、複數個外電接墊212與複數個内連接線路 220，其中母一内連接線路220 —端連接内電接塾21〇，一另 端連接外電接墊212。且如圖所示，内電接墊21〇與晶片13〇 之主動面132電性連接。而複數個焊球23〇設置於重配線基 板200的外電接墊212上，以供與外界裝置電性連接。於: 實施例中，重配線基板200為重配線薄膜基板。 於一實施例中，如圖3A所示，晶片封裝體1〇〇更包括一 第一金屬層125設置於晶片130之背面134。於又一實施例 申，如圖3B所示，第二金屬層125更包括覆蓋晶片丨3〇之 側面〗35,且第一金屬層120與第二金屬層125可為相同材 質，例如銅。請繼續參考圖3B，其中重配線基板2〇〇更包括 至少一接地線路222連接第一金屬層12〇與内連接線路 220。藉由金屬層覆蓋晶片，不僅提供遮蔽及良好的接合力， 亦可改善晶片散熱問題。 於又一實施例中，形成晶片封裝體1〇〇之步驟亦可如圖 4A至圖4D所示。與上述實施例不同之處在於先設置晶片於 載板上，再形成第一金屬層覆蓋晶片，其詳細述如下。首先， 如圖4A’提供一載板110。接著，設置一晶片130於載板11〇 上，其中晶片130之一主動面132係朝向載板110,晶片no 之者面134係背向載板110。接著，請參考圖4B，形成一『y 201237974 第金屬層120覆蓋晶片130，包括但不限於覆蓋晶片I% 的背面134、側面135與載板110。接著，如如圖4C所示， 形成一封膠體140覆蓋晶片130與第一金屬層12〇。再來， 移除載板110以露出晶片130的主動面132及第一金屬層12〇 的下表面123，如圖4D所示。於一實施例中，第一金屬層 120可利用沉積或是電鍍方式形成，若以電鍍方式形成，則 在形成第一金屬層120之前，更包括以濺鍍方式形成一金屬 接合層126,例如鎳’覆蓋晶片13〇與載板11〇,則移除載板 110後如圖4E所示，會露出金屬接合層126與晶片13〇的主 動面132。其後，如同圖4F所示，將所提供的重配線基板2〇〇 設置於晶片封裝體1〇〇下方，並使重配線基板2〇〇與晶片13〇 的主動面132電性連接。如圖4G所示，亦可如上述實施例 中所述，重配線基板2〇〇可包括至少一接地線路222連接第 一金屬層120與内連接線路22〇。 ，，綜合上述，本發明一實施例之一種半導體封裝結構及其 製造方法，湘對晶片先封裝在再重配線基板結合，且晶片 封裝體内設有第-金屬層位於與基板的接合面，可增加晶片 封裝體與基板之間的接合力以提高製程良率。此外，金屬層 可增加晶片的散熱效率，並可提高EMI遮蔽效果。 以上所述之實施例僅係為說明本發明之技術思想及特 點，其f的在使熟習此項技藝之人士能夠瞭解本發明之内容 並據以實施，當不能以之限定本發明之專㈣g，即大凡依 本發明所揭示之精神所作之均等變化或修飾，仍應涵蓋在本 發明之專利範圍内。 201237974 【圖式簡單說明】 :iί本發明一實施例之半導體封裝結構之製造方法的結構 圖2Α、圖2Β、圖2C、圖2D、圖2£、 例之半導體封裝結構的結構剖視圖。 *月貫方也 圖3Α、圖 剖視圖。 3Β為本發料同實施狀半導㈣裝結構的結構 圖4Α、圖4Β、圖4C、圖4D、圖 明一實施例之半導體封裝結構的結構剖二圖4G為本發 【主要元件符號說明】 100 晶片封裝體 110 載板 112 上表面 120 第一金屬層 121 上表面 122 開口 123 下表面 125 第二金屬層 126 金屬接合層 130 晶片 132 主動面 201237974 134 背面 135 側面 140 封膠體 200 重配線基板 210 内電接墊 212 外電接墊 220 内連接線路 222 接地線路 230 焊球The 201237974 method includes the steps of: forming a chip package and providing a rewiring. The substrate is under the chip package and electrically connected to the chip package. Forming a chip package therein includes the steps of: providing a carrier; providing a wafer on the carrier, wherein one of the active faces of the wafer faces the carrier; forming a first metal layer covering the wafer and the carrier; forming a The colloid covers the wafer and the first metal layer; and the carrier is removed to expose the active face of the wafer and the first metal layer. One object of the present invention is to provide a semiconductor package structure comprising: a chip package comprising: a first metal layer having an opening; a wafer on the opening, wherein one of the back side of the wafer and the first metal layer An upper surface is oriented in the same direction; and a colloid covers the back surface of the wafer and the upper surface of the first metal layer, and one of the active surface of the wafer and the lower surface of one of the first metal layers are exposed to the encapsulant. And a heavy wiring substrate is disposed under the chip package and electrically connected to the active surface of the wafer. The purpose, technical contents, features and effects achieved by the present invention will be more readily understood from the following detailed description of the embodiments. [Embodiment] The detailed description is as follows, and the preferred embodiment is not intended to limit the invention. In the semiconductor package structure of the invention, the method of manufacturing the semiconductor package structure, as shown in the figure, the manufacturing method of the semiconductor package structure includes the following steps: forming the chip package 100 and providing Re-arranged just below the chip package, and electrically connecting the re-wiring substrate 200 to the solar cell package 1. Continuing the above, in the embodiment, the chip package is formed _ as shown in FIGS. 2A to 2E +,, 4· You open no. Watson, as shown in Fig. 2A, provides a carrier plate, and a seven-first-metal layer 120 is formed on one of the upper surfaces 112 of the carrier plate 110. [5 201237974 The invention relates to a semiconductor packaging technology, in particular to a package structure and a manufacturing method thereof. [Prior Art] = Semiconductor package process A, due to the trend of thin and light electronic products j can continue to increase' so that the package density will continue to increase, and continue to shrink 'f虞 size and improved packaging technology. How to develop packaging technology to improve process yield and improve heat dissipation efficiency SUMMARY OF THE INVENTION In order to solve the above problems, one of the objects of the present invention is to provide a semiconductor package structure and a method of fabricating the same that the package is packaged and then bonded to a rewiring substrate, and the package is packaged. The metal layer is disposed on the bonding surface with the substrate, which can increase the bonding force between the wafer body and the substrate to improve the process yield and the heat dissipation efficiency. One of the objects of the present invention is to provide a semiconductor package structure. The manufacturing method comprises the steps of: forming a chip package and providing a redistribution substrate under the chip package and electrically connecting to the chip package. The step of forming the chip package comprises: providing a carrier; forming a first a metal layer is formed on an upper surface of the carrier; at least one opening is formed on the first metal layer to expose a portion of the carrier; and a wafer is disposed on the exposed portion carrier, and one of the active faces of the wafer is oriented a carrier; forming a colloid-covered wafer and a first metal layer 'and removing the carrier to expose the active surface of the wafer and the first metal layer One of the objects of the present invention is to provide a semiconductor package structure manufacturing method 201237974. In one embodiment, the first metal layer 120 includes, but is not limited to, a conductive metal film, and the first metal layer 120 is disposed on the carrier plate in a press-fit manner. 110, it can be understood that, in addition to the single layer structure, the first metal layer 12 can also be a composite film layer formed by stacking a plurality of metal layers. Next, referring to FIG. 2B, at least one opening 122 is formed. A metal layer 120 is exposed to expose a portion of the upper surface 112 of the carrier 11. The method of forming the opening 122 includes dry film exposure and development. Further, as shown in FIG. 2C, a wafer 130 is disposed on the exposed portion. On the board 110, one of the active faces 32 of the wafer 130 is directed toward the carrier u, and one of the backs 34 of the wafer 130 is facing away from the carrier ι10. Next, please refer to FIG. 2D' to form a glue 140 covering the wafer 130 and the first metal layer 12A. Further, the carrier 110 is removed to expose a portion of the wafer 130 and the first metal layer 〇2, such as the active surface 132 of the wafer 130 and the lower surface 123 of the first metal layer 12, as shown in FIG. 2E. Finally, as shown in Fig. 2F, the provided redistribution substrate 2 is placed under the wafer package 1A, and the redistribution substrate 2A is electrically connected to the active surface 132 of the wafer 13A. In the embodiment, the first metal | i 2 〇 may also be formed on the upper surface 112 of the carrier 110 by deposition or electromineralization. In addition, referring to FIG. 3A, in another embodiment, before forming the encapsulant 14 to cover the wafer 13 , a second metal layer 125 is formed to cover the back surface 134 of the wafer 130 . Alternatively, as shown in FIG. 3B, the second metal layer 125 further includes a side surface 135' of the cover wafer (10), wherein the first metal layer 125 and the first metal layer (4) may be the same material. The coverage of the wafer by the metal layer can enhance the effectiveness of the leg masking. Further, the arrangement of the metal layer may be performed by adding a bonding force of a different material, for example, increasing the bonding force between the package body 140 and the rewiring substrate 2A. spear! The structure formed by the above-described production method is shown in Fig. a. As shown, the semiconductor package structure includes a wafer package and a redistribution substrate 200. The chip package 1 includes: a first metal layer 20 / . . . having an opening 122 ′ wherein the material of the first metal layer 12 包含 is included but 201237974 is not limited to copper. A wafer 130 is disposed on the opening 122, wherein a back surface 134 of the wafer 13 is oriented in the same direction as an upper surface 121 of the first metal layer 12A. And a colloid 14 covering the back surface 134 of the wafer 13 and the upper surface 121 of the first metal layer 20, and one active surface 132 of the wafer 130 and one lower surface 123 of the first metal layer 120 are exposed on the encapsulant 14〇 And a heavy wiring substrate 200 disposed under the chip package 1 and electrically connected to the active surface 132 of the wafer 13 . In the above embodiment, the redistribution substrate 2 includes a plurality of internal electrical pads 210, a plurality of external electrical pads 212, and a plurality of internal connecting lines 220, wherein the female-inner connecting circuit 220 is connected to the internal power. Connected to 21 〇, the other end is connected to the external electrical pad 212. As shown, the inner electrical pad 21A is electrically connected to the active surface 132 of the wafer 13A. The plurality of solder balls 23 are disposed on the external electrical pads 212 of the rewiring substrate 200 for electrical connection with the external device. In the embodiment, the redistribution substrate 200 is a redistribution film substrate. In one embodiment, as shown in FIG. 3A, the chip package 1 further includes a first metal layer 125 disposed on the back surface 134 of the wafer 130. In another embodiment, as shown in FIG. 3B, the second metal layer 125 further includes a side surface 35 covering the wafer, and the first metal layer 120 and the second metal layer 125 may be of the same material, such as copper. Referring to FIG. 3B, the re-wiring substrate 2 further includes at least one grounding line 222 connecting the first metal layer 12 and the inner connecting line 220. Covering the wafer with a metal layer not only provides shielding and good bonding force, but also improves the heat dissipation problem of the wafer. In still another embodiment, the step of forming the chip package 1 can also be as shown in FIGS. 4A to 4D. The difference from the above embodiment is that the wafer is first placed on the carrier and the first metal layer is covered to form the wafer, which is described in detail below. First, a carrier 110 is provided as shown in Fig. 4A'. Next, a wafer 130 is disposed on the carrier 11A, wherein one of the active faces 132 of the wafer 130 faces the carrier 110, and the face 134 of the wafer no faces away from the carrier 110. Next, referring to FIG. 4B, a "y 201237974 metal layer 120 covers the wafer 130, including but not limited to the back surface 134 covering the wafer I%, the side surface 135, and the carrier 110. Next, as shown in FIG. 4C, a colloid 140 is formed to cover the wafer 130 and the first metal layer 12A. Further, the carrier 110 is removed to expose the active surface 132 of the wafer 130 and the lower surface 123 of the first metal layer 12A, as shown in FIG. 4D. In one embodiment, the first metal layer 120 may be formed by deposition or electroplating. If formed by electroplating, before forming the first metal layer 120, further including forming a metal bonding layer 126 by sputtering, for example. The nickel 'covers the wafer 13' and the carrier 11', and after removing the carrier 110, as shown in FIG. 4E, the metal bonding layer 126 and the active surface 132 of the wafer 13 are exposed. Thereafter, as shown in Fig. 4F, the provided redistribution substrate 2 is placed under the wafer package 1A, and the redistribution substrate 2A is electrically connected to the active surface 132 of the wafer 13A. As shown in FIG. 4G, as described in the above embodiment, the redistribution substrate 2A may include at least one ground line 222 connecting the first metal layer 120 and the inner connection line 22A. According to an embodiment of the present invention, a semiconductor package structure and a method of fabricating the same, the wafer is first packaged on a re-wiring substrate, and the first metal layer is disposed on the bonding surface of the substrate. The bonding force between the chip package and the substrate can be increased to improve the process yield. In addition, the metal layer can increase the heat dissipation efficiency of the wafer and improve the EMI shielding effect. The embodiments described above are merely illustrative of the technical spirit and characteristics of the present invention, and those skilled in the art can understand the contents of the present invention and implement them according to the invention. Equivalent changes or modifications made by the spirit of the present invention should still be included in the scope of the present invention. 201237974 BRIEF DESCRIPTION OF THE DRAWINGS FIG. 2A, FIG. 2B, FIG. 2C, FIG. 2D, FIG. 2, and a structural cross-sectional view of a semiconductor package structure of the present invention. *The monthly square is also shown in Figure 3Α and the cross-sectional view. 3Β is a structure of the same material as the semi-conductive (four) mounting structure of the present invention. FIG. 4A, FIG. 4B, FIG. 4C, FIG. 4D, and FIG. 4D show the structure of the semiconductor package structure of the embodiment. FIG. 4G is the main component symbol description. 100 chip package 110 carrier 112 upper surface 120 first metal layer 121 upper surface 122 opening 123 lower surface 125 second metal layer 126 metal bonding layer 130 wafer 132 active surface 201237974 134 back 135 side 140 encapsulant 200 rewiring substrate 210 inner electric pad 212 outer electric pad 220 inner connecting line 222 grounding line 230 solder ball