TW200945527A - Package structure - Google Patents

Package structure Download PDF

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Publication number
TW200945527A
TW200945527A TW097114436A TW97114436A TW200945527A TW 200945527 A TW200945527 A TW 200945527A TW 097114436 A TW097114436 A TW 097114436A TW 97114436 A TW97114436 A TW 97114436A TW 200945527 A TW200945527 A TW 200945527A
Authority
TW
Taiwan
Prior art keywords
layer
wire
package structure
active surface
solder resist
Prior art date
Application number
TW097114436A
Other languages
Chinese (zh)
Inventor
Shih-Ping Hsu
Original Assignee
Phoenix Prec Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Phoenix Prec Technology Corp filed Critical Phoenix Prec Technology Corp
Priority to TW097114436A priority Critical patent/TW200945527A/en
Publication of TW200945527A publication Critical patent/TW200945527A/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

A package structure is disclosed, characterized by forming a solder mask layer on the substrate having bonding pads formed on at least one surface thereof, the solder mask layer being formed with openings to expose those bonding pads therefrom. A Ni/Pd layer or Ni/Pd/Au layer is formed on the bonding pads and a semiconductor chip having an active surface and an opposing non-active surface is mounted onto the solder mask layer, wherein the active surface has electrode pads formed thereon and the non-active surface is disposed on the chip-placement area. Copper wires are used to electrically connect the bonding pads with the aforementioned Ni/Pd layer or Ni/Pd/Au layer and the electrode pads, thereby providing increased density with reduced width between bonding pads and reduced costs by using copper wires for electrical connection.

Description

200945527 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種半導體裝置，尤指一種以銅導線 電性連接封裝基板及半導體晶片之封裝結構。 【先前技術】 隨著電子產業的蓬勃發展，電子產品亦逐漸邁入多功 能、高性能的研發方肖。為滿足+導體封裝#高積华度 (Integration)以及微型化（Miniaturizati〇n)的封裝 ❹:求’承载半導體晶片之封裝基板，逐漸由單層板演變成 夕層板（Multi-layer Board)，俾於有限的空間下，藉 =層間連接技術（Interlayer ―咖心）以擴大封裝曰 二反上可利用的線路面積，以因應高電子密度之積體電路 (ntegrated Circuit)的使用需求。 式封^用以承載半導體晶片之料基板係、包括有打綉 工、裝基板U尺寸封裝（csp)基板及覆晶基板（fcbga: ❹要因應微處理器、晶片組、與繪圖晶片之運算需 有線路之電路板亦需提昇其傳遞晶片訊號之品質、 頻寬、控制阻抗等功能，以因應高1/〇數封裝件的發 形成打綠Γί1A至1E圖，係為習知封裝結構之打線塾」 供m層之製法剖視圖；如第1A圖所示，首先者 封裝基板10，其至少一矣 及署表面10&具有複數打線墊10 置曰日區1 〇 2，且該打線執η ] 1Β圖 、，墊1〇1具有電鍍導線103;如| Μ圖所示，於該封 ^ 极1U之表面1〇a形成有防焊, 110818 5 200945527 11，且該防焊層u形成有開口〗 及置晶區此如第iC圖所示，藉由該電鍵導線1〇^ 線墊101上電鍍形成電鍍鎳/金(Ni/Au)層12. ^ H)圖所示，於該封襄基板1()之置晶區⑽上接置半 ¥體晶片13,該半導體晶片13 、 面13b，該作用面13a具有複數電極塾⑶，且該非 面13b以黏著層14設置於該置晶區1〇2上；如第圖所 不，於該打線塾101上之電鍍鎳/金層12以金導線 ❹性連接該半導體晶片13之電極墊m，使該半導體 13以金導線15電性連接該封裝其#彳 玎褒基板10，並以封膠材料 (Molchng corapound) 16完整覆蓋該些打線墊ι〇ι、 體晶片13及金導線15，以保護該些打線墊ι〇ι、半導 晶片13及金導線15三者不受外界環境之氧化或是應 擊而造成損毁。 ^ 惟，該打線墊101上形成電鍍鎳/金層12係藉由電鍍 導線103電鍍形成，於該封裝基板10上即必須佈設電^ 導線103 ’如此則佔用該封裝基板1〇之面積，而無心 到高密度佈線及打線墊之間的細間距之目的；且在貴金 屬原料持續攀昇的狀況下，該半導體晶片13係以金^線 15電性連接該封裝基板1〇之打線墊ι〇1，導致生產成本 增加。 因此，如何提供一種於打線墊上形成金屬層之封裝結 構，得提供高密度佈線及打線墊之間的細間距，並免除使 用金導線以降低生產成本，實已成爲目前業界亟待克服之 110818 200945527 難題。 【發明内容】 鑑於以上所述習知技術之缺點 供-種封裂結構，能降低生產成本。 的係提 鑛導線，以提高供-種封裳結構’能免除使用電 包括為其他目的’本發明揭露-種封裝結構，係 呈有防焊厚日兮 表面具有禝數打線墊，於該表面 •具有防知層，且該防焊層具有開口以顯露該200945527 IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor device, and more particularly to a package structure in which a package substrate and a semiconductor wafer are electrically connected by a copper wire. [Prior Art] With the rapid development of the electronics industry, electronic products have gradually entered the multi-function, high-performance research and development. In order to meet the +conductor package #高积化 (Integration) and miniaturization (Miniaturizati〇n) package 求: seeking 'storage substrate carrying semiconductor wafers, gradually evolved from a single-layer board to a multi-layer board, 俾In a limited space, the interlayer connection technology (Interlayer) is used to expand the available circuit area of the package to meet the needs of the use of high electron density integrated circuits. The package substrate for carrying the semiconductor wafer, including the embroiderer, the package substrate U-size package (csp) substrate, and the flip chip substrate (fcbga: the operation of the microprocessor, the chip set, and the drawing chip) The circuit board that needs to have a line also needs to improve the quality, bandwidth, and control impedance of the transmitted chip signal, so as to form a green Γ1A to 1E picture in response to the formation of a high 1/〇 package, which is a conventional package structure. A method for making a layer of m layer; as shown in FIG. 1A, the first package substrate 10, at least one of which has a surface 10& has a plurality of wire pads 10 placed in a day zone 1 〇 2, and the wire is n 1Β, the pad 1〇1 has an electroplated wire 103; as shown in the figure, the surface 1〇a of the sealing electrode 1U is formed with solder resist, 110818 5 200945527 11, and the solder resist layer u is formed The opening and the crystallizing area are as shown in the i-th diagram, and the electroplated wire 1 〇 ^ wire pad 101 is plated to form an electroplated nickel/gold (Ni/Au) layer 12. ^ H) as shown in the figure A semiconductor wafer 13 is attached to the crystal region (10) of the substrate 1 (), and the semiconductor wafer 13 and the surface 13b have an active surface 13a. a plurality of electrodes 3(3), and the non-face 13b is disposed on the crystallizing region 1〇2 with an adhesive layer 14; as shown in the figure, the electroplated nickel/gold layer 12 on the wire 塾101 is connected by a gold wire The electrode pad m of the semiconductor wafer 13 is electrically connected to the package 13 by the gold wire 15 and covered by the Molchng corapound 16 to cover the wire mats and the body. The wafer 13 and the gold wire 15 protect the wire pad ι〇ι, the semiconductor wafer 13 and the gold wire 15 from being oxidized or attacked by the external environment. ^, the electroplated nickel/gold layer 12 is formed on the wire pad 101 by electroplating wire 103. On the package substrate 10, the electric wire 103 must be disposed, so that the area of the package substrate 1 is occupied. The purpose of the fine pitch between the high-density wiring and the wire bonding pad; and in the case where the precious metal material continues to climb, the semiconductor wafer 13 is electrically connected to the packaging substrate 1 by the gold wire 15 , resulting in increased production costs. Therefore, how to provide a package structure for forming a metal layer on a wire pad, to provide a fine pitch between the high-density wiring and the wire pad, and to eliminate the use of gold wires to reduce the production cost has become a difficult problem to be overcome in the industry at present 110818 200945527 . SUMMARY OF THE INVENTION In view of the shortcomings of the above-mentioned prior art, a cracking structure can be used to reduce the production cost. The system of extracting oreing the wire to improve the supply-and-selling structure can eliminate the use of electricity, including other purposes. The invention discloses a package structure which has a solder-proof thick corrugated surface with a number of wire-bonding pads on the surface. • having a layer of anti-knowledge, and the solder mask has an opening to reveal the

鑛錄/⑽1/Pd)層’係形成於該些打線塾L 二’：具：作用面及非作用面，該作用㊆具有複數電極 墊’且以該非仙面設置於該防焊層上；以及銅導線， 電性連接該打線塾上之化鐘錄/把層與電極塾。 依上述之封裝結構，該防焊層之開口復包括露出該： 裝基板之部份表面，並使該半導體晶片接置於該開口中. 表面上，·該化鍍鎳/鈀層之鎳的厚度為3#^至 的厚度為0.01/iin至0.5/zm。 又依上述之結構，復包括黏著層，係設置於該半導體 晶片之非作用面與置晶區之間；復包括封膠材料 (Molding compound) ’係完整覆蓋該些打線墊、半導體晶 片及銅導線。 本發明復提供一種封裝結構，係包括♦•封裝基板，至 少一表面具有複數打線墊，於該表面具有防焊層，且該防 知層具有開口以顯露該些打線塾；化鐘錄/纪/金 110818 7 200945527 (Ni/Pd/Au)層，係形成於該些打線墊上；半導體晶片，係 具有作用面及非作用面，該作用面具有複數電極墊，且以 該非作用面設置於該防焊層上；以及銅導線，係電性連接 該打線墊上之化鍍鎳/鈀/金層與電極墊。 • 依上述之封裝結構，該防焊層之開口復包括露出該封 裝基板之部份表面，並使該半導體晶片接置於該開口中之 表面上；該化鍍鎳/鈀/金層之鎳的厚度為3“^至2〇仁 m，鈀的厚度為〇.01#m至〇·5/ζιη，金的厚度為〇〇1至 ❹ 0. 2 /z m。 又依上述之結構，復包括黏著層，係設置於該半導體 晶片之非作用面與置晶區之間；復包括封膠材料 (M〇ldingCOmpound)，係完整覆蓋該些打線墊、半導體晶 片及銅導線。 本發明之封裝結構5係於該封裝基板之打線墊以化學 沉積形成該化鍍鎳/鈀（Ni/Pd)層或化鍍鎳/鈀/金 ⑩（Ni/Pd/Au)層，以免除習知之電鍍導線，俾以提高密度佈 線及打線墊之間的細間距；且以物料價格較低之銅導線 電性連接該半導體晶片與打線墊，俾能降低生產成本，以 提高市場競爭力。 【實施方式】 以下藉由特定的具體實施例說明本發明之實施方 式，熟悉此技藝之人士可由本說明書所揭示之内容輕易地 瞭解本發明之其他優點及功效。 [第一實施例] 8 110818 200945527 _ β參閱第2A至2E 81 ’係顯示本發明封裝結構之製法 示意圖。 如第2A圖所示，提供一封裝基板2〇，其至少一表面 20a具有複數打線塾2〇1。 • 如第2B圖所示，於該封裝基板20之表面20a形成有 防焊層2卜且該防焊層21形成有開口 2ι〇，以露出該些 打線墊201。 如第2C及2C’圖所示，於該些打線墊2〇1上由内而 ❹外依序形成化鍍鎳/鈀（”/?(1)層22(如第％圖所示）；或 於該打線墊201上由内而外依序形成化鍍鎳/鈀/金 (Ni/Pd/Au)層22’（如第2C’圖所示）；由於該打線墊2〇1 上以係如化學沉積形成該化鍍鎳/鈀層22或化鍍鎳/鈀/ 金層22，而可免除習知之電鍍導線以電鍍形成鎳/金層， 俾以提高密度佈線及打線墊之間的細間距；之後以第2C 圖所示之結構作說明。 ❹ 如第2D圖所示’於該防焊層21上接置有半導體晶片 23 ’該半導體晶片23具有作用面23a及非作用面23b , 該作用面23a具有複數電極墊23卜且該非作用面23b以 黏著層24設置於該防焊層21上。 如第2E圖所示，於該打線墊2〇1上之化鍍鎳/鈀層 22以銅導線25電性連接該半導體晶片23之電極墊231， 使該半導體晶片2 3以銅導線2 5電性連接該封裝基板 ，且使用物料價格較低之銅導線25作電性連接，俾以 降低生產成本，以提向市場競爭力；此外，並以封膠材料 110818 9 200945527 (Molding compound)26完整覆蓋該些打線墊別卜半導體 θ片23及銅導線25，藉以保護該些打線墊2〇卜半導= 曰曰 片23及銅導線25三者不受外界環境之氧化或是應力衝 擊而造成損毁。 本發明係提供-種封裳結構，係包括：封裳基板2〇， 其至少一表面20a具有複數打線墊2〇1 ’於該表面2〇a且 有防烊層2卜且該防焊層21具有開口 21()以顯露該些打 線墊201;化鍍鎳/鈀〇^/13(1)層22,係形成於該些打線墊 ❿201上；半導體晶片23，係具有作用面2知及非作用面 23b，該作用面23a具有複數電極墊231，且以該非作用 面23b設置於該防焊層21上；以及銅導線巧，係電性連 接該打線墊201上之化鍍鎳/鈀層22與電極墊231。 依上述之封裝結構，該化鍍鎳/鈀層22之鎳的厚度為 3/^至20^，鈀的厚度為〇〇1/^至〇5/^;復=括 黏著層24’係形成於該半導體晶片23之非作用面2如盥 防焊層21之間。 八 [第二實施例] 响參閱第3A至3D圖’係顯示本發明封裝結構之第二 實施例製法示意圖，與前—實施例之不同處在於該防輝層 具有開口以露出該封裝基板之打線墊及置晶區，使該半導 體晶片接置於該置晶區上。 •如第3A圖所示，提供一係如第2A圖所示之結構，且 該封裝基板20之至少一表面20a具有複數打線墊2〇1， 於該封裝基板20之表面20a形成有防焊層21，且該防焊 110818 10 200945527 層21形成有開口 210’以顯露該些打線墊2〇1及封裝基板 20之部份表面20a。 如第3B及3B，圖所示，於該些打線墊2〇1上由内而 外依序形成化鍍鎳/鈀（Ni/Pd)層22(如第3B圖所示）；或 •於該打線墊201上由内而外依序形成化鍍鎳/鈀/金 (Nl/Pd/Au)層22’（如第3B’圖所示）；之後以第圖所 示之結構作說明。 如第3C圖所示，於該防焊層21之開口 21〇,中的封 蠡裝基板20的表面20a上以黏著層24接置該半導體晶片 23之非作用面23b’以將該半導體晶片23設置於該開口 210,中。 >第3D圖所示’於該打線墊2()1上之化鑛錄/紅層 22以銅導線25電性連接該半導體晶片“之電極墊231， 使該半導體晶片23以銅導線25電性連接該封裝基板 〇 ’且以封膠材料26完整覆蓋該些打線塾2(H、半導體 晶片23及銅導線25，藉以保護該些打線塾2〇1、半導體 =3及銅導線25三者不受外界環境之氧化或是 擊而造成損毁。 本：明復提供一種封裝結構，係包括:封裝基板2〇, 至>、-表面20a具有複數打線塾2〇1，於 防焊層21，且該防焊層21 π 〇 有 熱州…二 開口 210,以顯露該些打線 塾201及封裝基板2〇之部份矣 ㈤題_22，，传形成^ &化鑛錄/把/金 曰片23你且古你 打線墊2〇1上；半導體 日日片23 ’係具有作用面23a芬兆> m a及非作用面23b，該作用面 110818 11 200945527 23a具有複數電極# 231 ’且以該非作用面挪設置於該 開2丨0中之表面20a上；以及銅導線25，係電性連接 該打線墊201上之化鍍鎳/鈀/金層22，與電極墊231。 、依上述之封裝結構，該化鍍鎳/鈀/金層22,之鎳的厚 度為3#m至20/zm，鈀的厚度為 的厚度為0.01至0. 2/z m;復包括黏著層24，係設置於該 半導體晶片23之非作用面23b與封裝基板2〇之表面2〇a 之間。 碜 本發明之封裝結構，係於該封裝基板之打線墊以化學 沉積形成該化鍍鎳/鈀（Ni/Pd)層或化鍍鎳/鈀/金 (Ni/Pd/Au)層，以免除習知之電鍍導線以電鍍形成鎳/金 層，俾以提高密度佈線及打線墊之間的細間距；且以物料 價格較低之銅導線電性連接該半導體晶片之打線墊與打 線墊上之化鍍鎳/鈀層（或化鍍鎳/鈀/金）層俾以降低生 產成本’以提高市場競爭力。 上述實施例係用以例示性說明本發明之原理及其功 效，而非用於限制本發明。任何熟習此項技藝之人士均可 在不違背本發明之精神及範疇下，對上述實施例進行修 改。因此本發明之權利保護範圍，應如後述之申請專利範 圍所列。 【圖式簡單説明】 第1A至1E圖係為習知於封裝結構之打線墊上以電鑛 導線電鍍形成打線金屬層之製法剖視示意圖； 第2A至2E圖係為本發明封裝結構之第一實施例剖視 12 110818 200945527 小忍固， 第2C圖係為第2C之另一實施例剖視示意圖； 第3A至3D圖係為本發明封裝結構之第一實施例剖視 示意圖；以及 第3B’圖係為第3B之另一實施例剖視示意圖。 【主要元件符號說明】 10、20 封裝基板 101 、 201 打線墊 102 置晶區 Ό 103 電鍍導線 l〇a 、 20a 表面 11、21 防焊層 110、210、210, 開口 12 電鍍鎳/金層 13、23 半導體晶片 131 、 231 電極墊 ⑩13a 、 23a 作用面 13b 、 23b 非作用面 14、24 黏著層 15 金導線 16、26 封膠材料 22 化鍍鎳/鈀層 22， 化鍍鎳/鈀/金層 25 銅導線 13 110818The mineral record / (10) 1 / Pd) layer is formed in the wire 塾 L two ': has: the active surface and the non-active surface, the action seven has a plurality of electrode pads ' and the non-fairy surface is disposed on the solder resist layer; And a copper wire electrically connected to the chemical clock/layer and the electrode of the wire. According to the above package structure, the opening of the solder resist layer comprises exposing: partially mounting a surface of the substrate, and placing the semiconductor wafer in the opening. On the surface, the nickel plating of the nickel/palladium layer The thickness is from 3#^ to a thickness of from 0.01/iin to 0.5/zm. According to the above structure, the adhesive layer is disposed between the non-active surface and the crystallizing region of the semiconductor wafer; and the Molding compound includes a complete covering of the bonding pads, the semiconductor wafer and the copper. wire. The present invention further provides a package structure, comprising: a package substrate, at least one surface having a plurality of wire pads, having a solder resist layer on the surface, and the anti-knowledge layer having an opening to reveal the wire bonds; / Gold 110818 7 200945527 (Ni/Pd/Au) layer is formed on the wire bonding pads; the semiconductor wafer has an active surface and a non-active surface, the active surface has a plurality of electrode pads, and the non-active surface is disposed on the And a copper wire electrically connected to the nickel-plated/palladium/gold layer and the electrode pad on the wire pad. According to the above package structure, the opening of the solder resist layer includes a portion of the surface of the package substrate exposed and the semiconductor wafer is placed on the surface of the opening; the nickel plating of the nickel/palladium/gold layer The thickness is 3"^ to 2〇仁m, the thickness of palladium is 〇.01#m to 〇·5/ζιη, and the thickness of gold is 〇〇1 to ❹0. 2 /zm. The adhesive layer is disposed between the non-active surface and the crystallizing region of the semiconductor wafer; and comprises a sealing material (M〇ldingCOmpound) for completely covering the wire bonding pads, the semiconductor wafer and the copper wire. The structure 5 is formed by chemically depositing the nickel/palladium (Ni/Pd) layer or the nickel/palladium/gold 10 (Ni/Pd/Au) layer on the wire pad of the package substrate to avoid the conventional plating wire.俾 提高 提高 提高 提高 提高 提高 提高 提高 提高 提高 提高 密度 密度 密度 密度 密度 密度 密度 密度 密度 密度 密度 密度 密度 密度 密度 密度 密度 密度 密度 密度 密度 密度 密度 密度 密度 密度 密度 密度 密度 密度 密度 密度 密度 密度 密度 密度 密度The embodiments of the present invention will be described below by way of specific embodiments. Other advantages and effects of the present invention can be readily understood by those skilled in the art from this disclosure. [First Embodiment] 8 110818 200945527 _ β Refer to 2A to 2E 81 ' is a schematic diagram showing the manufacturing process of the package structure of the present invention. As shown in FIG. 2A, a package substrate 2 is provided, at least one surface 20a having a plurality of wires 塾2〇1. • As shown in FIG. 2B, a solder resist layer 2 is formed on the surface 20a of the package substrate 20. And the solder resist layer 21 is formed with an opening 2 ι 〇 to expose the wire bonding pads 201. As shown in the 2C and 2C' drawings, the plating pads are sequentially formed on the wire bonding pads 2〇1 from the inside and the outside. Nickel/palladium ("/?(1) layer 22 (as shown in Figure 5%); or sequentially formed on the wire pad 201 from the inside to the outside of the nickel/palladium/gold (Ni/Pd/Au) layer 22' (as shown in Fig. 2C'); since the wire pad 2〇1 is formed by chemical deposition such as the nickel/palladium layer 22 or the nickel/palladium/gold layer 22, the conventional one can be dispensed with. The electroplated wires are plated to form a nickel/gold layer to increase the fine pitch between the density wiring and the wire pads; the structure shown in FIG. 2C will be described later. As shown in FIG. 2D, a semiconductor wafer 23 is attached to the solder resist layer 21. The semiconductor wafer 23 has an active surface 23a and a non-active surface 23b. The active surface 23a has a plurality of electrode pads 23 and the non-active surface 23b. The adhesion layer 24 is disposed on the solder resist layer 21. As shown in FIG. 2E, the nickel/palladium layer 22 on the wire pad 2〇1 is electrically connected to the electrode pad of the semiconductor wafer 23 by the copper wire 25. 231, the semiconductor wafer 23 is electrically connected to the package substrate by a copper wire 25, and the copper wire 25 with a lower material price is used for electrical connection, so as to reduce the production cost and provide market competitiveness; And the sealing material 110818 9 200945527 (Molding compound) 26 completely covers the wire bonding pads 243 and the copper wires 25, thereby protecting the wire bonding pads 2 半 半 = = 曰曰 及 及 及 及 及 及 及 及 及 及 及The three are not damaged by the oxidation or stress of the external environment. The present invention provides a cover structure comprising: at least one surface 20a having a plurality of wire mats 2〇1' on the surface 2〇a and having a tamper-proof layer 2 and the solder resist layer 21 has an opening 21 () to expose the wire pad 201; a nickel-plated / palladium-ruthenium / 13 (1) layer 22 is formed on the wire pad 201; the semiconductor wafer 23 has an active surface 2 The non-acting surface 23b has a plurality of electrode pads 231, and the non-active surface 23b is disposed on the solder resist layer 21; and the copper wire is electrically connected to the nickel-plated/palladium electroplated on the wire bonding pad 201. Layer 22 and electrode pad 231. According to the above package structure, the nickel of the nickel/palladium plating layer 22 has a thickness of 3/^ to 20^, and the thickness of the palladium is 〇〇1/^ to 〇5/^; and the adhesive layer 24' is formed. The non-active surface 2 of the semiconductor wafer 23 is between the solder resist layers 21. [Second Embodiment] Referring to Figures 3A to 3D, there is shown a schematic view showing a second embodiment of the package structure of the present invention, which differs from the previous embodiment in that the anti-glaze layer has an opening to expose the package substrate. The wire pad and the seeding zone are placed such that the semiconductor wafer is placed on the crystallographic region. As shown in FIG. 3A, a structure as shown in FIG. 2A is provided, and at least one surface 20a of the package substrate 20 has a plurality of wire pads 2〇1, and the surface 20a of the package substrate 20 is formed with solder resist. The layer 21 and the solder resist 110818 10 200945527 layer 21 are formed with openings 210 ′ to expose the wire pads 2 〇 1 and a portion of the surface 20 a of the package substrate 20 . As shown in FIGS. 3B and 3B, the nickel/pd (Ni/Pd) layer 22 is formed on the wire pad 2〇1 from the inside to the outside (as shown in FIG. 3B); or The wire pad 201 is sequentially formed with a nickel/palladium/gold (Nl/Pd/Au) layer 22' (as shown in FIG. 3B') from the inside to the outside; the structure shown in the figure will be described later. As shown in FIG. 3C, the non-active surface 23b' of the semiconductor wafer 23 is attached to the surface 20a of the sealing substrate 20 in the opening 21 of the solder resist layer 21 by the adhesive layer 24 to the semiconductor wafer. 23 is disposed in the opening 210, in the middle. > shown in Fig. 3D, the chemical deposit/red layer 22 on the wire pad 2 (1) is electrically connected to the electrode pad 231 of the semiconductor wafer by a copper wire 25, so that the semiconductor wafer 23 is made of a copper wire 25 Electrically connecting the package substrate 〇 ' and completely covering the wire 塾 2 (H, the semiconductor wafer 23 and the copper wire 25 with the sealing material 26, thereby protecting the wire 塾 2 〇 1, the semiconductor = 3 and the copper wire 25 The present invention is not damaged by the oxidation or attack of the external environment. Ben: Ming Fu provides a package structure, including: package substrate 2〇, to >, surface 20a has a plurality of wires 塾2〇1, in the solder mask 21, and the solder resist layer 21 π 热 has a hot state ... two openings 210 to expose the portion of the wire 塾 201 and the package substrate 2 矣 (5) _22, the formation of ^ & mine record / put /金曰片23You and the ancient you hit the wire mat 2〇1; the semiconductor daily film 23' has the action surface 23a 芬兆> ma and the non-active surface 23b, the active surface 110818 11 200945527 23a has a plurality of electrodes # 231 'and the non-acting surface is disposed on the surface 20a of the opening 2丨0; and the copper wire 25 is electrically connected a nickel-plated/palladium/gold layer 22 on the wire pad 201, and an electrode pad 231. According to the above package structure, the nickel/palladium/gold layer 22 has a thickness of 3#m to 20/zm. The thickness of the palladium is 0.01 to 0.2 / zm; and the adhesive layer 24 is disposed between the non-active surface 23b of the semiconductor wafer 23 and the surface 2〇a of the package substrate 2A. The package structure is formed by chemically depositing the nickel/palladium (Ni/Pd) layer or the nickel/palladium/gold (Ni/Pd/Au) layer on the wire pad of the package substrate to avoid the conventional plating. The wire is plated to form a nickel/gold layer to increase the fine pitch between the density wiring and the wire pad; and the copper wire with a lower material price is electrically connected to the wire pad of the semiconductor wafer and the nickel/palladium plating on the wire pad. Layer (or nickel/palladium/gold) layer to reduce production cost to increase market competitiveness. The above examples are intended to illustrate the principles of the invention and its efficacy, and are not intended to limit the invention. Those skilled in the art can modify the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be as listed in the scope of the patent application to be described later. [Simplified description of the drawings] The first embodiment of the present invention is a method for forming a wire metal layer by electroplating wire on a wire bonding pad of a package structure. 2A to 2E are cross-sectional views of a first embodiment of the package structure of the present invention 12 110818 200945527 small toughness, and 2C is a cross-sectional view of another embodiment of the 2C; 3A to 3D A schematic cross-sectional view of a first embodiment of the package structure of the present invention; and FIG. 3B' is a cross-sectional view of another embodiment of the third embodiment. [Main component symbol description] 10, 20 package substrate 101, 201 wire pad 102 crystallized area Ό 103 plating wire l〇a, 20a surface 11, 21 solder resist layer 110, 210, 210, opening 12 electroplated nickel/gold layer 13 23 semiconductor wafer 131, 231 electrode pad 1013a, 23a active surface 13b, 23b non-active surface 14, 24 adhesive layer 15 gold wire 16, 26 sealing material 22 nickel/palladium layer 22, nickel/palladium/gold plating Layer 25 copper wire 13 110818

Claims (1)

200945527 十、申請專利範圍： 1· 一種封裝結構，係包括： 子裝基板-表面具有複數打線墊，於該表 :具有防焊層’且該防焊層具有開口以顯露該些打線 塾， 域錄/把（Ni/Pd)層，係形成於該些打線墊上； 半導體晶片’係具有作用面及非作用面，該作用 面具有複數電極墊，且以該非作用面設置於該防焊層 ❿ 上；以及 銅導線，係電性連接該打線塾上之化鍵錄/把層 與電極墊。 2. 如申請專利範圍第！項之封裝結構，其中，該防焊層 之開口復包括露出該封袭基板之部份表面，並使該半 導體晶片接置於該開口中之表面上。 3. 如申請專利範圍帛！項之封裝結構，其中，該化鍵錄 /鈀層之鎳的厚度為至20_，鈀的厚度為0.01 ^ Aim 至 0.5/zm。 4. 如申請專利範圍第i項之封裝結構，復包括黏著層， 係設置於該半導體晶片之非作用面與防焊層之間。 5. 如申請專利範圍第1項之封裝結構，復包括封膠材料 (Molding compound)，係完整覆蓋該些打線墊、半導 體晶片及銅導線。 6. —種封裝結構，係包括·. 封裝基板，至少一表面具有複數打線墊，於該表 110818 14 200945527 且該防焊層具有開 以顯露該些打線 面具有防焊層， 、墊； 化鍍錄/!巴/金（Ni/Pd/Au)層，係形成於該些打線 Jx. J ·， 半導體晶片’係具有作用面及非作用面該作用 面具有複數電極墊，且以該非作用面設置於該防谭層 上，以及 銅導線，係電性連㈣打轉上之化制Μ〆金 φ 層與電極墊。 7. 如申請專利範圍帛6項之封裝結構，其中，該防焊層 之開口復包括露出該封裝基板之部份表面，並使該半 導體晶片接置於該開口中之表面上。 8. 如申請專利範圍帛6項之封裝結構，其中，該化鏡錄 /鈀/金層之鎳的厚度為3#m至2〇/；m，鈀的厚度為 0.01//〇1至0.5//111，金的厚度為〇〇1至〇.2//111。 9. 如申請專利範圍第6項之封裝結構，復包括黏著層， 係設置於該半導體晶片之非作用面與封裝基板之表 面之間。 10.如申請專利範圍第6項之封裝結構，復包括封膠材料 (Molding compound)，係完整覆蓋該些打線墊、半導 體晶片及銅導線。 110818 15200945527 X. Patent application scope: 1. A package structure, comprising: a sub-package substrate-surface having a plurality of wire mats, wherein the watch has a solder resist layer and the solder resist layer has an opening to reveal the wires, the domain A Ni/Pd layer is formed on the wire bonding pads; the semiconductor wafer has an active surface and a non-active surface, the active surface has a plurality of electrode pads, and the non-active surface is disposed on the solder resist layer And a copper wire electrically connected to the keying/putting layer and the electrode pad on the wire. 2. If you apply for a patent scope! The package structure of the article, wherein the opening of the solder resist layer comprises exposing a portion of the surface of the sealing substrate and placing the semiconductor wafer on a surface in the opening. 3. If you apply for a patent range! The package structure of the item, wherein the nickel of the chemical bond/palladium layer has a thickness of 20 Å, and the thickness of the palladium is 0.01 ^ Aim to 0.5 / zm. 4. The package structure of claim i, wherein the adhesive layer is disposed between the non-active surface of the semiconductor wafer and the solder resist layer. 5. If the package structure of claim 1 is covered, the Molding compound is included to completely cover the wire mats, the semiconductor wafers and the copper wires. 6. A package structure comprising: a package substrate, at least one surface having a plurality of wire bonding pads, the table 110818 14 200945527 and the solder resist layer having an opening to expose the wire bonding surfaces with a solder resist layer, a pad; A plated/! bar/gold (Ni/Pd/Au) layer is formed on the wire Jx. J ·, the semiconductor wafer has a working surface and a non-active surface, the active surface has a plurality of electrode pads, and the non-active The surface is disposed on the anti-tank layer, and the copper wire is electrically connected (4) to the plated φ layer and the electrode pad. 7. The package structure of claim 6 wherein the opening of the solder resist layer comprises exposing a portion of the surface of the package substrate and placing the semiconductor wafer on a surface of the opening. 8. The package structure of claim 6 wherein the thickness of the nickel/palladium/gold layer is from 3#m to 2〇/m, and the thickness of the palladium is from 0.01//〇1 to 0.5. //111, the thickness of gold is 〇〇1 to 〇.2//111. 9. The package structure of claim 6 wherein the adhesive layer is disposed between the non-active surface of the semiconductor wafer and the surface of the package substrate. 10. The package structure of claim 6 of the patent application, comprising a molding compound, which completely covers the wire bonding pads, the semiconductor wafers and the copper wires. 110818 15
TW097114436A 2008-04-21 2008-04-21 Package structure TW200945527A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI511247B (en) * 2011-07-18 2015-12-01 Advanced Semiconductor Eng Package structure and package process of semiconductor
TWI615925B (en) * 2013-03-04 2018-02-21 盧森堡商經度半導體責任有限公司 Semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI511247B (en) * 2011-07-18 2015-12-01 Advanced Semiconductor Eng Package structure and package process of semiconductor
TWI615925B (en) * 2013-03-04 2018-02-21 盧森堡商經度半導體責任有限公司 Semiconductor device
US9907175B2 (en) 2013-03-04 2018-02-27 Longitude Semiconductors S.A.R.L. Semiconductor device

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