TWI511247B - Package structure and package process of semiconductor - Google Patents

Description

Semiconductor package structure and semiconductor package process

The present invention relates to a package structure and a package process, and more particularly to a package structure and a package process that provide a good wire bonding effect.

The package of the integrated circuit is a very important part of the semiconductor back-end process. The purpose is to protect each wafer after processing and electrically connect the pads on the wafer to the printed circuit board (PCB). There are many solder joints on the printed circuit board and the chip carrier substrate, and the contact faces of these solder joints with the circuit layer of the printed circuit board or the wafer carrier substrate are subjected to surface treatment before soldering. ) or metallization. For example, a nickel-palladium (Ni/Pd) or gold-nickel (Au/Ni) bimetal layer or a nickel-palladium-gold (Ni/Pd/Au) trimetal layer can be formed on the pad of the wiring layer. And other surface treatment methods.

The present invention provides a package structure that can improve the wire bonding effect and improve the process yield.

The present invention provides a packaging process for fabricating the aforementioned package structure.

The present invention provides a semiconductor package structure including a substrate, a wafer, at least one metal laminate, and at least one copper wire. The substrate has a bearing surface, and the carrier surface is provided with at least one first pad, and the wafer has a first table The surface of the wafer and the second surface of the first surface are attached to the bearing surface of the substrate by the second surface, and the first surface is provided with at least one second pad, and the metal layer is disposed on the first pad Each metal stack includes a nickel layer, a palladium layer and a gold layer, wherein the palladium layer is between the nickel layer and the gold layer, and the nickel layer is between the palladium layer and the first pad, and the thickness of the nickel layer The copper wires are respectively connected between the second pads and the corresponding metal stacks to electrically connect the first pads of the wafer and the substrate.

The present invention provides a semiconductor package structure including a substrate, a wafer, at least a first metal stack, at least a second metal stack, at least one copper wire, and a solder ball. The substrate has a first bearing surface and corresponding a second bearing surface of the first bearing surface, and the first bearing surface is provided with at least one first pad, and the second bearing surface is provided with at least one third pad, the wafer has a first surface and is opposite to the first a second surface of a surface, the wafer is attached to the first bearing surface of the substrate by the second surface, and the first surface is provided with at least one second pad, and the first metal layer is disposed on the first pad. The second metal layer is disposed on the third metal pad, and the first metal layer and the second metal layer respectively comprise a nickel layer, a palladium layer and a gold layer, wherein the palladium layer is located between the nickel layer and the gold layer, and The nickel layer is located between the palladium layer and the first pad, and the thickness of the nickel layer is greater than or equal to 1.5 micrometers and less than or equal to 3 micrometers, and the copper wires are respectively connected between the second pads and the metal pads on the corresponding first pads. , electrically connecting the first pad of the wafer and the substrate The solder balls are disposed on the second metal stack.

The present invention provides a semiconductor package process including providing a substrate having a carrier surface and having at least one first pad on the carrier surface. form a nickel layer is disposed on each of the first pads, wherein the thickness of the nickel layer is greater than or equal to 1.5 micrometers and less than or equal to 3 micrometers, and a palladium layer is formed on each of the nickel layers to form a gold layer on each of the palladium layers. A wafer to the carrying surface. The wafer has a second surface facing the substrate and a first surface opposite to the second surface, and the first surface is provided with at least one second pad. Bonding at least one copper wire between the second pad and the corresponding metal stack to electrically connect the first pad of the wafer and the substrate.

Based on the above, the present invention sets the thickness of the nickel layer in the metal laminate to be between 1.5 micrometers and 3 micrometers to adjust the hardness of the metal laminate within the tolerance range of the process, thereby making the difficulty of wire bonding less, and the wire is less likely to be wire-bonded. The process breaks, which in turn improves process yield and improves wire bonding.

The above described features and advantages of the present invention will be more apparent from the following description.

1A is a schematic cross-sectional view of a semiconductor package structure according to an embodiment of the present invention, and FIG. 1B is a top plan view of a portion of the components of FIG. 1A. For convenience of description, FIG. 1B removes the encapsulant 150 of FIG. 1A to more clearly illustrate the overall structure of the interior of the encapsulant 150. Referring to FIG. 1A and FIG. 1B , the semiconductor package structure 100 of the present embodiment includes a substrate 110 , a wafer 120 , at least one first metal stack 130 , at least one copper wire 140 , an encapsulant 150 , and at least one gold wire . 160. The substrate 110 can be a printed circuit board having a bearing surface 112 and a bottom surface 114 opposite to the bearing surface 112. The bearing surface 112 is provided with at least one first pad 112a and a bottom. At least one fifth pad 114b is disposed on the surface 114, and at least one solder ball 114a is disposed on the fifth pad 114b. The wafer 120 has a first surface 122 and a second surface 124 opposite to the first surface 122. The wafer 120 is attached to the bearing surface 112 of the substrate 110 by the second surface 124. The first surface 122 is provided with at least one The second pad 122a, the third pad 122b, and the fourth pad 122c are connected to the third pad 122b and the fourth pad 122c to electrically connect the third pad 122b and the fourth pad 122c. . The metal laminates 130 are respectively disposed on the first pads 112a. Each of the copper wires 140 connects the corresponding second pads 122a and the first metal stack 130 to electrically connect the wafer 120 and the first pads 112a of the substrate 110.

More specifically, depending on the direction of the wire bonding, the appearance of the contacts on the second pads 122a and the first metal laminate 130 may differ. When the wire bonding direction is first to form a first pad on the second pad 122a, and then to form a second pad on the first metal layer 130, between one end of each wire 140 and the corresponding second pad 122a. A first contact is formed, and a second contact is formed between the other end of each of the wires 140 and the corresponding first metal stack 130. Or, when the wire bonding direction is first forming a first solder joint on the first metal layer 130 and then forming a second solder joint on the second pad 122a, one end of each of the wires 140 and the corresponding first metal stack A first contact is formed between the layers 130, and a second contact is formed between the other end of each of the wires 140 and the corresponding second pads 122a to electrically connect the first pads of the wafer 120 and the substrate 110. 112a. In this embodiment, the first type of wire bonding is drawn as an example.

The encapsulant 150 is disposed on the carrying surface 112 and covers the wire 140, the first metal stack 130, and the wafer 120 to provide moisture resistance thereto. Protection against oxidation and short-circuit protection.

Please refer to a partial enlarged view of FIG. 1A. In detail, the first metal stack 130 of the present embodiment includes a gold layer 132, a palladium layer 134 and a nickel layer 136, wherein the palladium layer 134 is located on the gold layer 132 and the nickel layer. Between the layers 136, the nickel layer 136 is located between the palladium layer 134 and the first pads 112a, and the thickness of the gold layer 132 is less than or equal to 0.15 microns, and the thickness of the palladium layer 134 is less than or equal to 0.3 microns, while the nickel layer 136 The thickness is greater than or equal to 1.5 microns and less than or equal to 3 microns.

2 is a cross-sectional view showing a semiconductor package structure according to another embodiment of the present invention, wherein the same components as the previous embodiment are denoted by the same reference numerals. Referring to FIG. 2, the semiconductor package structure 100 of the present embodiment further includes at least one second metal stack 114c disposed on the fifth pad 114b. Since the second metal laminate 114c and the first metal laminate 130 are applied in the same process, the composition of the first metal laminate 130 and the second metal laminate 114c are the same, and the thickness of each laminate is also the same. For example, the thickness of the gold layer 132 of the second metal stack 114c is the same as the thickness of the gold layer 132 of the first metal stack 130, which is 0.15 micrometers; the thickness of the palladium layer 134 of the second metal stack 114c and the thickness of the first metal stack 130 The palladium layer 134 has the same thickness of 0.3 microns; the thickness of the nickel layer 136 of the second metal stack 114c is the same as the thickness of the nickel layer 136 of the first metal stack 130, which is 3 microns.

3 is a schematic view showing the relationship between the hardness of the metal laminate 130 and the thickness of the nickel layer. In general, the thickness of the nickel layer in the currently used metal laminate is usually 8 μm or more, so that the corresponding metal laminate hardness is greater than 400 HV. In addition, the material of the wire 140 may include copper or gold or a surface forming an anti-oxidation The layer is palladium, which is a copper-plated palladium wire; the material of the wire 140 may also be an anti-oxidation layer composed of two or more metal elements on the surface, which may be gold or palladium. Metal elements such as platinum, rhodium, silver or nickel. Taking a copper-plated palladium wire as an example, the hardness is about 80 HV, so the hardness of the metal laminate is much larger than the hardness of the wire. Thus, in the process of wire bonding, the wire is easily broken by the pinch of the porcelain nozzle and the metal laminate, and the thickness of the nickel layer is thicker, and the surface lattice of the metal layer is also increased with the thickness of the nickel layer. The difficulty of hitting the line is improved.

In order to overcome the above problem, in the present embodiment, the upper limit of the thickness of the nickel layer 136 is set to 3 μm, and the hardness of the corresponding metal laminate 130 can be set to 180 HV or less. As a result, since the hardness of the metal laminate 130 is lowered, it contributes to an increase in the bonding effect of the wire 140 and the metal laminate 130. At the same time, since the thickness of the nickel layer 136 is relatively thin, the surface lattice of the formed metal laminate 130 is relatively small, which greatly reduces the difficulty of the wire bonding, and further improves the yield of the wire bonding.

On the other hand, in consideration of the factors of the process, the present invention can set a lower limit of 1.5 μm for the thickness of the nickel layer 136 because if the thickness is less than 1.5 μm, the plating time is too short, and excessive impurities are generated on the surface, which is disadvantageous for the wire bonding. Since a gas (such as hydrogen) is generated during the initial process of electroless plating, if the thickness of the initially formed nickel layer is thin, voids or metal oxides or hard-wearing non-pure metal substances with impurities are easily formed. On the surface thereof, the hardness of the metal laminate 130 is difficult to be well controlled. Therefore, it is recommended that the formed nickel layer 136 should be accumulated to a certain thickness or more, for example, 1.5 μm or more.

4A is a schematic diagram of the first step of a packaging process in accordance with an embodiment of the present invention. Referring to FIG. 4A, first, a substrate 110 is provided. The substrate 110 has a bearing surface 112 and a bottom surface 114 of the opposite bearing surface 112. The bearing surface 112 is provided with a plurality of first pads 112a, and the bottom surface 114 is provided with a plurality of fifth pads 114b, and then the first pads. 112A respectively form a first metal stack 130, and a second metal stack 114c may be formed on the fifth pads 114b at the same time. First, the first pads 112a are cleaned with a plasma and a surfactant, and then the first pads 112a or the fifth pads 114b are microetched with sulfuric acid. After the micro-etching step is completed, the first pad 112a or the fifth pad 114b is subjected to a pre-dipping step, for example, acidifying the surface with dilute sulfuric acid to prevent rapid oxidation of the first pad 112a in a subsequent process. Next, the first pad 112a or the fifth pad 114b is surface-activated, and a seed crystal of palladium is formed on the surface for subsequent activation. Then, a nickel layer 136 is formed on each of the first pads 112a or the fifth pads 114b by electroless plating. This embodiment can change the plating time to control the thickness of the nickel layer 136 to be between 1.5 micrometers and 3 degrees. Between microns. Of course, in other embodiments of the invention, the process temperature and the concentration of the reaction solution can also be varied to control the thickness of the nickel layer 136. Next, a palladium layer 134 is formed on each of the nickel layers 136 by electroless plating. The thickness of the palladium layer is between 0.1 micrometers and 0.3 micrometers, and a gold layer 132 is formed on each of the palladium layers 134 by electroless plating immersion plating. The thickness of the gold layer needs to be between 0.05 microns and 0.1 microns.

4B is a schematic diagram of the second step of the packaging process according to an embodiment of the present invention, and FIG. 4C is a schematic diagram of the third step of the packaging process according to an embodiment of the present invention. In step 2 shown in FIG. 4B, a wafer 120 is attached to the bearing surface. 112. Wafer 120 has a second surface 124 facing substrate 110 and a first surface 122 opposite second surface 124. A plurality of second pads 122a are disposed on the first surface 122.

Then, as shown in FIG. 4C, a plurality of wires 140 are bonded between the second pads 122a and the corresponding metal stacks 130 to electrically connect the wafers 120 and the first pads 112a of the substrate 110. The wire bonding direction may be as follows: a first solder joint is formed on the second pad 122a, the solder joint is a ball bond, and a second solder joint is formed on the metal layer 130. The solder joint is a seam. a stitch bond, the first solder joint is formed before the second solder joint, or a spherical joint is formed on the second pad 122a, and then a first solder joint is formed on the metal stack 130. The solder joint is a ball bond, and a second solder joint is formed on the second pad 122a. The solder joint is a stitch bond, and the first solder joint is formed on the second solder joint. prior to.

Finally, the encapsulant 150 is formed on the carrying surface 112 to cover the wire 140, the metal stack 130 and the wafer 120, and a plurality of solder balls 114a are disposed on the fifth pad 114b to substantially complete the packaging process.

In summary, in order to reduce the hardness of the metal laminate, the present invention reduces the difficulty of wire bonding and thereby improves the process yield, and reduces the thickness of the nickel layer to change the hardness of the metal laminate. When the nickel layer is formed, the time of electroless plating, the concentration of the reaction liquid or the process temperature can be changed to control the thickness of the metal laminate, so that the hardness of the metal laminate can be reduced within the range permitted by the process to achieve better wire bonding. Bonding effect improves the yield of the packaging process.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art does not deviate. In the spirit and scope of the present invention, the scope of protection of the present invention is defined by the scope of the appended claims.

100‧‧‧Semiconductor package structure

110‧‧‧Substrate

112‧‧‧ bearing surface

112a‧‧‧first mat

114‧‧‧ bottom

114a‧‧‧ solder balls

114b‧‧‧5th pad

114c‧‧‧Second metal laminate

120‧‧‧ wafer

122‧‧‧ first surface

122a‧‧‧second mat

122b‧‧‧ third mat

122c‧‧‧fourth pad

124‧‧‧ second surface

130‧‧‧First metal laminate

132‧‧‧ gold layer

134‧‧‧Palladium layer

136‧‧‧ Nickel layer

140‧‧‧ copper wire

150‧‧‧Package colloid

160‧‧‧ gold wire

1A is a schematic cross-sectional view showing a semiconductor package structure according to an embodiment of the present invention.

Figure 1B is a top plan view of a portion of the components of Figure 1A.

2 is a cross-sectional view showing a semiconductor package structure according to another embodiment of the present invention.

Figure 3 is a schematic illustration of the relationship between the hardness of a metal laminate and the thickness of its nickel layer.

4A is a schematic diagram of the first step of a packaging process in accordance with an embodiment of the present invention.

4B is a schematic diagram of the second step of the packaging process in accordance with an embodiment of the present invention.

4C is a schematic diagram of the third step of the packaging process in accordance with an embodiment of the present invention.

100‧‧‧Semiconductor package structure

110‧‧‧Substrate

112‧‧‧ bearing surface

112a‧‧‧first mat

114‧‧‧ bottom

114a‧‧‧ solder balls

114b‧‧‧5th pad

120‧‧‧ wafer

122‧‧‧ first surface

122a‧‧‧second mat

124‧‧‧ second surface

130‧‧‧First metal laminate

132‧‧‧ gold layer

134‧‧‧Palladium layer

136‧‧‧ Nickel layer

140‧‧‧ copper wire

150‧‧‧Package colloid

160‧‧‧ gold wire

Claims (18)

A semiconductor package structure comprising: a substrate having a bearing surface, wherein the carrier surface side is embedded with at least one first pad; and a wafer having a first surface and a second surface opposite to the first surface The wafer is attached to the bearing surface of the substrate by the second surface, and the first surface is provided with at least one second pad; at least one metal layer is disposed on the first pad, each metal The laminate includes a nickel layer, a palladium layer and a gold layer, wherein the palladium layer is between the nickel layer and the gold layer, and the nickel layer is between the palladium layer and the first pad, and the nickel The thickness of the layer is greater than or equal to 1.5 microns, less than 3 microns, wherein the hardness of the metal laminate is less than or equal to 180 HV; and at least one copper wire is respectively connected between the second pad and the corresponding metal laminate to be electrically The wafer is connected to the first pad of the substrate. The semiconductor package structure of claim 1, wherein one end of each copper wire forms a first contact with the corresponding second pad, and the other end of each copper wire and the corresponding one A second contact is formed between the metal laminates, the first contact is a ball bond, the second contact is a stitch bond, and the first contact is formed on the second connection Before the point. The semiconductor package structure of claim 1, wherein one end of each copper wire forms a first contact with the corresponding metal laminate, and the other end of each copper wire and the corresponding one A second contact is formed between the two pads, the first contact is a ball bond, and the second connection The point is a stitch bond, and the first contact is formed before the second contact. The semiconductor package structure of claim 1, wherein the surface of each of the copper wires forms an anti-oxidation layer of palladium, that is, a copper-plated palladium wire. The semiconductor package structure of claim 1, wherein an anti-oxidation layer is formed on the surface of each of the copper wires, and the anti-oxidation layer is composed of two or more metal elements, such as gold, palladium, and platinum. , bismuth, silver or nickel. The semiconductor package structure of claim 1, wherein the palladium layer has a thickness of less than or equal to 0.3 μm. The semiconductor package structure of claim 1, wherein the gold layer has a thickness of less than or equal to 0.15 micrometers. The semiconductor package structure of claim 1, wherein the first surface of the wafer further comprises a third pad and a fourth pad, the semiconductor package structure further comprising at least one gold wire respectively connected to the The third pad and the fourth pad electrically connect the third pad and the fourth pad. A semiconductor package structure comprising: a substrate having a bearing surface and a bottom surface corresponding to the bearing surface, wherein at least one first pad is embedded in the bearing surface side, and at least one fifth pad is disposed on the bottom surface a wafer having a first surface and a second surface opposite to the first surface, the wafer being attached to the first surface of the substrate by the second surface a bearing surface, and the first surface is provided with at least one second pad; at least one first metal layer is disposed on the first pad, and at least one second metal layer is disposed on the fifth pad, The first metal stack and the second metal stack respectively comprise a nickel layer, a palladium layer and a gold layer, wherein the palladium layer is located between the nickel layer and the gold layer, and the nickel layer is located in the palladium layer Between the first pads, the nickel layer has a thickness of 1.5 μm or more and 3 μm or less; at least one copper wire is respectively connected to the second pad and the corresponding metal pad on the first pad. The first pad is electrically connected to the wafer and the substrate; and at least one solder ball is disposed on the second metal stack. The semiconductor package structure of claim 9, wherein the surface of each of the copper wires forms an anti-oxidation layer of palladium, that is, a copper-plated palladium wire. The semiconductor package structure according to claim 9, wherein an anti-oxidation layer is formed on the surface of each of the copper wires, and the anti-oxidation layer is composed of two or more metal elements, and the metal element is gold, palladium or platinum. , bismuth, silver or nickel metal elements. The semiconductor package structure of claim 9, wherein the palladium layer has a thickness of less than or equal to 0.3 μm. The semiconductor package structure of claim 9, wherein the gold layer has a thickness of less than or equal to 0.15 micrometers. The semiconductor package structure of claim 9, wherein the hardness of the first metal layer or the second metal layer is less than or equal to 180HV. A semiconductor packaging process includes: providing a substrate having a bearing surface, wherein the bearing surface is provided with at least one first pad; forming a nickel layer on each of the first pads, wherein the thickness of the nickel layer 1.5 μm or more and less than 3 μm; forming a palladium layer on each nickel layer; forming a gold layer on each palladium layer, wherein the nickel layer, the palladium layer and the gold layer define a metal stack, The metal laminate has a hardness of less than or equal to 180 HV; a wafer is attached to the carrying surface, the wafer has a second surface facing the substrate and a first surface opposite to the second surface, the first surface is disposed Having at least one second pad; and bonding at least one copper wire between the second pad and the corresponding gold layer to electrically connect the wafer and the first pad of the substrate, wherein the nickel is formed Before the first pad, the layer further comprises a first pad surface activation process, and a seed crystal of palladium is formed on the surface of the first pad. The semiconductor packaging process of claim 15, wherein the method of forming the nickel layer comprises electroless plating. The semiconductor packaging process of claim 15, wherein the method of forming the palladium layer comprises electroless plating. The semiconductor packaging process of claim 15, wherein the method of forming the gold layer comprises immersion coating.