TW200425448A - Wafer level chip scale package with redistribution wires by wire bonding and method for manufacturing the same - Google Patents

Abstract

A wafer level chip scale package with redistribution wires by wire bonding comprises a chip, a plurality of redistribution wires formed by wire-bonding and at least a dielectric upholder. The chip has a bottom surface and an active surface with a plurality of bonding pads. Each redistribution wire has a connecting end, at least a bonding node and a rising tip. The connecting ends are bonded on the bonding pads. The bonding nodes are disposed on the active surface. The rising tips are raising away the active surface of the chip and supported by the dielectric upholder. Thus it is to replace a redistribution layer, a stress buffer layer, a plurality of bumps and an IC carrier.

Description

200425448 V. Description of the invention (l) [Technical field to which the invention belongs] The present invention relates to 'a wafer-level wafer size package, and more particularly to a useless redistribution circuit layer, a stress buffer layer, a bump, and a : Wafer-level wafer size package structure for carrier board. [Prior technology] Wafer level chip scaie package (WLCSP) is a miniaturized package structure whose package size is close to the wafer size. Or equivalent, the wafer-level wafer-size package structure is packaged in the wafer type during the manufacturing process. Common wafer-level ^ wafer-size package structures use solder balls or bumps as external electrical contact points due to the wafer In the chip size package structure, the internal circuit of the chip and the externally bonded printed circuit f have mismatched thermal expansion coefficient differences. After bonding, it will cause thermal stress on the chip and the in block. It may even cause solder balls or bumps: Uetalfatigue), and a stress buffer layer and a redistribution circuit layer are formed between the solder ball and the wafer, such as China's Patent Bulletin No. u: 封 U 冲 i 双 ί 片 晶"Packaging structure" reveals-seed crystal several leads I * ^ overflow secret contains a silicon wafer, the silicon wafer is formed with a dull protective layer and a plurality of conductive bumps a, using these leads to the dream wafer The stress buffer layer is used for these conductive and electrical connections. The round-level packaging structure is equipped with another layer to achieve the function of circuit redistribution. * Learn the process of film and film, increase the m-year chain, photoresistance, exposure, display In addition, another wafer-level wafer-size package structure is disclosed in Japan

200425448 V. Description of the invention (2) Disclosed in JP 2002-05071 "Semiconductor Device and Manufacturing Method" of the Patent Gazette. The wafer-level package packaging structure disclosed in the patent includes a wafer, and the wafer There is an active area formed with a solder pad, and a metal bump is formed on the welding pad to connect one end of the metal wiring, so that the metal wiring is connected to the metal bump and is supported by the building. Cantilever shape 'The other end of the metal wiring is connected to a solder ball for external bonding. The cantilever-shaped metal wiring supported by the metal bump is used to absorb the stress of the solder ball or metal bump. The bonding points of the metal bumps must be able to withstand the cantilever-shaped metal wiring and the solder balls. = The metal bumps should be sealed with a sealing resin, and the metal wiring should be connected with a strip-shaped wiring support resin film to Avoid the cantilever-shaped metal wiring and the solder balls from coming off. [Summary of the Invention] The main object of the present invention is to provide a wafer-level wafer size package structure using wire redistribution bonding wires, and a redistribution bonding wire formed by a plurality of bonding wires is formed on the active surface of a wafer. The wire system has a knot wire end, at least-solder joints and-dangling tips $. The dangling tip ends are used as external contacts of the wafer-level wafer-size package structure, and the known redistribution bonding wires are used to replace conventional ones. Redistribute circuit layers, stress buffer layers, bumps, and IC substrates. The second aspect of the present invention is to provide a wafer-level wafer ruler with a packaging structure that uses redistribution bonding wires. # Redistribution bonding wires formed with a plurality of bonding wires are formed :::: The bonding wire is formed with flexible υ tip ends as the wafer and the level chip.

200425448

External contacts, the suspended support brackets, and the use of these stress buffer layers and convex structures to increase the elastic cushioning of the dielectric brackets to replace the conventional brackets with conventional wafer-level chip-size package tips An adjacent floating tip end is beneficial to the dielectric block and the IC carrier board. Another purpose of the month is to provide a manufacturing method of round-die wafer size packaging structure using wire redistribution bonding, which is characterized in that a plurality of redistribution bonding wires are formed on the active surface of the chip. In the above, each bonding wire has a junction end, at least one solder joint and a floating tip end, and the floating tip ends are used as external contacts of the wafer-level wafer-size package structure. The redistribution bonding wire formed by the bonding wires is used. Replace the conventional redistribution circuit layer, stress buffer layer, bump and 1 (: carrier board. According to the present invention, the wafer-level wafer-size package structure using wire redistribution bonding wires is included in the wafer-level wafer-size package structure. There is a chip, a plurality of redistribution bonding wires formed by wire bonding, and at least one dielectric support member. The chip has an active surface and a back surface. The active surface is formed with a plurality of solder pads and a plurality of relay pads. Each bonding wire has a knot end, at least one solder joint, and a floating tip end. The knot ends are disposed on the solder pads, and the solder joints are coupled to the relay pads to be adjacent to the dielectric property. Care Preferably, the suspended tip ends are suspended and lifted away from the active surface of the chip. The dielectric support member is provided on the active surface of the wafer and supports the suspended tip ends of the bonding wires. The dielectric support piece and the suspended tip ends replace conventional stress buffer layers, bumps, and 1C carrier boards. In addition, the junction end of one end of the bonding wire is connected to the pad of the chip and the suspended tip of the other end is used. The terminal is externally connected to replace the conventional redistribution circuit layer and bump. 200425448 V. Description of the Invention (4) [Embodiment] Referring to the drawings, the present invention will enumerate the following embodiment descriptions.

According to the first specific embodiment of the present invention, please refer to FIGS. 1 and 2E, a wafer-level wafer size package structure using wire redistribution bonding wires, including a chip 11 and redistribution formed by a plurality of wires. The bonding wire 1440 and at least one dielectric brace 1220. The chip has an active surface 丨 1 and a back surface 112 ′. The active surface is formed with a plurality of bonding pads 113 on the active surface 111. A plurality of connection pads 13m and a plurality of relay pads 132 are formed by a metal layer 130. The connection pads 131 are combined with the solder pads 113, and the relay / pads 132 are adjacent to the dielectric support member. 120. Each redistribution bonding wire 140 has a junction end 141, a welding joint 142, and a floating tip end 143. The junction ends 141 are fixed to the connection pads 131 on the bonding pads 113. Section 1 4 2 is coupled to the relay pad 132 'adjacent to the dielectric support member 2 0 so that the suspended tip ends 143 are set on the wafer 1 10 and the suspended tips of the redistribution fresh line 140 The end 43 is suspended from the active surface of the wafer 11 and extends obliquely to the dielectric support 1 20, The dielectric supporting member 12 〇β is again on the active surface 111 of the chip 110 and supports the redistribution = line 140 > suspended tip 143, using the suspended tip J43 and the dielectric The supporting member 120 serves as a stress buffer for the wafer-level wafer size package structure 100 and the outside. The redistribution bonding wires 14 are used to connect with the 2 pads 11 3 of the wafer and the redistribution bonding wires 1 are used. The suspended tip end 143 of 40 is used for external bonding to achieve a level 2 chip size package using redistribution bonding wires 丨 40 for line redistribution. Preferably, the redistribution bonding wires 14 are covered with a plating layer 150, such as solder, to protect the junction ends 141, the 200425448, the fifth invention description (5) = 142, the connection pads 131, and the These relay pads 132 are added to the outer diameter of the bonding wire 140 to improve the reliability of the crystal structure 100. Said / i Ren Ding Nai, Xiangguosha, some redistribution fresh line 140 is a redistribution circuit layer, stress buffer layer, bump and board that can replace the conventional wafer-level wafer size structure. The wafer-level wafer size package The structure 100 has the effect of manufacturing with existing wire packaging equipment at low cost. The du wire ends 141 of the redistribution bonding wires 140 are used as external endpoints, and the bearing stress is first distributed to the bonding wires 142 and the relay pads 132. The joint will not directly act on the bonding pad 113. Even if the solder joints 142 are detached from the relay pads 132 or the relay pads 132 fall off from the active surface 111 of the chip 110, the electrical connection can still be maintained. Compared with the conventional wafer-level wafer size package structure with bumps, the wafer-level wafer size package structure of the present invention is more stress buffering and low, because the conventional bump ^ will be disconnected due to stress. Cost effectiveness. The manufacturing method of the wafer-level wafer size package structure 100 using the wire redistribution bonding wire of the present invention is described in detail below. Please refer to FIG. 2a, which provides one wafer 110 and multiple wafers 110. A wafer is formed, and the dielectric supporter 20 is formed on the active surface 111 of the wafer 110. The dielectric supporter 120 is provided on the screen by screen printing or photographic development technology. The active surface 111 of the wafer 110 has a thickness between 30 and 500 / zm, preferably between 60 and 180 // m. In this embodiment, the dielectric support 12 is formed by printing. Dielectric tapes such as silicone, rubber, or polyimide can be linear, gate-shaped, or round, and referring to FIG. 2B, the metal layer 130 is formed on the active surface 111 of the chip 11. The metal layer 130 is formed by a money ore method

200425448 V. Description of the invention (6) On the active surface 111 of the wafer 110, the metal layer 130 covers the pads 113 and the dielectric supporter 20 of the wafer 110, and then As described in 2C _, a wire-bonding machine (not shown) is used to form the redistribution bonding wires 140 such as gold wires, copper wires, or aluminum wires with the junction ends 14 ι, and the junction ends 141 is combined with the metal layer 13 on the bonding pads 113, and then the redistribution bonding wires 140 are pulled over the metal layer "ο next to the dielectric support member 120, and the redistribution is performed. The bonding wires 140 are formed with the bonding joints ι42, so that the bonding joints 142 are tightly combined with the metal layer 130 adjacent to the dielectric support 120, and then the tail ends of the redistribution bonding wires 140 are pulled away from the The wafer 11 ° is formed on the active surface 111, so that the redistribution bonding wires 14o are formed with the suspended tip ends 143. Referring to FIG. 2D, the metal layer 13o is not connected with the redistribution bonding wires. Part of the junction end 141 of 140 or the joint of solder joint 142 is removed by etching, so that the metal layer 130 forms the connection pads 13m under the junction ends 141 and the solder joints 142. The relay pad 132 enables the redistribution bonding wires 14〇 ^^ to be combined with the active surface 111 of the chip 110 to achieve the effect of line redistribution, and utilizes the suspended tip ends 143 and the dielectric support. The protective member 120 serves as a stress buffer for the wafer-level wafer-size package structure 100 and the external bonding. It is better to form the plating layer 150 such as solder or other metal materials by electroplating as shown in FIG. 2E to cover The redistribution bonding wires 14 are used to protect the junction ends 141, the bonding joints 142, the connections / 塾 131, and the relay pads 132, and the redistribution bonding wires 14 are added using the plating layer 150. The outer diameter of 〇 to improve the reliability of the wafer-level wafer size package structure 丨 〇〇 The second embodiment of the present invention, please refer to Figures 3 and 4, a wafer-level wafer using redistribution of bonding wires Size package structure 200, including

200425448 V. Description of Invention (7)

There is a chip 210, a redistribution bonding wire 240 formed by a plurality of wires, and at least one dielectric supporter 220. The chip 210 has an active surface 211 and a back surface 212. The active surface 211 is formed with a plurality of bonding pads. 213, and a plurality of connection pads 231, a plurality of first relay pads 232, and a plurality of second relay pads 233 composed of a metal layer are formed on the active surface 211, and the connection pads 231 are combined with the The solder pads 213, the first relay pads 232 are adjacent to the dielectric support 220, and the second relay pads 233 are located at any position on the active surface 211 of the chip 210. The wire 240 has a knot wire end 241, a first solder joint 242, a second solder joint 244, and a suspended tip end 243. The knot wire ends 241 are fixed to the connection pads 231, and the first solder joint 242 Are connected to the first relay pads 232 adjacent to the dielectric supporter 220, so that the suspended tip ends 243 are set on the wafer 210 and suspended away from the active surface 211 of the wafer 210; Before the redistribution bonding wires 2 40 are formed to form the first welding joints 242, another second welding pad 233 is formed tightly. The second welding joints 244 are combined, and the second welding joints 244 are disposed between the corresponding junction ends 241 and the first welding joints 242 to enhance the redistribution welding wires 2 40 arc height. The stability of each redistribution bonding wire 2 4 0, the first bonding joint 242, and the second bonding joint 244 may not be located on the same straight line, so as to improve the wiring of these redistribution bonding wires 240. Flexibility, to achieve the effect of line redistribution, the dielectric supporter 22 0 is provided on the active surface 211 of the chip 21 0 and supports the suspended tip ends 2 4 3 of the bonding wire redistribution 2 40, The suspended tip ends 2 4 3 and the dielectric support member 2 2 0 are used as a stress buffer for the wafer-level chip size package structure 2 0 and external bonding. The scope of protection of the present invention shall be defined by the scope of the attached patent application

200425448 V. Description of the invention (8) shall prevail. Any changes and modifications made by those skilled in the art without departing from the spirit and scope of the present invention shall fall within the protection scope of the present invention. I ·· Page 14 200425448 Brief Description of Drawings [Simplified Description of Drawings] Figure 1: According to a first embodiment of the present invention, a three-dimensional schematic diagram of a wafer-level wafer size package structure using wire redistribution of bonding wires; Figures 2A to 2E: cross-sectional views of a wafer-level wafer size packaging structure manufacturing method using wire redistribution bonding wires according to a first embodiment of the present invention; Figures: A second specific implementation according to the present invention For example, a schematic top view of a portion of a wafer-level wafer size package structure using wire redistribution of bonding wires; and FIG.... According to a second specific embodiment of the present invention, the use of wire redistribution of fresh line wafer size wafer size A cross-sectional view of a packaged structure. The third and fourth component symbols are simply explained: I 0 0 wafer-level wafer size package structure II 〇 wafer 111 active surface 113 solder pad 1 2 0 dielectric support 130 metal layer 131 connection pad 1 4 0 redistribution bonding wire 1 41 Junction end 143 Floating tip end 150 Electric key layer 2 0 0 Wafer-level chip size package structure 11 2 Back side 132 Relay 塾 142 solder joint

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200425448 Brief description of the diagram 21 0 Chip 211 Active surface 21 2 Back surface 213 Solder pad 220 Dielectric support 231 Connection pad 232 First relay pad 233 Second relay pad 240 Redistribution bonding wire 241 Junction end 242 First Weld joint 243 Floating tip 244 Second weld joint

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Claims (1)

200425448 6. Scope of patent application [Scope of patent application] 1. A wafer-level wafer size package structure using wire redistribution bonding wires, including: a wafer having an active surface and a back surface, the active surface is formed with A plurality of welding pads; a plurality of relay pads formed on the active surface; A plurality of redistribution bonding wires formed by the bonding wires are arranged on the active surface of the chip. Each redistribution bonding wire has a knot end, a first solder joint and a suspended tip end, and the knot ends are fixedly disposed on the chip. Solder joints, the first solder joints are coupled to the relay pads, the suspended tip ends are suspended and lifted off the active surface; and at least one dielectric support member is protruded from the active part of the chip Surface for supporting the suspended tip ends of the redistribution bonding wires. 2. The wafer-level wafer size package structure using redistribution bonding wires as described in item 1 of the scope of the patent application, wherein a plurality of connections are formed between the pads and the junction ends of the redistribution bonding wires. pad. 3. The wafer-level wafer-size package structure using wire redistribution bonding wires as described in item 1 of the scope of the patent application, in addition, a plating layer is formed, and the mineral layer covers the redistribution bonding wires. 4. The wafer-level wafer-size package structure using redistribution bonding wires described in item 1 of the scope of the patent application, wherein each redistribution bonding wire further includes a second fresh section, and the second welding sections are provided in corresponding Between the junction ends and the first solder joints. 5. As described in item 4 of the scope of patent application, the use of wire to redistribute the welding wire 200425448 The scope of the patent application is a round-level wafer-size package structure, in which the junction ends, the first solder joints, and the second solder joints of the same redistribution bonding wire are arranged non-linearly. 6. The wafer-level wafer-size package structure using redistribution of bonding wires as described in item〗 of the patent application scope, wherein the first solder joints are adjacent to the dielectric support. 7. The wafer-level wafer-size package structure using redistribution of bonding wires as described in item 1 of the scope of the patent application, wherein the suspended tip ends of the bonding wires extend obliquely to the dielectric support. 8. The wafer-level wafer-size package structure using redistribution of bonding wires as described in item 1 of the scope of the patent application, wherein the dielectric support member is a dielectric tape formed by printing. 9. The wafer-level wafer size package structure using wire redistribution of bonding wires as described in item 丨 of the scope of patent application, wherein the thickness of the supporting member is between 30 and 500 β m. 10. The wafer-level wafer size package structure using wire re-distribution of bonding wires as described in item 1 of the scope of patent application, wherein the thickness of the supporting member is between 60 and 180 / zm. 11. The wafer-level wafer size package structure using redistribution bonding wires as described in item 1 of the scope of patent application, wherein the bonding wires are gold wires, copper wires or aluminum wires. 1 2. A wafer-level wafer size package structure utilizing wire redistribution and recording, including: a wafer having an active surface and a back surface, the active surface being formed with a plurality of bonding pads; and Page 18 200425448 6. The scope of the patent application is a plurality of redistribution bonding wires, which are set on the active surface of the chip. Each redistribution bonding wire has a knot end, at least one solder joint, and a floating tip end. These knot ends Fastened on the welding pads, the welding joints are formed on the active surface, and the suspended tip ends are suspended and lifted away from the active surface. 1 3. The wafer-level wafer-size package structure using wire redistribution bonding wires as described in item 12 of the scope of the patent application, which further forms a plating layer that covers the redistribution bonding wires. 14. A method for manufacturing a wafer-level wafer size package structure using wire redistribution bonding wires, comprising: providing a wafer having an active surface and a back surface, the active bread containing a plurality of bonding pads; forming a A metal layer covers the active surface of the wafer; a plurality of redistribution bonding wires are formed on the active surface of the wafer. Each redistribution bonding wire has a knot end, at least one solder joint, and a floating tip end. The knot ends are bonded to the metal layers on the solder pads, and the solder joints are fixed to the metal layer on the active surface, and the suspended tip ends are suspended and lifted away from the active surface; and the metal layer is etched, The metal layer is formed into a plurality of connection pads under the junction end and a plurality of relay pads under the solder joints. 15. The manufacturing method of a wafer-level wafer size package structure using wire redistribution bonding wires as described in item 14 of the scope of patent application, further comprising the steps of: forming at least one A dielectric support is on the active side of the chip. Page 19 200425448 VI. Application for patent scope 16 6. The manufacturing method of wafer-level wafer size package structure using wire redistribution bonding wires as described in item 14 of the scope of patent application, which further includes the steps of: etching After the metal layer, a plating layer is formed, and the plating layer covers the redistribution bonding wires. « Page 20