JP2001094228A - Mounting structure of semiconductor device - Google Patents

Mounting structure of semiconductor device

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Publication number
JP2001094228A
JP2001094228A JP26939199A JP26939199A JP2001094228A JP 2001094228 A JP2001094228 A JP 2001094228A JP 26939199 A JP26939199 A JP 26939199A JP 26939199 A JP26939199 A JP 26939199A JP 2001094228 A JP2001094228 A JP 2001094228A
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JP
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Patent type
Prior art keywords
connected
circuit board
mounting structure
ic chip
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP26939199A
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Japanese (ja)
Inventor
Tadashi Komiyama
忠 込山
Original Assignee
Seiko Epson Corp
セイコーエプソン株式会社
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Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device with a highly reliable mounting structure which does not develop crackings even if a stress caused by difference in heat expansion coefficient is applied. SOLUTION: A plurality of protruding electrodes (solder bumps) 13 formed on the bad side of an IC chip 12 for outer connection are connected to the predetermined positions of conductor patterns 141 on a flexible intermediate connection layer 14. The intermediate connection layer 14 is extended at least in the lateral direction of the connected IC chip 12. Terminal electrode parts 142 are formed on the rear side of the main surface of the intermediate layer 14 which is extended in the lateral direction. The terminal electrode parts 142 are connected to the conductor patterns 141 through via-holes, etc. That is, the protruding electrodes (solder bumps) 13 of the IC chip 12 are connected to the predetermined positions of a circuit board 11 by utilizing the terminal electrode parts 142.

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【発明の属する技術分野】本発明は、半導体装置の実装形態に係り、特にBGA(Ball Grid Array)やCSP BACKGROUND OF THE INVENTION The present invention relates to implementation of a semiconductor device, in particular BGA (Ball Grid Array) and CSP
(Chip Size Package またはChip Scale Package)の構造を有する半導体装置の実装構造に関する。 Implementation structure of a semiconductor device having (Chip Size Package or Chip Scale Package) structure.

【0002】 [0002]

【従来の技術】半導体装置の実装は、リードフレームを利用した製品の実装の他、はんだバンプ等の外部接続端子を利用して回路基板に接続する製品も多用されている。 Implementation of a semiconductor device, other products of the implementation utilizing the lead frame, and the product is also often used to connect to the circuit board by using the external connection terminals such as solder bumps. その中でも、CSP(Chip Size Package またはCh Among them, CSP (Chip Size Package or Ch
ip Scale Package)は、半導体ベアチップ表面のパッドに外部接続端子を直接形成し、基板に実装する構造を有する。 ip Scale Package) is an external connection terminal formed directly on the pad of the semiconductor bare chip surface, having a structure mounted on the substrate. 従ってCSPは、実装面積が最小限に抑えられ、 Therefore CSP is footprint is minimized,
実装面の限られた製品、あるいは携帯機器等、小型化が要求される製品に使用される。 Product or portable devices, such as the limited mounting surface, is used in products where miniaturization is required.

【0003】図3は、CSPに適用される従来の実装形態を示す断面図である。 [0003] Figure 3 is a sectional view showing a conventional implementation that is applied to the CSP. 実装基板31にCSP構成のI I of the CSP configuration on the mounting board 31
Cチップ32が実装されている。 C chips 32 are mounted. すなわち、ICチップ32の複数の外部端子(はんだバンプ)33は、実装基板31上の導電パターン311の所定箇所とクリームはんだ印刷等の技術を用いて接続される。 That is, a plurality of external terminals (solder bumps) 33 of the IC chip 32 is connected with a predetermined portion and the solder paste printing technology such as conductive pattern 311 on the mounting substrate 31. パッド34に接続されている外部端子33以外の領域は保護膜35で覆われている。 Regions other than the external terminal 33 connected to the pad 34 is covered with a protective film 35. 実装基板31上における導電パターン31 Conductive patterns 31 on the mounting board 31
1の所定箇所以外の領域には絶縁膜(保護膜)312で覆われている。 1 in the region other than the predetermined locations is covered with an insulating film (protective film) 312.

【0004】上記のようにCSP構成のICチップ32 [0004] The CSP configuration as the IC chip 32
を実装基板31に搭載する場合、ICチップ32を構成するシリコンと、実装基板31を構成するエポキシ樹脂等の熱膨張率は異なる。 When mounting on a mounting substrate 31, the silicon constituting the IC chip 32, the thermal expansion coefficient, such as an epoxy resin of the mounting substrate 31 are different. 矢印F1,F2は、それぞれ実装基板31とICチップ32の熱膨張による応力の大きさの相違を矢印の長さで簡略的に表している。 Arrows F1, F2 are the stress due to thermal expansion of the mounting substrate 31, respectively and the IC chip 32 size differences of simplified representation in the length of the arrow.

【0005】 [0005]

【発明が解決しようとする課題】外部端子(はんだバンプ)33の接続部は、上述のような応力の影響によって、クラックCRKを起こす恐れがある。 Connecting portions of the 0007 external terminals (solder bumps) 33, the influence of stress as described above, there is a risk of cracks CRK. クラックCR Crack CR
Kが発生すると、電気抵抗は増加し、最悪、オープンになるなどの不具合を招くという問題がある。 When K is generated, the electric resistance is increased and worst case, which leads to inconveniences such as will open.

【0006】本発明は上記のような事情を考慮してなされたもので、その課題は、熱膨張率の違いにより応力が加わってもクラックを発生させることなく、高信頼性の実装構造を有する半導体装置を提供することにある。 [0006] The present invention has been made in view of the circumstances described above, and an object thereof without also applied stress by the difference in thermal expansion coefficient causes cracks, with high reliability of the mounting structure to provide a semiconductor device.

【0007】 [0007]

【課題を解決するための手段】本発明の半導体装置の実装構造は、半導体チップの突起電極部と、回路基板の電極パターン部とが電気的に接続される実装構造に関し、 Mounting structure of a semiconductor device of the present invention, in order to solve the problem] has a protruding electrode portion of the semiconductor chip, relates mounting structure and the electrode pattern of the circuit board are electrically connected,
主表面において前記半導体チップの突起電極部が接続される導電パターンが形成され、少なくとも前記半導体チップの横方向に延在するフレキシブルな中間接続層と、 A conductive pattern protruding electrode portions of the semiconductor chip is connected at the main surface is formed, a flexible intermediate connectors extending transversely of at least the semiconductor chip,
前記中間接続層の横方向に延在した主表面に対する裏面側において形成された前記回路基板に接続される端子電極部とを具備したことを特徴とする。 Characterized by comprising the said intermediate connector terminal electrode portion connected to the circuit board formed on the rear surface side with respect to the horizontal direction the major surface extending in the.

【0008】本発明によれば、上記フレキシブルな中間接続層は実装において横方向に延在する。 According to the present invention, the flexible intermediate connectors extends laterally in the mounting. 好ましくは、 Preferably,
主表面の半導体チップにおける突起電極部の接続領域と、回路基板への端子電極部の接続領域は表裏で重なることなく互いに離間する。 A connection area of ​​the protruding electrode portions on the main surface of the semiconductor chip, the connection area of ​​the terminal electrode portions of the circuit board separated from each other without overlapping on the front and back. 中間接続層は、回路基板や半導体チップの応力に追従して変形する緩衝材となる。 Intermediate connectors is a buffer material that deforms following the stress of the circuit board and the semiconductor chip.

【0009】 [0009]

【発明の実施の形態】図1は、本発明の実施形態に係るCSP(Chip Size Package またはChip Scale Packag Figure 1 DETAILED DESCRIPTION OF THE INVENTION, CSP according to the embodiment of the present invention (Chip Size Package or Chip Scale Packag
e)に適用される半導体装置の実装構造を示す断面図である。 It is a sectional view showing a mounting structure of a semiconductor device applied to e). この発明では、回路基板11にCSP構成のIC In the present invention, IC of CSP structure to the circuit board 11
チップ12を実装するにあたって、フレキシブルな中間接続層14を利用する。 When mounting a chip 12, utilizing a flexible intermediate connectors 14.

【0010】ICチップ12のパッド側に形成された外部接続用の複数の突起電極(はんだバンプ)13は、中間接続層14上の導電パターン141の所定箇所と接続されている。 [0010] IC plurality of projecting electrodes of the chip 12 for the pad side formed external connection (solder bump) 13 is connected to the predetermined portion of the conductive pattern 141 on the intermediate connection layer 14.

【0011】中間接続層14は、例えばポリイミドテープの主表面上に導電パターン141が形成されている。 [0011] intermediate connector 14, for example conductive patterns 141 on the main surface of the polyimide tape are formed.
中間接続層14上は、導電パターン141の接続ポイント以外は絶縁膜143で覆われている。 The intermediate connection layer 14, other than the connection point of the conductive pattern 141 is covered with the insulating film 143. 中間接続層14 Intermediate connector 14
は、少なくとも接続されたICチップ12の横方向に延在している。 Extends laterally of the IC chip 12 which is at least connected.

【0012】この中間接続層14の横方向に延在した主表面に対する裏面側において端子電極部142が設けられている。 [0012] the terminal electrode portions 142 are provided on the rear surface side with respect to the main surface extending in the lateral direction of the intermediate connector 14. この端子電極部142は導電パターン141 The terminal electrode 142 conductive pattern 141
とビア等を介して接続されている。 It is connected through a via or the like and. すなわち、ICチップ12の突起電極(はんだバンプ)13は、回路基板1 That is, the protruding electrodes (solder bumps) 13 of the IC chip 12, the circuit board 1
1の所定箇所111との接続にこの端子電極部142を利用する構成となっている。 And it has a configuration that uses the terminal electrodes 142 for connection with the first predetermined portion 111. 所定箇所111は導電パターンの接続ポイントであり、所定箇所111以外の領域は絶縁膜(保護膜)112に覆われている。 Predetermined portion 111 is a connection point of the conductive pattern, the area other than the predetermined portion 111 is covered with an insulating film (protective film) 112.

【0013】上記構成によれば、CSP構成のICチップ12と実装基板11の熱膨張率が互いに異なっていても、熱サイクルによる互いの伸縮は直接影響し合うことはない。 With the above arrangement, it is different from the thermal expansion coefficient of the IC chip 12 and the mounting substrate 11 of the CSP structure each other, expansion from each other due to thermal cycle never interact directly. すなわち、上記フレキシブルな中間接続層14 That is, the flexible intermediate connector 14
は、実装において横方向に延在し、主表面の表裏で重なることなく互いに離間している。 Extends laterally in the mounting, are spaced apart from each other without overlapping in the front and back major surface. これにより、中間接続層14は、回路基板11やICチップ12の応力に追従して変形する緩衝材となる。 Thus, the intermediate connection layer 14 is a buffer material that deforms following the stress of the circuit board 11 and the IC chip 12. 従って、回路基板11、I Accordingly, the circuit board 11, I
Cチップ12の各接続領域A1,A2における接続部のクラック発生を抑制することができる。 It is possible to suppress the crack generation of the connection portion in the connection regions A1, A2 of the C chips 12.

【0014】図2は、本発明を適用したCSPに適用される半導体装置の実装構造を含む応用例を示す概観図である。 [0014] Figure 2 is a schematic view showing an application example, including a mounting structure of a semiconductor device applied to CSP according to the present invention. 図1と同様の箇所には同一の符号を付す。 The same portion as FIG. 1 are designated by the same reference numerals. CSP CSP
構成のICチップ12は、フレキシブルな中間接続層1 IC chip 12 structure, flexible intermediate connector 1
4を介して回路基板11に実装される。 4 is mounted on the circuit board 11 via the. このため、回路基板11にICチップ12に対応しない実装エリアSA Therefore, mounting area SA which do not correspond to the IC chip 12 to the circuit board 11
が与えられたとしても実装が可能になる場合もある。 In some cases also to allow implemented as given.

【0015】すなわち、実装エリアSAは、中間接続層14の導電パターン設計と端子電極部142の設計が許容できる範囲で変形が可能である。 [0015] That is, mounting area SA, the design of the conductive pattern design and the terminal electrode portions 142 of the intermediate connector 14 are capable of modifications in an acceptable range. ICチップ12は、 IC chip 12,
他のIC領域15の上に中間接続層14を介して乗せることができる。 It can be put through an intermediate connection layer 14 on top of the other IC region 15. これにより、実装のレイアウトの自由度が増す。 As a result, the degree of freedom in the implementation of layout is increased.

【0016】また、図示しないが、上記CSP構成のI [0016] In addition, although not shown, I of the CSP configuration
Cチップ12の代りに、CSPよりも実装面積が大きくなるBGA(Ball Grid Array)の実装に本発明を適用してもよい。 Instead of C chips 12, the present invention may be applied to implement a BGA (Ball Grid Array) mounting area than CSP increases. 回路基板への実装エリアがBGA実装面より小さくても実装を可能とすることもある。 Sometimes mounting area of ​​the circuit board to allow mounting also smaller than BGA mounting surface. もちろん、 of course,
熱サイクルにおけるクラック防止に寄与する。 Contribute to preventing cracks in the heat cycle.

【0017】以上説明したように、中間接続層14は、 [0017] As described above, the intermediate connection layer 14,
ポリイミドなどのテープを用いるので、柔らかく、相手側の形状に追従する。 Since use of tapes such as polyimide, soft, to follow the shape of the other side. よって、回路基板11への接続領域A1と、ICチップ12における接続領域A2で構成される各接続部への応力は極めて小さくなる。 Accordingly, the connection region A1 to the circuit board 11, the stress to the connecting portions formed in the connection region A2 in the IC chip 12 is extremely small.

【0018】特に、回路基板11では加熱、冷却時に発生する伸縮は著しいが、これがICチップ12に直接影響しない。 [0018] In particular, the circuit board 11 heated, although remarkable expansion which occurs during cooling, this does not directly affect the IC chip 12. これにより、CSPのようなICチップ12 Thus, IC chip 12, such as a CSP
に直接突起電極13を形成するような構成への接続部のクラック発生を抑制することができる。 Cracking of connection to such forms constitute a direct projection electrode 13 can be suppressed to.

【0019】 [0019]

【発明の効果】以上説明したように本発明によれば、I According to the present invention as described above, according to the present invention, I
Cチップの突起電極と回路基板とがフレキシブルな中間接続層を介して離間しつつ実装される。 And C chips of the protruding electrodes and the circuit board is mounted with spaced through a flexible intermediate connectors. これにより、I As a result, I
Cチップと回路基板の熱膨張率の違いによる応力の影響は中間接続層に吸収される。 Effect of C chips and circuit stress due to a difference in thermal expansion of the substrate is absorbed in the intermediate connector. また、ICチップの突起電極パターンに必ずしも従わなくてもよいので、実装エリアに自由度が与えられる。 Further, since it is not necessarily follow the protruding electrode pattern of the IC chip, the degree of freedom is given to the mounting area. この結果、各々実装に関係する接続部にクラックを発生させることなく、また、レイアウトの自由度が得られる高信頼性の実装構造を有する半導体装置の実装構造を提供することができる。 As a result, without causing cracks in the connecting portion associated with each mounting, it can also provide a mounting structure of a semiconductor device having a flexibility is highly reliable mounting structure obtained layout.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】本発明の実施形態に係るCSPに適用される半導体装置の実装構造を示す断面図である。 It is a sectional view showing a mounting structure of a semiconductor device applied to the CSP in accordance with an embodiment of the present invention; FIG.

【図2】本発明を適用したCSPに適用される半導体装置の実装構造を含む応用例を示す概観図である。 2 is a schematic view showing an application example, including a mounting structure of a semiconductor device applied to CSP according to the present invention.

【図3】CSPに適用される従来の実装形態を示す断面図である。 3 is a cross-sectional view showing a conventional implementation that is applied to the CSP.

【符号の説明】 DESCRIPTION OF SYMBOLS

11…回路基板 12…CSPを構成するICチップ 13…突起電極(はんだバンプ) 14…中間接続層 141…導電パターン 142…端子電極部 143,112…絶縁膜(保護膜) 15…他のIC領域 111…導電パターンの所定箇所 11 ... IC chip 13 ... protruding electrodes (solder bumps) to the circuit board 12 ... CSP 14 ... intermediate connector 141 ... conductive patterns 142 ... terminal electrode portions 143,112 ... insulating film (protective film) 15 ... other IC region 111 ... predetermined portion of the conductive pattern

Claims (2)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】 半導体チップの突起電極部と、回路基板の電極パターン部とが電気的に接続される実装構造に関し、 主表面において前記半導体チップの突起電極部が接続される導電パターンが形成され、少なくとも前記半導体チップの横方向に延在するフレキシブルな中間接続層と、 前記中間接続層の横方向に延在した主表面に対する裏面側において形成された前記回路基板に接続される端子電極部と、を具備したことを特徴とする半導体装置の実装構造。 And 1. A semiconductor chip protruding electrode portion, relates mounting structure and the electrode pattern of the circuit board are electrically connected, a conductive pattern protruding electrode portions of the semiconductor chip is connected at the main surface is formed , at least the the flexible intermediate connectors extending transversely of the semiconductor chip, the intermediate connector terminal electrode portion connected to the circuit board formed on the rear surface side with respect to the horizontal direction the major surface extending in the , mounting structure of a semiconductor device, characterized in that provided with the.
  2. 【請求項2】 前記中間接続層における前記半導体チップの突起電極部の接続領域と前記端子電極部の回路基板への接続領域は表裏で重なることなく互いに離間していることを特徴とする請求項1記載の半導体装置の実装構造。 2. A method according to claim, characterized in that are separated from each other without connection area to the circuit board of the intermediate connector in the semiconductor chip wherein the terminal electrode portion and the connecting region of the protruding electrode portions of which overlap on the front and back mounting structure of the semiconductor device 1 according.
JP26939199A 1999-09-22 1999-09-22 Mounting structure of semiconductor device Granted JP2001094228A (en)

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WO2002034019A1 (en) * 2000-10-20 2002-04-25 Silverbrook Research Pty. Ltd. Method of manufacturing an integrated circuit carrier
WO2002035896A1 (en) * 2000-10-20 2002-05-02 Silverbrook Research Pty. Ltd. Integrated circuit carrier with recesses
US6507099B1 (en) 2000-10-20 2003-01-14 Silverbrook Research Pty Ltd Multi-chip integrated circuit carrier

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WO2002034019A1 (en) * 2000-10-20 2002-04-25 Silverbrook Research Pty. Ltd. Method of manufacturing an integrated circuit carrier
WO2002035896A1 (en) * 2000-10-20 2002-05-02 Silverbrook Research Pty. Ltd. Integrated circuit carrier with recesses
US6507099B1 (en) 2000-10-20 2003-01-14 Silverbrook Research Pty Ltd Multi-chip integrated circuit carrier
US6710457B1 (en) 2000-10-20 2004-03-23 Silverbrook Research Pty Ltd Integrated circuit carrier
US6775906B1 (en) 2000-10-20 2004-08-17 Silverbrook Research Pty Ltd Method of manufacturing an integrated circuit carrier
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US7705452B2 (en) 2000-10-20 2010-04-27 Silverbrook Research Pty Ltd Carrier assembly for an integrated circuit
US7767912B2 (en) 2000-10-20 2010-08-03 Silverbrook Research Pty Ltd Integrated circuit carrier arrangement with electrical connection islands
US7919872B2 (en) 2000-10-20 2011-04-05 Silverbrook Research Pty Ltd Integrated circuit (IC) carrier assembly with first and second suspension means
US7936063B2 (en) 2000-10-20 2011-05-03 Silverbrook Research Pty Ltd Carrier assembly for an integrated circuit
US7974102B2 (en) 2000-10-20 2011-07-05 Silverbrook Research Pty Ltd Integrated circuit carrier assembly

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